( ESNUG 596 Item 8 ) ----------------------------------------------------- [04/12/2024]
Subject: Sassine's unfair advantage in hard design IP ... but not in soft VIP
CHI-FOON CHAN'S LEGACY: Waaaaay back in 1991 or 1992, I remember in the early days
of Design Compiler seeing the words "GTECH" and "SEQGEN" mixed in with the Verilog
netlist schematics (basic AND2/XOR2/INV and basic register/flip-flop cells).
These were Verilog gate netlists that were unmapped to any specific library.
It was from there that we technology mapped over to the LSI 10k library.
But around the late 1998 or 1999, this guy named Chi-Foon Chan told me a new
thing he had come up with, "DesignWare", where DC would map to these really nice
larger parameterized cells for things FIFOs, MACs, ECCs, Encoder/Decoders,
floating point parts, FIRs, JTAGs, memory controllers, etc. that engineers
could use as the building blocks for their chips.
The problem was these DW_libs were locked to only be used in Design Compiler.
At first, the HW designers of that day felt betrayed.
"Design Reuse is myth. It's this year's EDA hobby. They're trendy
industry buzzwords that'll be long forgotten 2 to 3 years from now.
Engineers do not want to reuse somebody else's design. Engineers
want to 'create' and they do _not_ want to modify another engineers
code to do it."
- Cliff Cummings of Sunburst Design (03/31/1999 at SNUG'99)
"I feel a little betrayed. I was asked to come into SNUG'99 to talk
about the strides Synopsys has made in interoperability. I even
wrote an article specifically about this in EE Times. Now, this
flies in the face of mix and match IP. It's really been buging me."
- Rita Glover, an analyst at EDA Today about CoreBuilder and
CoreConsultant delivering encrypted IP to customers via a
proprietary algorithm that only works with Design Compiler
(03/31/1999 at SNUG'99)
"Those little Mom & Pop IP start-ups? The French have a term for
IP. It's 'I pee on you.' At one point we counted 167 of these
little IP companies, but they're dropping like flies."
- Gary Smith, Dataquest analyst (03/31/1999 at SNUG'99)
There was even a SNPS customer rebellion where we shared secret tips on ESNUG
on how to NOT use DesignWare in our Design Compiler runs ...
"John, please keep me anon.
To disable the DW foundation licenses use:
synlib_dont_get_license = {DesignWare_Foundation}
Then use:
synlib_disable_limited_license = FALSE
To trick Synopsys into thinking its using it in Evaluation mode. When
you're done, at the last minute, you can switch back to non-Evaluation
mode to then write out your working design by using:
synlib_disable_limited_license = TRUE
along with a get_license for DW license."
- [ The Man In The Iron Mask ] from ESNUG 278 #4 (01/24/1998)
But over time Chi-Foon's Synopsys-locked DesignWare gained acceptance (simply
because DW was just too damned useful and it made so we chip designers didn't
have to reinvent the G** D*** wheel each time we designed a new chip!)
Then Aart started the big push to add "star IP" to the Synopsys DesignWare library
with his painful first "star IP" being his ill-fated DW PCI Core
Our experience with Synopsys' PCI product was quite bad (11/03/1995)
Synopsys DW PCI sucks; but LMC's PCI is fantastic! (11/16/1995)
Then my summary in 1999 of the Synopsys DesignWare PCI fiasco:
"... the Synopsys DesignWare PCI fiasco. Essentially, in mid-1995, Synopsys
and Intel made a big hoopla in the trade press about their new, joint
DesignWare PCI part. "It's the wave of the future of design!", yada,
yada, yada... A few months later, and after some major customer buy-in,
ESNUG 229 & 230 had users (another scoop!) openly reporting in technical
detail their horror stories using the DW PCI part. It simply didn't work!"
"Synopsys pulled the PCI part from the market. The 20 or so Synopsys R&D
engineers responsible eventually left the company. Aart De Geus, the
CEO of Synopsys, took personal responsibility and made sure that each
customer who had foolishly bought the DW PCI part had a working PCI
implementation in their respective chips. An honorable recovery, but
in the end there was still no way to transfer complex IP to buyers."
- from https://www.DeepChip.com/posts/0314.html (03/28/1999)
Which then triggered 4 more very painful DW PCI follow-ups!
These DW CoreBuilder/CoreConsultant tools really kinda suck (01/16/1999)
SNPS GM rebutts Cliff Cummings' trashing of SNPS DW tool (05/21/1999)
SNPS DW PCI Core still doesn't work for both FPGA & ASICs! (08/23/2000)
Clock latency problems are plaguing the SNPS DW PCI Core (09/13/2000)
After much soul-searching and tech drama, by 2002 Aart's R&D finally got a
handle on how difficult (and painful) it is to create reusable designs and
I remember Aart himself saying pithy quotes along the lines of:
"It takes 3x the effort to make a design reusable than it does
to initially create that design."
- Aart De Geus, CEO of SNPS (sometime in 2002?)
And Aart's SNPS DW R&D guys even wrote the book on design reuse.
(Not joking. They actually wrote the book on it! 1st, 2nd, 3rd editions even!)
---- ---- ---- ---- ---- ---- ---- ---- ----
SASSINE'S UNFAIR ADVANTAGE: Now, 25 years later, with all these extended growing
pains behind them, Sassine has inherited a massively crushing dominance in the
non-ARM 3rd party hardware design IP market.
That's all the red circled in light blue parts of this slide above.
That all adds up to a hefty $1.54 Billion in 2023 revenue that Sassine enjoys;
and that Cadence and Siemens EDA can NOT take away -- because it's waaaaay too
much absolute engineering hell to catch up with what Aart's DW R&D guys had
already suffered through 25 years ago.
And it's even more unfair.
That 3rd party market has a CAGR of 11% over the past 8 years -- while SNPS DW's
CAGR is 19% over those same 8 years. As long as the trends keep trending (as
tends tend to do) Sassine's DW Revenue will be waaaay beyond $1.54 Billion that
he has today -- and that's an unfair guaranteed 25% of SNPS revenue that Cadence
and Siemens EDA do NOT -- and can NEVER -- have.
---- ---- ---- ---- ---- ---- ---- ---- ----
BUT THERE'S A WEAKNESS: Yes, while Sassine enjoys an unquestionable virtual lock
in design IP -- that also locks Sassine out of Verification IP.
That is, whenever you make something, it's always good engineeering practice to
independently check what you made is what you made and correctly made.
- from Industry Gadfly: "My Cheesy Must See List for DAC 2023"
Here is where Siemens and Cadence get the last laugh. They dominate VIP sales;
because they're the only way to independently check what Synopsys DW made.
(Still, having 25% of your revenues guaranteed is a sweet deal for SNPS anyway...)
---- ---- ---- ---- ---- ---- ---- ---- ----
Related Articles
Whoa - Sassine's first real speech anywhere was his keynote at SNUG'24
WTF? - Sassine held his very first SNPS Investor Day at SNUG'24???
WTF? - Scooby Doo Mystery; why did Ravi launch a mediocre ZeBu EB2 at SNUG'24?
Whoa - Shankar is now seriously gunning for Tom Beckley's Virtuoso empire
Whoa - hands-on user benchmark confirms SNPS ASO.ai gets 50% analog migration
Zing - Sassine's unfair advantage in hard design IP ... but not in soft VIP
Join
Index
Next->Item
|
