( SNUG 99 Item 9 ) ----------------------------------------------- [3/31/99]
THE BASEMENT IS FLOODING: One of the bigger announcements Synopsys
made at SNUG'99 was the how they intended to keep adding more and more
parts to the basic Designware Foundation library. That is, as a piece
of IP becomes more mainstream in useage, Synopsys is just going to
automatically add it to the Foundation at no extra cost to users. In
this vein, Aart annouced that the DW PCI core and the DW 8051 were now
part of the DW Foundation library -- free to anyone already using that
library. This effectively means it's free to anyone using Design
Compiler due to its close ties to the DW Foundation lib! Way cool!
"We use Ambit with Synopsys. Right now the Ambit equivalent to a
DesignWare library is very weak. It didn't exist two revs ago
and it currently only contains three parts. This is why we used
Synopsys in conjunction with Ambit because of the huge DW library.
For example, we had some blocks that needed a binary encoder and
DesignWare had it."
- Thomas Tomazin of Analog Devices
"Design Reuse is myth. It's this year's EDA hobby. They're trendy
industry buzzwords that'll be long forgotten 2 to 3 years from now.
Engineers do not want to reuse somebody else's design. Engineers
want to 'create' and they do _not_ want to modify another engineers
code to do it."
- Cliff Cummings of Sunburst Design
"I feel a little betrayed. I was asked to come into SNUG to talk
about the strides Synopsys has made in interoperability. I even
wrote an article specifically about this in EE Times. Now, this
flies in the face of mix and match IP. It's really been buging me."
- Rita Glover, an analyst at EDA Today about CoreBuilder and
CoreConsultant delivering encrypted IP to customers via a
proprietary algorithm that only works with Design Compiler
"Those little Mom & Pop IP start-ups? The French have a term for
IP. It's 'I pee on you.' At one point we counted 167 of these
little IP companies, but they're dropping like flies."
- Gary Smith, Dataquest analyst
"I am told that there is a tool which allows you to put a wrapper
around Verilog code to allow it to be simulated with VHDL in VSS.
Essentially the wrapper means that the Verilog will be simulated
under VCS within the VSS simulation. The tool is free. This could
give us a free route to simulations involving VHDL and Verilog IP
(such as is required on [Project Name Deleted].) I am asking our
local support for more info."
- Euro Anon
|
|
