( ESNUG 359 Item 10 ) -------------------------------------------- [9/13/00]
Subject: ( ESNUG 358 #7 ) DW PCI Core Doesn't Work For Both FPGAs & ASICs!
> We're looking for a soft PCI master-target core. The idea is to implement
> it in Xilinx Virtex, test it, then migrate it to ASIC. The frequency we
> need is 33 MHz and the bus width 32 bits. We tried with Synopsys DWPCI.
> Unfortunately, we were unable to implement it in the Virtex.
>
> At first I used the constraints files and synthesis scripts provided by
> Synopsys, and later I changed the scripts to try different options and
> strategies. After a lot of tries, I got, in the best case, a pad-to-setup
> slack of -20 ns (after place and route). As for the synthesis software, I
> used both FPGA Compiler (Design Compiler for FPGAs) and FPGA Compiler II
> (the results were very alike in both cases). It seems there is a lot of
> combinational logic at the inputs, and, as you might imagine, I am
> somewhat disappointed.
>
> Does anybody know a good PCI soft core that can be implemented in FPGA and
> later migrated to ASIC?
>
> - Angel Ramiro
> Systems on Silicon, Inc.
From: "jok" <jok@erols.com>
With regard to PCI cores, John, it seems that the devil lies in the fact
that the clock latency can kill you when you are trying to meet the tight
clock to q times. This same clock is used for pulling data into the bus
interface.
It would appear that most core vendors assume a low latency clock, or maybe
this is not a consideration at all. The other constraint surfaces when
considering I/O timing, which can be application specific. But, the bottom
line is that core vendors may not add this I/O variable into their synthesis
scripts.
From what I have read, it would appear that many FPGA vendors are hand
tweaking the cores on the physical end to fix some of the variation in
I/O timing and clock distribution. The other issue which I don't have a
handle on is on what technique is used for the FIFO, if needed. If registers
are used, this could cause more load on the clock and variation in the
route. If a FIFO is used, the loading might be fixed, but you are still
presented with FPGA vs. ASIC timing.
The optimum solution might be to have a core with paramters on how much
margin one has in these various areas. Robbing Peter to pay Paul, if you
will. But at least you would know the budget.
Just some thoughts off the top off my head.
- Jim Jok
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