( ESNUG 358 Item 7 ) --------------------------------------------- [8/23/00]
From: Angel Ramiro <angel.ramiro@ds2.es>
Subject: Synopsys DW PCI Core Doesn't Work For Both FPGA And ASIC Designs!
Hi, John,
We're looking for a soft PCI master-target core. The idea is to implement
it in Xilinx Virtex, test it, then migrate it to ASIC. The frequency we
need is 33 MHz and the bus width 32 bits. We tried with Synopsys DWPCI.
Unfortunately, we were unable to implement it in the Virtex.
At first I used the constraints files and synthesis scripts provided by
Synopsys, and later I changed the scripts to try different options and
strategies. After a lot of tries, I got, in the best case, a pad-to-setup
slack of -20 ns (after place and route). As for the synthesis software, I
used both FPGA Compiler (Design Compiler for FPGAs) and FPGA Compiler II
(the results were very alike in both cases). It seems there is a lot of
combinational logic at the inputs, and, as you might imagine, I am somewhat
disappointed.
Does anybody know a good PCI soft core that can be implemented in FPGA and
later migrated to ASIC?
- Angel Ramiro
Systems on Silicon, Inc.
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