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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2023"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
My unofficial guide to the San Francisco DAC'23 exhibit floor. Enjoy!
EDITOR'S NOTE: This NOT just a DAC guide. This Cheesy List will get roughly
70,000 pageviews over the next 9 months because engineers use it as a quick
EDA tool shopping guide. If you're an EDA vendor and your tool is missing
(or you have more data for it) send that info to me ASAP. This offer ends
July 19th. After July 19th this document is frozen. - John Cooley
3D-IC / CHIPLET / MULTI-DIE DESIGN TOOLS
1.) NEW! -- Siemens 3D-IC flow is where Joe Sawicki suddenly reveals that
his Mentor Graphics has been doing 3D-IC designs for Intel since 2012.
Sawicki was furious to see Tom Beckley imply Cadence has the only working
integrated 3D-IC flow in ESNUG 592 #5 in 2022's Troublemaker Panel.
"Beckley showed 8 cherry picked 3D-IC design tasks, for his 8 Cadence
tools. Whereas a true, actually proven 3D-IC flow -- our Siemens flow
for 3D-IC -- has 21 3D-IC design tasks, that involve 24 Siemens tools!"
At this DAC'23, see how Siemens 3D-IC tools were used to design Intel's
EMIB with tons of silicon interposers embedded the package substrate.
Users are Broadcom, Qualcomm, Micron, MediaTek, Facebook, Samsung, Amkor
(booth 2521) Ask for Mike Walsh. Freebee: espresso & beer
Cadence Integrity 3D-IC used for simultaneously designing and analyzing
multiple chiplets. Innovus and Virtuoso and Allegro to do system-level
plan/implement/analyze any type of 2.5D/3D stacked die designs. It
competes against the SNPS 3DIC Compiler/ANSS Redhawk-SC Partnership.
Samsung, Fraunhoffer, Sony, Broadcom, and Rivos are Integrity 3D-IC users.
(booth 1511) Ask for Vinay Patwardhan. Freebie: lotto stamp
RedHawk Analysis/Fusion PnR Partnership is a super tight integration
of RedHawk-SC with Primetime-SI to work inside Aart's Fusion Compiler.
Now with lots of AI/ML stuff thrown in. That's 2 EDA vendors with
3 different db's under one hood; a difficult interop but now it works!
Does 3D-IC, machine learning, AI. "We added Tweaker ECO to this, too!"
(booth 1539) Ask for John Lee. Freebie: stuffed animal
FYI -- interesting new 3D-IC/chiplet/multi-die TEST tools in #22 below.
"ARTIFICIAL INTELLIGENCE" DIGITAL PNR TOOLS
2.) NEW(ISH) -- Cadence Cerebrus does AI-driven digital chip PnR with
reinforcement learning, that automatically optimizes PPA. Used
by "10 of top 20 semi companies and 5 of the top hyperscalers"
at 7/6/4/3nm, with at least 200 tapeouts. 60% better timing, and
40% reduced leakage, and 10X TAT engineering productivity.
Used by Mediatek, Renesas, Samsung, ST, ARM, Broadcom, Intel, GUC.
(booth 1511) Ask for Kumkum Bhatt. Freebie: lotto stamp
NEW(ISH) -- Synopsys DSO.ai is Aart's answer to Cadence Cerebrus with
exact same AI claims but for Fusion Compiler. Also has 200 tapeouts.
Also used by MediaTek, Renesas, Samsung, ST, ARM, IBM, and SK Hynix.
(booth 2456) Ask for Shankar Krishnamoorthy. Freebee: pens
POWER / IR-DROP / NOISE / THERMAL for transistors
3.) NEW! - Siemens mPower -- IC signoff EMIR for analog, digital, and 3D IC.
Rivals Ansys RedHawk SC and Totem SC, Cadence Voltus and Voltus-Fi.
(code named BlueWave.) "Totem and Voltus-Fi can't do dynamic EMIR and
craps out at 1 million transistors; our mPower Analog can do dynamic
analog EMIR on 100 million transistors, and static analog EMIR on 1.5
Billion transistors". Claims mPower Analog works with DSPF, extracted
views, Calbre extraction, Star-RC extractions, Spectre, AFS, Eldo,
HSPICE ... "anything that outputs an FSDB" ... while Voltus-Fi is
locked into a CDNS-only flow.
On the digital side, an AI chip guy using mPower Digital did dymamic
and static digital EMIR at 7nm with "1064 RISC-V processors" (which
I'm guessing is around 3 to 3.5 billion instances.) So it looks like
MENT's plan is to attack Voltus & Redhawk on capacity weaknesses, too.
See ESNUG 590-06. Users are MaxLinear, Onsemi, Hammatsu Photonics.
(booth 2521) Ask for Joe Davis. Freebee: espresso & beer
NEW(ISH) -- Cadence Celsius -- thermal solver in an electro thermal
simulation tool to rival Ansys IcePak and Siemens FloTherm for die.
"Simulate in minutes designs that require hours in other tools, with
the same level of accuracy." Celsius 3x faster simulation/design
cycle turnaround time (TAT), due to tight integration with Allegro
for PKG/PCB, Integrity for 3D-IC, Innovus for digital PnR, Virtuoso
for RFIC and full custom, and AWR Microwave Office for chiplets.
Users are ADI, SatiXfy, ST, Bosch, Tower Semi, Rohde & Schwarz, ARM
(booth 1511) Ask for Albert Zeng. Freebie: lotto stamp
Ansys Apache RedHawk is full-chip/3D-IC power integrity analysis and
sign-off, transients, simultaneous switching noise package/PCB with
distributed processing. It's the original Apache RedHawk with the
huge loyal customer base -- but now with lots of AI/ML thrown into
your analysis. Last reported scalable to 32 machines (256 cores).
"500M insts with 8B resistors plus keeping flat simulation accuracy".
Vector-based and vectorless. Clock jitter. TSMC 7nm/5nm/3nm FinFET.
Rivals claimed in 2019 that RedHawk was sold under a RedHawk-SC wrapper.
RedHawk-SC is built on SeaScape ("Gear") to give it elastic compute
and last claims "IR-drop in 6 hours on a 1 billion gate chip on a
16G machine" and "does 1000 scenarios overnight". 10/7/5/3nm.
(booth 1539) Ask for John Lee. Freebie: stuffed animal
Cadence Voltus does full-chip signoff, IR-drop, Power-Grid-Views.
Massively parallel XP "scales up to 1,024 CPUs" 1 B insts over 100s
of compute CPUs. Have done 18 billion node circuits. Does ECO's.
Works with Tempus and Sigrity chip/package/board and Innovus PnR.
Heard rumors Facebook/Google/Amazon use it for AI chips. Voltus is
TSMC 5nm certified, but RedHawk-SC is always "will be in 3 months."
"Has multiple 5nm tapeouts. All good silicon. Customers happy."
Now in TSMC 5nm ref flow. HiSilicon, Juniper, TI, ARM, Nvidia, NXP,
TSMC, GF, Samsung, STM, ON Semi, Spreadtrum, Mellanox, Renesas, ADI.
Voltus-Fi does transistor-level noise/power signoff with Quantus QRC
and MMSIM inside Virtuoso. Both Voltus & Voltus-Fi are TSMC 10/7nm.
Apache Totem and Synopsys HSim-PWRA both compete against Voltus-Fi.
(booth 1511) Ask for Ben Gu. Freebie: lotto stamp
Cadence Clarity is Anirudh's assault against the Ansys HFSS full wave
solver empire. Cloud, massive parallelization, plus a "breakthrough
new way to solve the matrix", Clarity is getting 10X faster speed using
12x to 32x less memory! (ESNUG 586 #5) It has Ansys Ajei Gopal in a
defensive war. Samsung, Teradyne, Ambarella, Global Unichip, Socionext.
(booth 1511) Ask for Gary Lytle. Freebie: lotto stamp
Cadence Celsius EC Solver (formerly 6SigmaET by Future Facilities) is
electronics cooling simulation software. Lets PCB designers solve
cooling issues. "... uses meshing technology..." Fix cooling problems
ASAP. Can analyze airflow, temp, and heat transfer in electronic
assemblies and enclosures related to natural convection, forced
convection, solar heating, and liquid cooling. User Rohde & Schwarz
(booth 1511) Ask for Sherry Hess. Freebie: lotto stamp
NEW SCHOOL RTL SIMULATORS
4.) Metrics DSIM Cloud is cloud Verilog RTL simulation-by-the-minute.
It's Costello moving his Montana VPUs into the cloud to compete against
Cadence Xcelium and Synopsys VCS FGP (Cheetah). DSIM runs custom tuned
IEEE 1800-2012 and "can take 100 M gates and run 5X to 20X faster than
Cadence Xcelium or Synopsys Cheetah VCS. At 4 Billion gates, it goes
even faster". NOT FPGA, so no super long HAPS/Zebu/Protium compiles!
First user review at ESNUG 580 #2. These hockey loving
Canadians are pioneering the 4-cents-a-minute SaaS price model in EDA.
Fun history -- Metrics is the first known EDA tool on Google Cloud.
(Panel 3:00 DAC Monday) Ask for Joe Costello. Freebie: explanations
Cadence Xcelium (Rocketick RocketSim) is parallelized System Verilog
across 100's of Intel CPUs. Benched 23X faster vs. VCS, Incisive,
Questa. Does gate and RTL sims. Compiles 1 B gates in 2 hours.
Got #3 User's Best of in 2016. (DAC'16 #3) AWS/Azure/GPC cloud.
Xcelium comes in 1K cloud packs at a discount. SystemC, e/Specman, VHDL,
low power. Users Intel, Nvidia, Renesas, Alif, AutoChips, RealTek, ST
ARM sees 5X speed-up for RTL/gate; STmicro at 8X for DFT simulation.
New this year, Xcelium Apps like Xcelium-ML for machine learning for
coverage closure and bug hunting; X-pessimism for gate level bring up;
Power Playback for parallelization of glitch accurate power estimation.
(booth 1511) Ask for Matt Graham. Freebie: lotto stamp
Siemens QuestaSim recently added a Profiler and a Visualizer for debug.
(Booth 2521) Ask for Moses Satyasekaran . Freebie: espresso & beer
Synopsys VCS FGP used to be called Cheetah. It's Aart's home grown
answer to Lip-Bu's 2016 Rocketick acquistion, also based on X86 CPUs.
Fine-grained parallelism. RTL 8X speed-up on 20 cores. Gates 12X
speed up on 20 cores. X-prop. Low power. Verdi integration.
(booth 2456) Ask for Ravi Subramanian. Freebee: pens
BUGHUNTERS
5.) Cadence JasperGold has now has 17 formal Apps. They added
- Jasper C2RTL app for checking C++ algorithms vs RTL implementation
- Jasper FPV/SEC/Coverage to verify processor- and domain-specific
computing-based designs (including RISC-V)
- Jasper Superlint/CDC/RDC for RTL designers to hand off clean RTL
for further implementation and verification
"Our new artificial intelligence kicks ass!" Jasper finds bugs 1000's
of cycles deep. Tight with Xcelium and Verisium. Tons of users gushed
about the Jasper apps years ago. (DAC'16 #1, DAC'17 #11, DAC'18 #7)
Google, Intel, ARM, Nvidia, Qualcomm, Samsung, ST, ADI, NXP, RealTek
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
Siemens OneSpin does niches that Cadence Jasper and Synopsys
VC Formal doesn't do -- plus a ton more. 360 Verify does property
checking with coverage. 360 Quantify does a full formal coverage of
your code and SVAs. 360 Safety injects faults into device code to
see if it recovers from an operational fault in the field, and still
works. SystemC App Connectivity XL App sees if your 1 billion
gate chip is interconnected properly. Their Trust tool sees if any
HW security holes. PortableCoverage App measures coverage. FPU App
does formal on IEEE 754 floating point. 26262 FMEDA tool does safety
metrics (SPFM, LFM, PMHF). And their RISC-V Verification App does
zero bug escapes and guarantees full compliance with the ISA. It
also does RISC-V compliance, SEE/MEE analysis, FPU, mutation analysis,
transactional assertions and Gap-Free. Super tight with QuestaSim.
Plus the 10 old Mentor Questa Formal formal Apps for X-checking,
RTL checks, coverage, assertion checks, property generation, CDC,
connectivity checks, post-Silicon, register checks, unreachability;
plus SLEC for safety-critical designs. "ISO 26262, baby!" Marvell,
Microsoft, Samsung, Cypress, Infineon, Nokia, Mediatek, AMD, Rambus.
(booth 2521) Ask for Chris Giles. Freebie: espresso & beer
Cadence Verisium (formerly Cadence Indago) is Anirudh's answer to Aart's
Verdi3 empire. Verisium Debug works by adding Big Data Capture to Root
Cause Analysis plus "a ton more AI stuff" -- to data mine your CDNS tool
run logs -- to "highlight causality" and correlations causing your bug
in the first place. Does HW/SW bug hunting. Verisium Manager, the AI
version of CDNS vManager to do regression optimization, failure triage,
verification planning and coverage closure, reported by DeepChip users
to save "1hr/day/engineer" (See DAC'20 #2a). Verisium Apps including
SemanticDiff, PinDown, WaveMiner, and AutoTriage that employ AI and
machine learning to reduce total debug time by as much as 6-10x.
Samsung, MediaTek, Analog Devices, TI, Bosch, Broadcom, Renesas, ST.
(booth 1511) Ask for Matt Graham. Freebie: lotto stamp
NEW! - Siemens Questa Verification IQ (VIQ) is Sawicki's snarky reply
back at Anirudh's CDNS Verisium launch. Questa VIQ does "data driven
verification with predictive and prescriptive analytics" (plus AI voodoo)
"to accelerate closure, accelerate debug turnaround time, and provide
regression efficiency." VIQ's early user list "is to be announced soon".
(booth 2521) Ask for Mark Olen. Freebie: espresso & beer
Real Intent Ascent Lint RTL and netlist rule checking and sign off.
Certified by TUV SUD for ISO-26262 (TCL2). Has high impact rules for
syntax, semantic, and style checks for low noise and ease of debug.
Integrated debugger. Rule configuration editor has severity config and
annotations, categories, filters and searches.
New is it does "total TAT minimization from start to sign-off." Supports
multiple rule sets in a single run to verify IP and new RTL in ONE run.
New targeted debugger shows related violations in the same proximity.
Also new is duplicate violations are rolled up into a group presentation.
And the user can now define four custom levels of severity. Ascent Lint
is used by Google, Hailo, Dream Chip, Alif Semiconductor, Esperanto, Groq
(booth 1525) Ask for Lisa Piper. Freebie: LED pen
Real Intent Ascent AutoFormal identifies RTL design bugs early. 10X
speedup & 3 million gate capacity. It extracts RTL "implied intent"
checks, runs formal analysis, & determines root cause errors.
Detects FSM deadlocks, dead code & range violations, etc.
(booth 1525) Ask for Lisa Piper. Freebie: LED pen
Ausdia Timevision SOC Budgeter handles the SDC time budgetting
across hierarchical boundaries. Uses SDFs, timing reports and physical
data (LEF/DEF) to produce and manage accurate timing budgets for the
blocks used in hierarchical implementation flows.
Ausdia Timevision SdcCheck does 200 checks. "your SDC + checking it's intent."
MMMC constraints, Verilog/SystemVerilog/VHDL, IEEE P.1735 encrypted RTL.
Precise file/line backtracking pinpoint in your source RTL/SDC issues.
(booth 2311) Ask for Sam Appleton. Freebie: frisbees
Excellicon ConMan formally crafts hierarchical constraints for
multi/merged mode SDC, promotion, clocking analysis. Rivals Ausdia
and Fishtail. 500+ M inst. Concert EQ is equivalence checking for
Top2Block, Top2Top (1D2S, 2D2S, 2D1S, SDC2ETM checking). Does ECO
changes, cloning, decloning, logical restructuring etc.
Excellicon ConTree does pre-CTS analysis of clocking structure for
proper clock skew groups, automatic creation of anchor buffers and
creation of CTS file. In post-CTS phase, verifies CTS for lowered
clock latency and skew.
Excellicon ConCert verifies timing intent & structural exceptions
using SVA+/formal. SDC, CTS, demotion, equiv checking. They added
timing budgeting and exceptions toolboxes to ConCert this year.
LG, Samsung, Marvell, Renesas, Qualcomm, Western Digital, Maxim, ST.
(booth 2526) Ask for Himanshu Bhatnagar. Freebie: dice cups
Synopsys Atrenta Spyglass plays heavily in killer linters, but I
don't know if they got space in the Synopsys booth this year.
Real Intent Meridian RDC finds messy reset metastability & glitch
problems. Categorizes violations, has minimum noise. Claims in
benchmark vs. rival it had MUCH few violations (200 vs 500,000),
and was 8X faster (45 min vs 6 hours). Parallel & hierarchical.
Rivals SpyGlass RDC, Questa RDC. 200M gate full RDC in 9 hrs.
Claims 20% faster runtime and 30% better RAM utilization. Improved
viewer, does save-restore incrementals, can now do targeted RDC runs
for fast debug. Used by Groq, Esperanto, Google, Hailo, Dream Chip
(booth 1525) Ask for Sanjay Thatte. Freebie: LED pens
Real Intent Verix SimFix detects & corrects X-pessimism in gate-level
sims, enabling gate-level functional sign-off. Did 100M to 350M nets.
Real Intent Meridian RXV does X-impact analysis on RTL to avoid
messes with reset schemes, diverse IPs. Shows X-optimism causing
design errors. NO simulation vectors, nor coverage analysis nor
simulation is needed. Rivals Synopsys VCS Xprop, Cadence JasperGold.
(booth 1525) Ask for Sanjay Thatte. Freebie: LED pens
Amiq Verissimo is like a Spyglass linter but just for System Verilog
testbench code. "200+ checks in assertions, dead code, language
pitfalls, code maintainability, and UVM methodology guidelines."
It can auto-correct failures, and compare reports and tracking progress
Samsung, Cisco, Qualcomm, Xilinx, Toshiba, Broadcom, Nvidea, NXP.
(booth 1326) Ask for Cristian Amitroaie. Freebie: chocolates
Siemens Visualizer (formally Avery SimXACT) automatically find X bugs
in RTL and eliminates false X's in gate-level simulation. Has gated
clock X pessimism analysis and auto generated fix deposits. It competes
with Synopsys Verdi and Cadence SimVision/Indago/Verisium. Siemens
QuestaSim/Veloce/Symphony now ships with Visualizer. "Gate simulation
bring-up productivity is more than fixing false Xs!" Broadcom, Nvidia,
MediaTek, Qualcomm, Western Digital, Cavium, HPE -- and 5,000+ others.
(booth 2521) Ask for Mark Olen. Freebie: espresso & beer
Siemens Austemper KaleidoScope does mixed-signal fault injection as
functional safety tool. Does ISO26262 automotive stuff from OneSpin.
It rivals Synopsys Z01X, Cadence Xcelium Safety. KaleidoScope does
fault injection campaigns to detect the faults. Samsung, Rambus users
(booth 2521) Ask for Ann Keffer. Freebee: espresso & beer
DIGITAL P&R
6.) Siemens Aprisa (formerly Avatar, formerly Atoptech) is the youngest 3rd place
PnR brother in a 3 brother PnR family. After many years of legal sturm und
drang, Aprisa is now a lawyer-safe ESNUG 592 #2 fiesty PnR brawler trying to
lock in a 2nm island inside the Innovus/Fusion Compiler "moat" before CDNS
and SNPS solve the 2nm chip physics problem themselves. It's a race to 2nm!
Ravi on Siemens' 14 new Aprisa PnR customers in only 12 months
At DAC'23, Aprisa PnR is definitely a "must see" because DAC is the only
non-CDNS, non-SNPS controlled open conference where you can see it.
Specifically new this year -- now TSMC/Samsung certified at 5/4/3nm;
tight correlation pre- to post-route and to Calibre sign-off has made
our "networking, HPC, low power" users happy; AI-driven macro placement
(Booth 2521) Ask for Alpesh Kothari. Freebie: espresso & beer
Cadence Innovus PnR is the #1 heavy weight champ of digital PnR. Claims
to be #1 for 5nm and "delivered the world's 1st production 3nm tapeouts."
Now working on 2nm. Innovus has "Smart Hierarchy" for "best TAT without
sacrificing PPA." The CDNS R&D guys developed "Flash PG", a language to
automatically script production power/grid configurations that compiles
in minutes. (Usually PG definitions are ad hoc, done through the GUI and
saved and replayed on later design versions -- usually messy and runtimes
can be long. "Flash PG" is a new language to spec out your power grid
going top down -- and you can compile it to new designs. It lets users
try out multiple PG combinations to dial-in IR-drop vs. area/congrestion
goals super fast.) Innovus + Joules also does glitch power optimization.
So it's no surprise that Qualcomm, Nvidia, ST, Faraday, GF, MediaTek,
ARM, Broadcom, Toshiba, Freescale, Juniper, Renesas, Maxlinear, Intel,
Spreadtrum, Silicon Labs, Sony, Cypress, ImgTec, Realtek, NXP, Meta,
Google (and one very big and very quiet "other") all use Innovus PnR.
(booth 1511) Ask for Rod Metcalfe. Freebie: lotto stamp
Synopsys Fusion Compiler is the #2 contender to the #1 CDNS Innovus PnR.
(booth 2456) Ask for Shankar Krishnamoorthy. Freebee: pens
COMPLETE CDC SIGN-OFF
7.) Real Intent Meridian CDC for low noise RTL CDC. Samsung used it's
hierarchical flow and cut # of CDC violations to review by 95-98%
and engineering time by 70%. Claims runtime cut by 8X, and memory
cut by 4X for 800M gate chip with 103 clock domains. New data
model cuts memory by 30%, noise by 5-10X. Dynamic CDC protocols.
New this year -- flat and hierarchical multimode sign-off, multimode
-aware dynamic CDC models, low noise sign-off (including handshake
and interface handling, glitch detection, and reconvergence), root
cause groups 10X faster, incremental iterations in minutes instead
of hours. Samsung, Google, Nvidia, Groq, Western Digital are users.
(Booth 1525) Ask Vikas Sachdeva. Freebie: LED Pen.
Siemens Questa CDC post-implementation, gate-level CDC analysis and
glitch detection for signoff. Low noise results due to focus on
implementation-based causes. High QoR, high scalability. ISO 26262.
Has gate-level stuff for FPGAs. "It runs in the cloud and we added a
boatload of AL/ML stuff, too!" Mediatek, Marvell, Cypress, AMD users.
(Booth 2521) Ask for Chris Giles. Freebie: espresso & beer
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 1425) Ask for Stanley Hyduke. Freebie: pens
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. 500 M inst with 1000 clocks in
8 hours. GUI user does full tracing. Handles flop duplication,
retiming and merging. Qualcomm, Nvidia, Broadcom, Mediatek, ARM
(booth 2311) Ask for Sam Appleton. Freebie: frisbee
Cadence JasperGold now has 17 formal Apps. One of them does CDC.
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
Siemens Questa Formal has 11 formal Apps. One of them does CDC.
(booth 2521) Ask for Chris Giles. Freebie: espresso & beer
SPICE / AMS / CHARACTERIZATION
8.) Cadence Spectre-X claimed to be 10x faster than old Spectre thus, if
true, it was going trash the entire SPICE ecosystem. The truth is it
did well in keeping up with Siemens BDA AFS, but it didn't wipe out AFS
at all. Massive distrubuted computing plus does AWS/Azure/GCP clouds.
New this year -- "Spectre-X is 10X faster with 5X more block level
capacity at golden SPICE accuracy." It loves complex analog, mixed-
signal and RF blocks. Does millions of post-layout parasitics with
10X more performance and 5X capacity. Scales up to 256 cores and can
leverage GPU hardware in a compute farm or on the cloud. Spectre-X
does mixed-signal with Xcelium digital (with RTL digital blocks mixed
with SPICE and/or behavioral model representations for analog blocks.)
Also this year Spectre-X seems to be going after Keysight's RF/microwave
niche. Spectre-X has an RF extension to support harmonic balance,
shooting newton , envelope and other RF/high frequency analyses for
fast and accurate verification of high frequency analog & RF circuits.
These RF Spectre XDP runs are on 256 cores across multiple machines to
allowing for bigass SPICE runs of post-layout RF/microwave designs.
For RF it does enhanced load pull analysis for high-speed I/O design.
MediaTek, Renesas, Siliconworks, Texas Instruments, Microsoft, AMD.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
Cadence Spectre-FX does FastSPICE. Claims 3X faster now from "advanced
partitioning and RC reduction" and "handles several 10s of millions of RC
parasitics and supports post-layout DSPF and extracted SPICE formats.
Transient simulations up to 32 cores. Competes against Synopsys
PrimesimPro and PrimesimXA. Spectre FX also does mixed-signal with the
Cadence Xcelium digital simulator. MediaTek, Renesas, SK hynix, Samsung
Foundry, JVC Kenwood, DB GlobalChip are Spectre FX users.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
Siemens BDA AFS claims is 2x faster than parallel SPICE simulators.
20+ M elements. TSMC 5/4/3nm certified. 2X faster. "We do a boatload
of AI/ML stuff now, plus we're in AWS/Azure/GPC cloud." and "Our hot
new AI stuff is going to give the other SPICE guys nightmares."
AFS with Solido, has 10x faster throughput for OCV vs. other SPICEs.
BDA ACE for analog characterization runs. AFS Mega does SPICE of
100+ M element mega arrays like memories. In 2020, Joe Sawicki said ...
Sawicki on his "free" AFS-XT being 5x-10x faster than Spectre-X
which resulted in ...
Users chose Sawicki's AFS-XT SPICE gambit as Best of 2020 #1a
So now Siemens AFS has over 235 customers like Samsung, MediaTek, Intel,
NXP, Broadcom, Qualcomm, SiLabs, Fujitsu, ADI, Sony, LG, Skyworks...
(Booth 2521) Ask for Francois Le Grix. Freebie: espresso & beer
Siemens Symphony Pro is Joe Sawicki's new updated answer to the market
dominant Cadence AMS Designer, and lessor Synopsys VCS AMS. All three
tools are mixed-signal; that is, they run an analog SPICE simulator plus
a digital Verilog/VHDL simulator on your design -- hence "mixed-signal".
Back in 2019, BDA Ravi's winning outside-of-box strategy to take on the
Cadence AMS Designer near-monopoly was -- as long as the customer used
Siemens BDA AFS for their SPICE -- in Siemens Symphony Pro you could use
any digital Verilog/VHDL simulator they wanted! They can use Questa or
VCS or Incisive or Xcelium or *whatever* they want to use! The result
was Siemens NO LOCK IN Symphony tool strategy got #1 of Best of 2021.
Siemens Symphony nips at Cadence AMS Designer is Best of 2020 #1e
New this year Symphony Pro has an "average 2X performance over previous
generation mixed signal simulators" and "our new intuitive visual debug
cockpit has up to 10X more productivity compared to legacy solutions".
Nvidia, Semtech, Mythic, Mixel, IDT, ST, Silicon Labs, and Invensense.
(booth 2521) Ask for Sumit Vishwakarma. Freebee: espresso & beer
Silvaco SmartSpice Pro is Dave Dutton's push into the memory
fastSPICE market. Claims "true SPICE behavior but with much faster
generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
designs with better waveform overlay results than other simulators."
Does 28/16/14/10/7nm. SmartSpice (golden), SmartSpice HPP (parallel).
Samsung and LG are users. SmartSpice PRO for SRAM simulation.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
Empyrean ALPS is a killer SPICE from a Chinese EDA company that
crushed FineSim/PrimeSim/Spectre-X in a 2022 user benchmark.
Empyrean ALPS benches 2.7X to 38.4X vs. FineSim/PrimeSim/Spectre-X
and Empyrean also kicked ass in 2020 with its ALPS-GT here with...
Empyrean ALPS-GT crushes Spectre-X and AFS-XT is Best of 2020 #1c
HiSilicon, Kilopass, Monolithic Power Systems, Ricoh, Toshiba are users.
(booth 2537) Ask for Jason Xing. Freebie: fluffy animal
Siemens Solido Characterization is an AI-enabled, production-accurate
.lib generation/verification tool. "Speeds up library characterization
and verification by weeks, using artificial intelligence. Finds trends
and outliers across PVTs. Generates .libs for new PVTs instantly." For
std cell, memory, and I/O libraries. NLDM, CCS, CCSN, CCSP, ECSM, AOCV,
LVF. New powerful validation GUI. New APIs for lots of customization.
(Booth 2521) Ask for Jeff Dyck. Freebie: espresso & beer
Cadence Liberate Trio now does cloud library characterization. Rivals
are Siliconsmart (SNPS), Kronos, and Predictor (Mentor). Maxlinear,
ARM, GF, Huawei, Dialog, Surecore, LG, Microchip all use Liberate.
(booth 1511) Ask for Seena Shankar. Freebie: lotto stamp
LibTech TurboChar competes against SiliconSmart and Liberate to
do std cell, IO, and SRAM characterization and modeling. Has
"massive parallelism", fast LVF/AOCV, improved auto-configuration.
Claims it improves linearly with more CPS, "does not level off like
queueing methods". (booth 916) Ask for Mehmet Cirit.
Silvaco Jivaro does netlist reduction for SPICE sim acceleration.
Multithreaded for DSPF/SPF netlists. Speeds up Spectre by 3X. More
accuracy. OA DM5 is supported. Silvaco Viso does quick analysis
of interconnect parasitics. Tight with Virtuoso. Silvaco Belledonne
does extracted netlist comparison -- for PDK optimization.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
Siemens Solido Variation Designer does variation-aware design for PVT
corners, 3 to 9-sigma Monte Carlo, hierarchical and sensitivity analysis.
Big thing is it cuts waaaaaaaay down on how many SPICE runs you need.
"We got cloud & AI everywhere, too!" Good for memory, std cell, analog/RF,
custom digital. TSMC, Broadcom, Nvidia, Huawei, Cypress, ARM, IBM users.
(Booth 2521) Ask for Jeff Dyck. Freebie: espresso & beer
Cadence Spectre FMC Analysis does variation aware analysis of PVT corners
on your chip. "3 to 6+ sigma yield with 10X speedup over brute force
Monte Carlo analysis." Does command-line and the Virtuoso ADE gui.
Compute farm or cloud. It works well with Liberate Trio and Tempus.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
Silvaco VarMan does Monte Carlo 3 to 8 sigma. Supports non-Gaussian.
Batch mode characteration of 100's of cells for you. 28nm FDSOI,
40 cells, 100 corners, Monte Carlo at each corner, 100's of measures,
took 173 mins using brute force MC and only 19 mins on VarMan. It
increases linearly to 6 sigma while claims Solido explodes hundreds
of times more to 6 sigma. ST Micro, Faraday, and Dolphin Integration.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
MunEDA WiCkeD analyzes SRAM cell/column/array, std cell, and analog
circuits for local variation to 9-sigma. Hierarchical and WCA.
FinFET, Bulk, Bipolar, BiCMOS. ST Micro and MunEDA published
silicon & bit cell analysis of 14nm FDSOI statistical BTI effects.
Samsung, SK Hynix, Infineon, Sanyo, Toshiba, and Altera users.
(booth 1407) Ask for Andreas Ripp. Freebie: pens
Empyrean XTime uses Big Data analysis to do "much faster accurate
Monte Carlo silicon timing sign-off." Does critical path, low
power and sensitivity analysis. Used for design margin recovery.
(booth 2537) Ask for Jason Xing. Freebie: fluffy animal
FPGA STUFF
9.) Blue Pearl Visual Verification lets FPGA engineers visually verify
with graphical FSMs, CDC, and false path viewers with cross probing to
RTL, with forward and reverse tracing, and linting message filtering.
They upgraded its simultaneous clock and clock domain analysis CDC stuff.
Reads and obfuscate encrypted IP to IEEE 1735. It lets encrypted IP to
be used during clock domain crossing analysis.
New this year -- Blue Pearl added reset domain crossing RDC. Also worked
they with NanoXplore SAS to design/test radiation hardened FPGA designs.
Microsoft, Lockheed, Bechtel, Raytheon, Thales, Navy Research Lab,
Harris, Ricoh, GE Medical, MBDA, BAE, Fujitsu, NEC, Bechtel, GE.
(booth 2429) Ask for Simon Matthews. Freebie: pens
Blue Pearl HDL Creator is an editor with 2000 real-time checks to fix
issues as you code, such as compilation and missing dependencies.
(booth 2429) Ask for Simon Matthews. Freebie: pens
Menta Origami Programmer is a unique tool that lets ASIC/SoC designers
create their own TSMC 28HPC+ or GF 14LPP embedded custom FPGA IP blocks.
(booth 1313) Ask for Yoan Dupret. Freebie: ment candy
Siemens Precision Synthesis does synthesis-based automated single event
effect mitigation methods such as triple modular redundancy (TMR),
fault-detect and fault-tolerant FSM encoding in FPGAs. ISO 26262,
DO-254, and IEC 61508. SEE mitigation in safety-critical designs.
LEC flow for datapath FPGA designs. Siemens Precision loosely rivals
Synopsys Synplify Premier. Customers "have small black helicopters."
(booth 2521) Ask for Rakesh Jain. Freebee: espresso & beer
Siemens Questa Equivalent Design FPGA does equivalence checking but for
FPGAs; sort of like Cadence Conformal, Synopsys Formality but for FPGAs.
It does RAM reduction, identical cell detection, instance mapping, etc.
on bigass FPGAs from Intel (Altera), AMD (Xilinx), and Microchip. Made
for Hi-Rel, A&D, Safety Critical, and Security on larger FPGA designs.
(booth 2521) Ask for Chris Giles. Freebee: espresso & beer
Siemens Questa PS adds PSS modeling to Questa Prime FPGA simulation
UVM verification flows. Does Breker Trek or CDNS Perspect in FPGAs.
(Booth 2521) Ask for Mark Olen. Freebie: espresso & beer
PORTABLE STIMULUS
10.) Portable Stimulus (PSS) promises UVM reuse from HW all the way to SW.
UVM Simulation ==> HW/SW Emulation ==> final post-Silicon
For a good detailed tech primer on PSS, see ESNUG 578 #1, #2, #3.
Breker TrekSoC had slipped way behind CDNS Perspec in "Best of 2018"
(See DAC'18 #2b) But I still recommend seeing Breker at DAC'23
because you can easily see Perspec at all the CDNlive events.
In 2019, Breker added DSL input, and better synthesis to UVM. Now in
2023 "We extended it to handle complex SoC verification requirements,
firmware, processor cores." Breker's strength is it's output is
easy to make into testbenches. Broadcom, Nvidia, Intel, ADI, AMD, ZTE
(booth 2520) Ask for Adnan Hamid. Freebie: SF candy
Cadence Perspec is on the not-C++ but DSL side. It's a multi-core
ARM verification library/tool for cache coherency, distributed virtual
memory, low power. "We're swimming in ARM cores, John!!! Swimming!"
Perspec voted #2 overall by users as "Best of 2018". (See DAC'18 #2a)
Qualcomm, Samsung, Mediatek, Renesas, ST, TI, Infineon are users.
(booth 1511) Ask for Moshik Rubin. Freebie: lotto stamp
Siemens Questa InFact "achieves System Verilog coverage 25X faster
than old school constrained random test." Imports SV constraints and
generates SV IP level tests & system level C/C++ tests. Dropped
proprietary input to be 100% PSS 1.0. Pre-PSS, InFact users like its
coverage space pruner getting 30X sim speed-up. (ESNUG 581 #3.)
Users are Qualcomm, Applied Micro, Ciena, Microsoft, Microsemi.
(Booth 2521) Ask for Mark Olen. Freebie: espresso & beer
Synopsys still isn't showing a PSS tool at DAC'23. Rumor is they're
still looking at acquiring Breker to fill that hole.
CALIBRE, STAR-RC, & RIVALS
11.) Siemens Calibre nmDRC is the industry's DRC king with 3nm tapeouts for
sign-off and they're developing 2nm. Scales to 2,000 CPUs for designs
and 10,000 CPUs for manufacturing. Rivals are SNPS ICV, CDNS Pegasus.
Lots of ML/AI to see -- and lots cloud stuff at DAC with AWS and Azure.
TSMC, Samsung, Intel, GlobalFoundries, SMIC, UMC, and TowerJazz all
use Calibre with vast, vast, vast ... unimaginable numbers of licenses.
(booth 2521) Ask for John Ferguson. Freebee: espresso & beer
Siemens Calibre nmDRC Recon -- a blazing fast Calibre RealTime tool
to quickly identify systematic design issues during early iterations.
Typical run times >10x faster than standard Calibre nmDRC. Also, able
to gray box (waiver) out known immature blocks for even faster run times
and to supress nuisance errors accelerating designer debut. "Competes
with ICV Design Explorer slide-ware." Production deployments across
effectively all the IC Insight's top 25 companies. Find someone who
isn't already using or evaluating it! Cloud ready on AWS/Azure.
(booth 2521) Ask for Michael White. Freebee: espresso & beer
Calibre Pattern Matching replaces text-based design rules with visual
geometry capture and compare. SRAM checking for TSMC 5/3nm are based
on it. Removes design patterns that are "yield detractors." Aimed
at 17/5/3/2nm designs. Also core to Samsung's Closed Loop DFM for
faster yield ramps. TSMC, Samsung, GlobalFoundries, SMIC, UMC.
(booth 2521) Ask for Michael White. Freebee: espresso & beer
Cadence Pegasus DRC "massively parallel DRC engine" runs "100's CPUs".
Claims 8X/12X faster than old Calibre. For Innovus PnR, Pegasus does
signoff DRC, incremental DRCs, signoff metal fill, incremental metal
fill, timing-aware metal fill, and MPT decomposition for FinFETs. Over
the years Sawicki had fun torturing Anirudh about there being no TSMC
certified runsets (ESNUG 576 #1, 585 #1); but that changed April 2019
when TSMC put out certified Pegasus runsets for both 7nm and 5nm. Will
Sawicki now be losing sleep on this? Texas Instruments, Microchip,
TSMC, Samsung, Global Foundries, Intel and Microsemi are users.
(booth 1511) Ask for Bala Kasthuri. Freebie: lotto stamp
Cadence Quantus QRC competes with Star-RCXT and Calibre-xACT. Does
multi-corner/statistical/inductance RLCK extraction, 16/14/10/7/5nm
Modeling, distributed processing, netlist reduction, SNA. Double
patterning, 3D-IC. 41 FinFET customers and 3 FD-SOI. Reliability.
Constraint validation. Works "in-design" in Innovus and Virtuoso.
Quantus QRC was in Amazon AWS and Microsoft Azure clouds years ago.
(booth 1511) Ask for Hitendra Divecha. Freebie: lotto stamp
Siemens Calibre-xACT does massively parallel full chip RLC parasitic
extraction without tiling. Processes entire net on a dedicated CPU.
No boundary and halo effects. "Attofarad accuracy with multi-million
instance digital or custom designs." Hybrid MOL/BEOL solver good to
7nm. Multi-patterning. Decks from TSMC, Samsung, GF available.
Tight links to Aprisa. Can do both field solver or table based.
(booth 2521) Ask for Carey Robertson. Freebee: espresso & beer
Lorentz PeakView does 3D EM extraction and modeling. Has vertical
inductance, multi-sheet extraction, and chip-package EM co-simulation.
Competes with Ansys HFSS. Users are Qualcomm, TI, TSMC, GF, Samsung.
(booth 1516) Ask for Henry Chi. Freebie: mugs
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. 22nm - 3nm.
(booth 2453) Ask for Coby Zelnik. Freebie: pens
Siemens Calibre YieldEnhancer fills both low nodes and complex analog
blocks. Has push button ECO Fill solution. 3nm in volume production,
pilot at 2nm. Cloud AWS/Azure. Synopsys IC Validator and Cadence
Pegasus are competitors. TSMC, Samsung, IFS, GlobalFoundries, SMIC, UMC.
(booth 2521) Ask for Jeff Wilson. Freebee: espresso & beer
Siemens Calibre PERC does circuit reliability verification, and is in
cell, block, and full-chip 3rd party sign-off flows to check for
common electrical failures such as Electrostatic Discharge (ESD),
Latch-Up, and Electrical Overstress (EOS). Has extensions to
Calibre YieldEnhancer for net-aware and orientation-aware metal fill.
PERC end users are Xilinx, Broadcom, ST, ARM, Silicon labs. Foundries
that support PERC are TSMC, GlobalFoundries, Samsung, TowerJazz, UMC.
(booth 2521) Ask for Carey Robertson. Freebie: espresso & beer
Ansys Helic Exalto does 3D electro-magnetic (EM) crosstalk analysis
and signoff. Has killer capacity/speed/accuracy. 12 Ghz chip with EM
coupling through PWR/GND. 2.8mm X 700u, with AP, M12-M7. Extracted
in 36 hours on 20 cores. Exalto is the only EM sign-off tool that
can handle designs with 2,000 ports doing full RLCK extraction in
40 hrs with 16 CPUs and 150GB of RAM. With 32 CPUs, under 1 day.
Exalto works with Star-RC, Quantus, Calibre-xACT. Huawei, Qualcomm.
(booth 1539) Ask Yorgos Koutsoyiannopoulos. Freebies: pens
Ansys Helic Pharos does EM risk-analysis. Analyzes EM isolation
between selected victim nets and all potential aggressors; does up to
100 billion pairs. Pharos does 2,000 ports vs. HFSS 30 ports. Gives
EM isolation "heat maps" with GHz frequency sweeps. Nothing like it
before. With Star-RC, Quantus QRC, Calibre-xACT. See ESNUG 584 #4.
(booth 1539) Ask Yorgos Koutsoyiannopoulos. Freebies: pens
NEW! -- Siemens Calibre DesignEnhancer is analysis driven Calibre-correct
physical design chip finisher for improved EM/IR robustness, design
quality and time to tape out. Competes with ICC2/Fusion and Innovus
chip finishing tools. Claims over 20 customers in production.
Public customers are ST Microelectroncs, Samsung, Juniper, Intel.
(booth 2521) Ask for Jeff Wilson. Freebee: espresso & beer
Silvaco (Infiniscale) TechModeler takes IV curves from silicon or 3D
parasitic extraction and uses a neural network to make very accurate
behavioral Verilog-A models from a small sample size that can be
simulated in SPICE. It competes with Keysight's NeuroFET.
(booth 2511) Ask Babak Taheri. Freebie: tape measure
Silvaco Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
Now 2x faster and can compare 5 different netlists at the same time.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
Silvaco SmartDRC & SmartLVS -- rivals Calibre, Pegasus, IC Validator
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
NEW! -- Silvaco Viso is their new parasitic extraction viewer.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
Synopsys Star-RC dominates extraction; unknown if showing at DAC'23.
EMULATION / ACCELERATION / PROTOTYPING
12.) Cadence Palladium Z2 is a processor-base HW emulator that scales up to
18.4 billion gates. Claims 50% runtime improvement this year. It's
Modular Compiler compiles 10 billion gate netlist designs in 5 hours.
It has "full vision" debugging, plus record and replay. Upper limit is
2,304 simultaneous users, but it's job scheduler does dynamic job
relocation so users can prioritize workloads. Comes in booth air cooled
and water cooled options, but most installations are water cooled.
Got #5 Best of 2020 for "Dynamic Duo" Protium compiles. (DAC'20 #5b)
Like everyone else, it has AI everywhere and does AWS/Azure/GCP cloud.
Marvell, ADI, Intel, AMD, ARM, HPE, Microsemi, Nvidia, Renesas, Cavium.
(booth 1511) Ask for Michael Young. Freebie: lotto stamp
Siemens Veloce Strato+ is a processor-base HW emulator that scales up to
15 billion gates. Strato's 28nm Chrystal 3+ uP chip is more recent as
compared to Palladium's much older uP chip. Capacity scales from 60 MG
(1 - 2 users) to largest configuration Veloce Strato+ 4M for 512 users.
SW scaled for faster turn around. "We got tons of AI/ML & cloud, too!"
Big selling point is it's air cooled, not water cooled. (ESNUG 567 #3)
(booth 2521) Ask for Vijay Chobisa. Freebee: espresso & beer
Siemens Veloce Apps are tight with Ansys Apache PowerArtist. Its RTL
power reduction analysis is 4.5X faster. There 8 other Veloce Apps:
Coverage, Assertion, Deterministic ICE, ICE, Power, SW Debug, DFT,
and Ixia Virtual Network App. ST, Broadcom, Mitsubishi are users.
(booth 2521) Ask for Vijay Chobisa. Freebee: espresso & beer
Cadence Protium-X2 is an FPGA based prototyper that can scales up to
9.6 billion equivalent FPGA gates, runs 3-5X faster than Palladium,
and can deliver working hardware as quickly as 2-3 weeks. It has
debug aimed at software workloads including, SVA with lightweight
mode, Save and Restore, and FullVision for 100% signal visibility
without pre-specifying probes. "Dynamic Duo" compiles with Palladium
is a very big selling point for Protium. (See Best of DAC 19 #1a)
Nvidia, Mellanox, Microsemi, Marvell, Medtronic, AMD/Xilinx are users.
(booth 1511) Ask for Michael Young. Freebie: lotto stamp
Siemens Primo is like Cadence Protium, but for Siemens Veloce Strato+
(booth 2521) Ask for Juergen Jaeger. Freebee: espresso & beer
Siemens Veloce proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Stratix 10. 600 M ASIC gates.
20 Gbps. In 5 years ProDesign shipped 1251 units to 121 customers.
(booth 2521) Ask for Juergen Jaeger. Freebie: espresso & beer
Synopsys EVE ZeBu-6 isn't here yet, but it's going to be based on the
brand new 7nm Xilinx Versal Adaptive SoC VP1902 FPGA with 900K LUTs;
just like the future Cadence Protium-X3 and the future Siemens Primo+.
I would personally go to each vendor and ask: "since you're each using
the exact same FPGA for you next gen prototyper, shouldn't I just buy
that prototyper with the cheapest sales price?" Why buy from you?
Aldec HES-DVM is the poor man's HAPS. Uses UltraScale U440's. Claims
633 M gates. Auto partitioning, ASIC-to-FPGA clock conversion,
static/dynamic probes, memory viewer, HW breakpoints. Ethernet, USB,
USB-OTG, HDMI, I2C, SPI, RS232, GPIO, ARM Debug & JTAG. Users are
Qualcomm, Samsung, Fuji-Xerox. Now HES-DVM Cloud does does System
Verilog DPI-C TLM's, virtual SW, and ICE in the Amazon AWS cloud.
(booth 1425) Ask for Stanley Hyduke. Freebie: pens
Synopsys HAPS-100 prototypes here but I don't know if it's at DAC'23.
MARGINs & ECOs
13.) Easy-Logic ECO Surgery does a new rewiring based functional ECO's
Does both pre-mask ECO and post-mask ECO. Logic patch generation, scan
chain fixing, low power cell insertion, and metal ECO "new ECO patches
sized just 1/100 to 1/1000 of manual". They won the ICCAD CAD contest
3 years in a row (2012, 2013, 2014). Runs in CDNS/SNPS/MENT flows
(booth 2445) Ask for Kager Tasi. Freebie: candies
Synopsys Tweaker is a family of physically-aware ECO tools:
Synopsys Tweaker-T1 vs. PrimeTime-ECO vs. Cadence Tempus-ECO
Synopsys Tweaker-F1 vs. Cadence Conformal ECO
Static/dynamic power ECO's. 50 M inst. 16/14/10/7nm FinFET. Now
hierachical/timing/CPU/IR-drop ECO flows. Intel/GF/Samsung/TSMC
Broadcom, Qualcomm, LG, TSMC, Mediatek, Samsung, Xilinx users.
(booth 2456) Ask for Shankar Krishnamoorthy. Freebee: pens
Empyrean XTop physical MCMM timing ECO tool. PBA timing fixes,
route-based timing fix. 16/14/10/7nm 100M inst. 5X faster.
ClockExplorer does CTS clock analysis and constraint generation.
It helps cuts clock insertion delay. Marvell, HiSilicon users.
(booth 2537) Ask for Jason Xing. Freebie: fluffy animal
Cadence Conformal ECO Designer generates "congestion-aware ECO"
for "last-minute difficult ECO areas" for pre- and post-mask layout.
Has a fast setup, 10X TAT and neat scan chain preservation stuff.
Users Broadcom, Qualcomm, ST, Samsung, Toshiba, AMD, Mediatek
(booth 1511) Ask for Jayanth Prakash. Freebie: lotto stamp
VIRTUOSO & RIVALS
14.) NEW! -- Siemens Solido Design Environment -- holy crap! Solido Amit is
taking on the Virtuoso ADE monopoly by launching Solido DE -- a cloud-ready,
comprehensive AI-powered environment for analog, memory, and std cell
flows, with integrated variation-aware design (and verification as well)
with an integrated modern wave viewer, Solido Waveform Analyzer.
It's a SPICE simulation environment like Virtuoso ADE that runs Siemens
AFS, CDNS Spectre, and SNPS HSPICE/FineSim SPICEs. (It's only a DE to
fire of SPICE runs. Siemens schematic capture and layout by Tanner
S-Edit and L-Edit. Virtuoso does it with Composer and Layout Editor.)
Also Solido DE "extends AI deeper into custom IC design/verification using
Additive AI and Assistive AI technologies causing disruptive impact."
Claims 1000X+ speedup with better accuracy. TAT is cut by weeks!
It competes with Cadence Virtuoso ADE and Virtuoso Variation, Synopsys
PrimeWave, Silvaco VarMan, and MunEDA. As part of the Solido distro,
Solido DE is used by 90+ semi houses like Samsung, SK Hynix, Infineon.
(booth 2521) Ask for Wei-Lii Tan. Freebee: espresso & beer
NEW(ISH) -- Cadence Virtuoso Studio is massive amounts of AI pumped
into the Virtuoso full custom/analog monopoly. Studio ADE kicks
off 1,000s of parallel SPICE runs and layout throughput is 100,000s
of single 5/4/3/2nm transistors and the new GAAFets. Built-in Pegasus
DRC/LVS for interactive signoff DRC that cuts TAT 20% by "quickly
detecting and fixing issues before they become a problem." Deep
hooks into Cadence AWR Microwave Office IP for RF/microwave/mmWave
and heterogeneous system designs. Deep hooks in Cadence Spectre,
Spectre-X, Spectre FX, and Spectre FMC Analysis for "10,000X speedup
in design space exploration for 3- to 6+-sigma variation analysis
with Monte Carlo simulations. Users ADI, Renesas, MediaTek, and TSMC.
Get this -- Virtuoso Studio now claims to do analog design migration
from node to node. Like 7nm going to 5nm. Or 5nm to 3nm. (WTF!?!)
(booth 1511) Ask for Steven Lewis. Freebie: lotto stamp
Synopsys Custom Compiler is Aart's 2nd attempt on Anirudh's Virtuoso
monopoly. The 1st try was Custom Designer (which flopped.) CC runs
the old Laker3 router plus the Ciranova Helix plus some "assistant
features" to generate many different layouts of one circuit. Few users.
(booth 2456) Ask for Shankar Krishnamoorthy. Freebee: pens
Siemens Calibre RealTime Digital does instant sign-off DRC checking
and fixing inside Innovus and ICC2/Fusion Compiler and Aprisa. Same
deck, same engine and same results as batch Calibre. Like CDNS Pegasus
Interactive and SNPS ICV, but it's 40% to 85% faster. ESNUG 584 #1.
(booth 2521) Ask for Joe Davis. Freebie: espresso & beer
Siemens Calibre RealTime Custom does instantaneous sign-off DRC checks
and fixes inside Virtuoso, Laker3, Custom Compiler. Same deck, same
results as batch Calibre. 2-5X productivity improvement when fixing
DRCs in 180-3nm nodes. Double/triple patterning, preferred metal
direction, density checks, pattern matching and voltage-aware DRC.
Has cells/blocks-to-macros DRCs to automatically launching batch
Calibre jobs. Rivals Cadence iPVS. Qualcomm, Broadcom, SiLabs.
(booth 2521) Ask for Joe Davis. Freebie: espresso & beer
Siemens Tanner is OA-based S-Edit schematic capture, L-Edit custom
layout, and T-Spice SPICE. Founded 1988. "Cost effective" prices.
The old HiPer Verify DRC was replaced by Calibre DRC. Pyxis in it,
too. Does 16/12nm now! MEMS designers like Obsidian, Microgen, Innotime,
Lewyn Consulting, Velankani, Eesy IC, Microdul AG, PragmatIC are users
(booth 2521) Ask for Jeff Daspit. Freebee: espresso & beer
Cadence Pulsic Animate & Unity does an AI-enhanced layout of analog
(transistor level) designs, with no constraints, no scripting, no
programming required. Multi-threaded. Makes 100's of fully PnR-ed
layouts in minutes from OA schematic (vs. 2-3 weeks single layout in
olde Virtuoso). Did a 40% reduction in cell block PnR time for Ricoh.
(booth 1511) Ask for Steven Lewis. Freebie: lotto stamp
Silvaco Expert is a hierarchical IC layout editor. Schmatic driven.
10 Gig GDSII loads in "minutes". Uses Calibre Interactive for DRC
"on the fly". Rapid pan/zoom. Equal resistance router. OA and
interop PDKs (iPDK) makes design migration easier. And WTF???!!
Silicon Creations uses it for 7/5nm FinFET? Silvaco doing 7/5nm?!?
Also Silvaco Clever 3D RC field solver BEOL/MEOL parasitic extract.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
Silvaco Cello FinFET fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 16/14/10/7nm.
Also does coloring, self aligned MOL, template based cell creation.
(booth 2511) Ask for Babak Taheri. Freebie: tape measure
LibTech LibChar does std cell, IO, SRAM characterization & modeling.
Now does PLLs. (booth 1510) Ask for Mehmet Cirit.
Movellus PLL/DLL/LDO Generator is kind of weird because it creates
*digital* versions of *analog* IP. In this case, it's PLL's, DLL's,
and LDO's. Why? Because then you can use *digital* synthesis, STA,
PnR on your PLL/DLL/LDO -- making them portable across nodes, and
you can do scan/ATPG/DFT on your PLL/DLL/LDO, too! (See ESNUG 582 #2)
So far at TSMC 16nm and Mo is working on 7nm. Intel Capital funded.
(booth 2417) Ask for Mo Faisal. Freebie: chocolates
Keysight Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Works with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Intel, Broadcom, Qualcomm, Infineon, Bosch, Marvell, Toshiba, TSMC.
(booth 1531) Ask for Niels Fache. Freebie: pens
MunEDA WiCked SPT converts analog/mixed-signal/RF circuits across
different foundries/processes. Transistor resizing, optimization,
and verification for best performance, area, low-power/low-voltage,
robustness against process variation and mismatch. Qualified for
FinFET, Bulk, Bipolar, BiCMOS, and FDSOI. GUI for migration and
yield optimizer, faster PVT corner runs and MC sampling. Their
WiCked Circuit Suite does transitor resizing for PPA, too. Users
Samsung, ST, GF, SMIC, Novatek, Infineon, Fraunhofer, Chipus, Perceptia.
(booth 1407) Ask for Andreas Ripp. Freebie: pens
Empyrean Skipper does super fast layout review, analysis, debug,
layout IP protection. 1TB GDSII. Marvel, Hisilicon, Sandisk.
(booth 2537) Ask for Jason Xing. Freebie: fluffy toy
Keysight ADS and GoldenGate SPICE is for silicon RF IC design and
simulation. iPDK PyCell & TSMC iRCX support, intuitive layout, does
electro-thermal on windows, harmonic balance & circuit envelope
converges faster. Qorvo, Skyworks, Broadcom/Avago, Qualcomm users.
(booth 1531) Ask for Niels Fache. Freebie: pens
Keysight SOS ADS does design data management for RF engineers using
Keysight Agilent ADS. Northrop, IDT, Quorvo, Rohde & Schwarz, Inphi
(booth 1531) Ask for Niels Fache. Freebie: pens
Intento ID-Xplore resizing/biasing/migration of analog/AMS circuits.
(booth 1411) Ask for Ramy Iskander. Freebie: stickers
DESIGN COMPILER & RIVALS
15.) Cadence Genus is an attack on Aart's 30 year Design Compiler
franchise. It's Anirudh's home-grown, massively parallel RTL and
physical synthesis tool that's "5X faster" than Design Compiler,
"1/2 iterations between unit and block/chip-level synthesis".
Genus got #4 "Best of 2017" with users in DAC'17 #4 and won a
user benchmark vs. DC-Graphical in ESNUG 582 #1. Broadcom, Texas
Instruments, Cienna, MaxLinear, Broadcom, Cisco, ImgTec are users.
This year it has intelligent awareness of congestion in synthesis,
and some neat block-centic and datapath-centric optimizations.
Big selling point is tight with Innovus PnR, Tempus STA, and Joules.
"Hey, everyone! Genus is on AWS/Azure/GCP clouds now, too!"
(booth 1511) Ask for Rob Knoth. Freebie: lotto stamp
Siemens Oasys-RTL does crazy fast RTL synthesis floorplanning, design
space exploration from "place first methodology". 3-hour runtimes
synth to floorplan a 2M inst chip 4G of machine memory. Synth-ed
and floorplanned 14nm 3M inst in 8 hours. 3.8M 28nm in 12 hours.
Designers can look at different views (logical, physical, timing).
New built-in memory exploration cockpit to find the best mem config
in your chip. Has integrated SQL dd to root-cause faulty RTL revs.
TI, Broadcom, Juniper, Qualcomm use Oasys. Xilinx Vivado is Oasys.
(booth 2521) Ask for Badru Agarwala. Freebee: espresso & beer
Synopsys Design Compiler is now 2.5x faster than old Design
Compiler Topo. "We beat Genus in benchmarks!" Claims improved
backend (ICC2 and Fusion Compiler) correlation at 5/3nm.
(booth 2456) Ask for Shankar Krishnamoorthy. Freebee: pens
RISC-V vs. ARM
16.) Codasip Studio creates application specific processors starting from
their production RISC-V IP. It generates RTL, UVM, and the software
design kit (compiler, debugger, profiler, ISS, etc.) from a single
high-level language. It competes against Synopsys ASIP Designer, ARM,
SiFive, and Andes. Codasip Studio 9.4.2 has better RTL performance
and area this year. The demo shows 91% reduction in runtime and energy
consumption with a 39% area increase. Also shows design exploration
to find interesting points for specific needs. (FYI -- Axel Strotbek,
the former CFO of Audi has now joined the Codasip BoD.) Users are Mythic,
Trinamic, Silicon Arts, Analogix, Xinsheng/Dahua, Dongwoon Anatech.
(Booth 2354) Ask for Troy Jones. Freebie: pens
NEW! -- Breker RISC-V Core and SoC Test Generator SystemVIP automatically
generates RISC-V tests for platform issues - e.g. Coherency, Security,
Load Store, Interrupt, etc. Competes against Google RISCV-DV Instruction
Generator. IBM, Broadcom, AMD, Sanechips (ZTE), ADI use Breker instead.
(Booth 2520) Ask for Adnan Hamid. Freebie: SF candy
Imperas ImperasDV does timing driven RISC-V custom instruction design and
optimization. Added configurable SystemVerilog functional coverage model
called riscvISACOV. "Save months of engineering effort with our lock-step
asynchronous continuous compare flow." NSI-TEXE, Marvell, Dolphin Design,
Ventana, Lightelligence, Nvidia Networking (Mellanox), OpenHW Group,
Silicon Labs, NXP, Intrinsix, lowRISC, Seagate are all Imperas users.
(booth 2336) Ask for Larry Lapides. Freebie: pens
NEW! -- Mirabilis VisualSim RISC-V Architect does micro-architecture
system modeling that models your RISC-V pipeline at 98% functional and
timing accuracy without the use of RTL or emulation. It can execute
benchmark code and provide detailed statistics of the instruction,
pipeline, execution, TLB, Cache, memory, and peripherals. VisualSim
gets cycles per instruction of 0.59 in the simulation vs 0.56 in the
actual Silicon. This block can execute the Dhrystone, Radar, or
network protocol code in cycle-accurate detail. The user can easily
modify the openly available code to import their design customization.
RISC-V core statistics, debugging, traces, power, and timing reports.
Qualcomm, AMD, Western Digital, Denso, Northrop Grumman, Lockheed, NASA
(booth 2217) Ask for Deepak Shankar. Freebie: Indian candy
RTL & GATE POWER
17.) Siemens PowerPro does RTL power optimization. Users see 9% to 12%
general Verilog RTL power savings. 37% cut in sequential logic power
saving in ESNUG 535 #2. Chatting up their "What If" ability with
to quickly understand power effects of potential mode, operating
environment or design changes "saving hours of turn-around-time".
PowerPro is only tool tight with Questa SLEC, which sequentially verifies
if your low power RTL tweaks equals your original RTL. Siemens PowerPro
competes against Ansys PowerArtist, Synopsys SpyGlass Low Power,
and Cadence Joules. Gets ~85% correlation to gate-level. 7/5nm FinFET.
Qualcomm, TI, Samsung, ARM, Raytheon, Google, NXP are users.
(booth 2521) Ask for Qazi Ahmed. Freebie: espresso & beer
Apache PowerArtist users saw 3% to 10% reductions. Does automatic
and guided. Sequential and combinational clock-gating constructs,
memory light/deep sleep modes, and wasted power in datapath logic.
RTL power accuracy within 15% of sign-off. 10 M gates in 1 hour.
10/7/5/3nm. Handles 100M+ instances. Hooks with RedHawk for
power grid integrity. Also peak power & thermal hotspot analysis.
Tight hooks into Siemens Veloce emulation and its Power App. Activity
streaming 10X faster vs. old slow FSDB for millisecs of activity.
Users are Broadcom, Nvidia, Samsung, ST, NXP, Toshiba, ARM, Ciena.
(booth 1539) Ask for John Lee. Freebie: stuffed animal
Synopsys Atrenta Spyglass Power users got 9% to 16% power cut on
Verilog RTL. RTL, gate-level, or post-layout. FSDB, VCD, SAIF
and vectorless. Does ECO's, CPF, UPF, mem in sleep mode. ERC
checks on P/G netlist. Power modeling and coarse clock gating.
(booth 2456) Ask for Ravi Subramanian. Freebee: pens
Cadence Joules is an RTL power cutter. Estimates power at RTL
to within 15% of signoff power. It has "power scrubbers". Joules works
with Genus and Palladium. Guided RTL power reduction cuts power by
up to 25%. RTL stimulus for activity-driven power reduction. Joules
xReplay works with Xcelium to power reclaim and glitch power analysis
using RTL vectors. AWS/Azure/GCP. Users are Qualcomm, Maxlinear,
ARM, Broadcom, TI, Socionext, Renesas, Microsemi, Analog Devices
(booth 1511) Ask Rob Knoth. Freebie: lotto stamp
Baum PowerBaum does static & dynamic RTL power analysis that's up to
"100X to 200X faster" vs. PowerPro/PowerArtist/Spyglass. "We couldn't
find a fast/accurate tool to do this, so we built one of our own!"
(booth 1550) Ask for Andy Ladd. Freebie: none
CDNS JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks to
see any issues the after the insertion of power management circuitry.
(booth 1511) Ask Pete Hardee. Freebie: lotto stamp
Mirabilis VisualSim Power v2.0 measures system level power on
your SoC or uP model. Does power gating and sleep modes. Users
are China Auto, IBM, Analog Devices, AMD, and Sandia Labs
(booth 2217) Ask for Deepak Shankar. Freebie: Indian candy
RTL ENVIRONMENTS/SIMULATORS/TOOLS
18.) Synopsys Verdi is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 2456) Ask for Ravi Subramanian. Freebee: pens
Cadence PinDown auto debugs regression failures by IDing the
commits that cause the test failures and automatically assigns bug
reports to the engineers who made these commits. PinDown debugs
down to the exact line of code. It instantly detects high-risk
code changes without any simulation. Samsung, Broadcom, Synopsys.
(booth 1511) Ask for Daniel Hansson. Freebie: lotto stamp
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 1541) Ask for Chouki Aktouf. Freebie: candy
Siemens QuestaSim bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, formal in one big smudgy bundle.
ISO 26262 certification, real number modeling, P1735 encryption.
(booth 2521) Ask for Mark Olen. Freebee: espresso & beer
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
The Plot Viewer does simple/polar/vector graph and image/color map.
Python support using Cocotb GPI. This enables terse, readable,
maintainable code while providing easy Python abstraction to RTL.
(booth 1425) Ask for Stanley Hyduke. Freebie: pens
Amiq Eclipse DVT IDE is an add-on to VCS/Questa/Incisive that lets
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta like Visual C stuff.
Samsung, Intel, Broadcom, Qualcomm, Toshiba, SK Hynix, Micron users.
(booth 1326) Ask for Cristian Amitroaie. Freebie: chocolates
Sigasi Studio is much like Amiq DVT. System Verilog & VHDL support.
In 2019, added Visual respresentation and GUIs for documentation.
NXP, UTC, ASML, Thales Group, Thales Alenia Space, Airbus, Philips,
Rohde & Schwarz, Bosch, Siemens, Facebook, MacLaren, Easics, Harris,
Prodrive, Johnson & Johnson, SCD, ABB, Saab, BAE, EPSON, GE, Dolby
Laboratories, CERN, Fraunhofer Institute, Heidenhain uses it.
(booth 2416) Ask for Bart Brosens. Freebie: Belgian chocolates
NEW! -- Sigasi Studio Veresta is a fast linter for CI/CD (analyzes Google
OpenTitan in 27 seconds on an Intel 12700K). Brings Sigasi Studio to the
command line, syntax checking, lints semantic checks, and style checking.
Works with SonarQube, Jenkins, Gitlab CI/CD, Github actions, etc. Give
overview on code quality. Cuts CI/CD costs by gatekeepering broken code.
(booth 2416) Ask for Bart Brosens. Freebie: Belgian chocolates
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for registers/sequences into UVM/RTL. Amazon, Google,
Marvell, OnSemi, Rambus, Conexant, Wipro, Conexant, John Deere, CERN
(booth 2512) Ask for Freddy Nunez. Freebie: travel mug
SystemC/C/C++/TLM STUFF
19.) Siemens Catapult HLS synthesizes C++/SystemC/MatchLib into
Verilog/VHDL to target either FPGA or ASIC. Does top-down and bottom up,
cuts project times 50% and verification costs by 80%. C->RTL visualizer.
Has libs and I/O for Xilinx and Altera to crank clock freq, has hooks
into Siemens Oasys-RTL. Partnership with Synopsys for better correlation
and QoR. Toolkits for AI/Machine Learning (YOLO Tiny) and complicated
math. AC_data_types open source on GitHub and still way faster than
SystemC types with no ambiguities. It's the King of HLS/HLV. Rivals
Cadence Stratus, Xilinx Vivado HLS. Nvidia, Google, ST, Meta, Alibaba.
(booth 2521) Ask for Stuart Clubb. Freebee: espresso & beer
Siemens Catapult Coverage does formal/lint checks on synthesizable
SystemC and C++ to prevent ambiguous or bad logic mistakes. Coverage
covers C statement, branch, toggle, expression, and array indexing; all
done hundreds of times faster than RTL simulation coverage. Qualcomm,
Nvidia, ST, Google, FotoNation, SeeCubic, Bosch, Fujitsu, Toshiba.
(booth 2521) Ask for Stuart Clubb. Freebee: espresso & beer
Siemens SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Rivals Synopsys Hector and Jasper EC.
Runs "bottom up" partitions. LSF support. Nvidia, Google, ARM users
(booth 2521) Ask for Stuart Clubb. Freebie: expresso & beer
Siemens Catapult Formal are formal verification apps for coverage,
equivalency, and RTL assurance in the Catapult HLS flow. Unique to
the Catapult ecosystem. (booth 2521) Ask for Stuart Clubb.
Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
RTL that Design Compiler or CDNS Genus can easily digest. Can do both
control logic and datapaths. Claims better accuracy than Catapult.
Hooks into CDNS Genus RTL synth, Joules low power, and Innovus PnR.
Supposedly can see PnR congestion issues in your SystemC/C/C++ source
HiSilicon, NXP, Bosch, Samsung, LG, Realtek, Toshiba, Fujitsu, Ricoh
At one time Brett owned the C synth space, but Badru stole his crown.
(booth 1511) Ask for Dave Pursley. Freebie: lotto stamp
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. It competes against Cadence
Virtual, Synopsys Virtualizer, Mentor Vista, and Wind River Simics.
NoCs. Fault injection. Linux, FreeRTOS, OpenRTOS, uC/OS, MQX, eCoS.
Now Imperas OVP has 40 EPKs, 170 CPU models of ARM, MIPS, RISC-V.
Users are ImgTec, Renesas, Recore, Altera, Audi, AMD, Nagravision.
(booth 2336) Ask for Larry Lapides. Freebie: USB charger
Synopsys Synphony HLS plays here but probably not showing at this DAC.
VERIFICATION IP
20.) Siemens Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet (400G, 100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I3C, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); FLASH Family (SDCard4.2,
SDIO4.1, eMMc5.1, ONFI4.0, Toggle, UFS, Parallel NOR, Serial NOR);
Display (CDC, DisplayPort, eDP, V-by-One, HDMI 2.1, HDMI 2.0,
HDMI 1.4, HDCP 1.4); HyperBus (Hyperram, Hyperflash); Auto (CAN,
CAN-FD, LIN); Mil-Aero (Spacewire, 1553b, PCI); 5G (JESD204B,
CPRI); Storage Family (SATA); NVMe over Fabric, Interlaken, I3C.
Now added PCIe 5, USB 3.2, DDR 5, LPDDR 5, UXSGMII, Ethernet Base T
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, Marvell, ST users.
"Oh, don't forget we have 1700 combinations of memory models, too!"
(booth 2521) Ask for Gordon Allen. Freebee: espresso & beer
Siemens Avery IP (VIP) does PCIe 5.0, DDR5, HBM2E, CXL, CCIX,
Gen-Z, Ethernet 400G, CSI/DSI, I3C; ARM and RISC-V. "Use all 59 VIPs
with one license." UCIe this year! Samsung, Broadcom, Xilinx, Marvell.
(booth 2521) Ask for Gordon Allen. Freebee: espresso & beer
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2, Ethernet 25G/50G, HBM, HMC,
MIPI DSI-2, WiFi MAC, CCIX, BLE5, DDR5" -- plus new "PCIe 5, HBM2,
LPDDR5, MVMe 1.3, CHI-B, UFS 3, USB 3.2, USB Type-C, DSI 2.0, I3C."
Now added USB-4, DisplayPort 2.0, CCIX, LPDDR5, DDR5, PCIe Gen5
Denali-style API, all simulated VIP runs on VCS, Questa and Incisive.
"VCS or Questa customers do not need Specman e". TripleCheck.
Broadcom, HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung.
"CDNS VIP runs 2x faster vs. SNPS VIP due to optimized VIP C cores!"
(booth 1511) Ask for Boyd Phelps. Freebie: lotto stamp
SmartDV SmartCompiler lets users customize any of the 700+ SmartDV
standards-based design IP and VIP products in the SmartDV catalog.
It uses a proprietary high-level language input to automate creating
and/or customizing of IP -- and spits it out in the user's desired
methodology. The resulting "IP Your Way" is higher quality and more
cost-effective than manual customization, with 10x less engineering
effort. "We've been using SmartCompiler for 16 years to generate
literally all of our own IP. We've customized 100's of IP cores."
(booth 2435) Ask for Mohith Haridoss. Freebie: Starbucks gift card
HARD & SOFT IP
21.) Talk about a corporate eff up! ARM decided to not show at DAC, thus
yeilding the mindshare over to their smaller IP rivals! D'oh!
Silvaco Samsung Foundry IP -- holy crap! How did Iliya's little tiny
company manage to get the rights to sell Samsung Foundry design IP for
their 14nm, 11nm, 10nm, 8nm FinFet and 28nm FD-SOI process nodes???
PCIe, DDR/LPDDR, MIPI PHY, Ethernet, HDMI, USB3.1, DisplayPort,
V-by-One; along with data converters, PLLs and other analog IP.
(booth 2511) Ask Babak Taheri. Freebie: tape measure
Synopsys is showing its Virage DW ARC 600 & 700 cores, plus its
mem IP, plus std cell libs; that all directly compete against ARM.
DW ARC HS4x and HS4xD processors. 6000 DMIPS per core. Security.
ARC now has 226 customers. DW ARC comes in low power and audio.
"Hey! You engineers! STOP looking at those damn RISC-V cores!"
(booth 2456) Ask for Ravi Subramanian. Freebee: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
Last year says it has new fully verified/certified PCIe 5.0 rev 0.7.
(booth 1511) Ask for Boyd Phelps. Freebie: lotto stamp
Silvaco Xena scans a chip-level database to list all detected IP and
versions of that IP. Works for embedded SW, too. It scores the
extent to which IP exists in the chip, from its entirety to fragments.
(booth 2511) Ask Babak Taheri. Freebie: tape measure
Silvaco NanGate IoT Std Cell Libs are "IoT optimized" full custom
libraries. 9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm si proven.
Cut area 8-14%. "Our 8T 28nm GF lib got 55% higher raw gate density."
(booth 2511) Ask Babak Taheri. Freebie: tape measure
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precisionv clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 2454) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 encoders, JPEG IP. New Geon "secure" uP, J2716, MIL-STD 1553.
(booth 1506) Ask Nikos Zervas. Freebie: stylus pen
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". Now multiple proven 7nm PLLs this year.
"We have 5nm PLLs, too!" TSMC, SMIC, UMC, GF, Samsung, ARM, Toshiba
(booth 2225) Ask for Andrew Cole. Freebie: USB car chargers
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 7FF+. (booth 1335) As for John Maneatis.
TEST/SCAN/BIST/JTAG/FAULTS/DFT
22.) Here's why Sawicki's test brainiacs are crushing Aart & Anarudh in test.
NEW! -- Siemens Streaming Scan Network (SSN) drives packetized scan data
(100% payload, no address data) to your chiplet/multi-die design. Cuts
test time 80%. Scalable. "Your core DFT planning is decoupled from your
chip, thus boosting your TAT". Can do plug-and-play last-minute design
changes without affecting DFT architecture. Cuts your power profile by
reducing IR-drop -- meaning passing more margins on your first silicon.
Tests identical cores with on-chip compare. Well-designed clock timing
for fast silicon bring-up. Supports hierarchical and tiled designs.
Supports burn-in and scan chain failure analysis through laser voltage
probing/imaging (LVP/LVI). Intel, Amazon, Broadcom, Qualcomm, Samsung.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
NEW! -- Siemens Tessent Multi-Die is DFT for chiplet/multi-die designs in
2.5D or 3D. It supports 2.5D flows with boundary scan-based interconnect
die-to-die test. It "enhances 3D flows with IEEE 1838 compliant PTAP/STAP
and it uses silicon-proven Tessent SSN as a flexible parallel port. It
extends proven hierarchical DFT methodologies to 3D-IC designs." Competes
against in-house tech. Tessent Multi-Die lets you port 2.5D chiplets over
to a 3D-IC implementation. Because "using SSN bus is the easiest way to
get in and out of chiplets that are in a stack." TSMC, Broadcom users.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
Siemens Tessent Diagnosis localizes silicon manufacturing defects by
analyzing failing test cycles from the ATE using design data and with
Tessent TestKompress ATPG patterns. Diagnosis data is routinely used to
guide failure analysis and volume diagnosis to improve yield. Competes
with Synopsys TestMax Diagnosis. New this year, LVI/LVP guided by chain
diagnosis making it even easier for designs containing SSN. Encrypted
design collateral can be shared by the fabless to enable foundries to
run diagnosis. (This encrypted flow changes all the names in a design
including pin names, instances and blocks to a garbled string that lets
the foundry to run diagnosis, while simultaneously protecting the IP of
the fabless so bare design names are no longer visible.) It also has a
SSN on-chip-compare so multiple identical cores to be tested all together
saving a tone of test time. Qualcomm, TSMC, Microsoft, Samsung, Cypress
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
NEW! -- Real Intent Meridian DFT is multi-test-mode static analysis to do
"shift-left" using specialized, fine-grained rules for early detection of
DFT issues. Rivals SpyGlass DFT/TestMax Advisor, Siemens Tessent ScanPro.
It checks multiple sets of rules in a single run, reducing setup time,
speeding up runtime, and accelerating debug. Does several million gates
in minutes with low peak memory footprint. Low noise, and ha fine rule
granularity to cut noise speed up debug and root cause analysis.
Fast setup, "takes only hours vs weeks for other DFT static tools."
FYI -- This is Real Intent's 25 year in business! Congrats Prakash!!!
(booth 1525) Ask for Kanad Chakraborty. Freebie: LED pens
NEW! -- Real Intent SafeConnect does connectivity and glitch detection on
early RTL and netlist level designs. Competes against SNPS Connectivity
Check and CDNS Connectivity Verification. Native command execution for
10X better runtime. Configuration commands for flexible, compact
specification. Options to control reporting and noise reduction. UPF
for design power intent analysis. Shows signal connectivity. Has a
library of pre-defined checks. Tight debug with annotated schematics
(booth 1525) Ask for Sanjay Thatte. Freebie: LED pens
Siemens TestKompress does hierarchical ATPG. Patterns are generated
independently for each core. Can be retargeted at chip top-level.
10x faster generate time and 1/10th CPU time of Synopsys TetraMAX.
Pattern count is 1/2, so less test time. Also this core-level ATPG
means no wait for whole design to be done before ATPG generation.
TestKompress does end-to-end hierarchical, which takes DFT out
of the critical path, reduces ATPG and diagnosis runtime by 10X,
and pattern count by another 2X. Users are Broadcom, NXP, Renesas,
OnSemi, Intel, NXP, Mediatek, Spreadtrum, and Annapurna Labs.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer
Cadence Modus Test does scan insertion, compression, ATPG, logic
and memory BIST. Physically aware 2D elastic compression cuts test
logic wirelength by 2.6X. Compression ratios 400X. Takes 1/3rd
tester time. Works with Genus RTL synthesis and because of hooks
into Innovus/Genus it has lower routing congestion, fast yield ramp.
Texas Instruments, GlobalFoundries, Microsemi, Sequans users.
(booth 1511) Ask for Rob Knoth. Freebie: lotto stamp
Siemens Tessent MissionMode does hardware functional safety stuff by
system-level low latency access to on-chip test resources for on-
line test and diagnosis. Non-destrictive memory tests, too. Works
with Tessent LogicBIST and MemoryBIST or other IJTAG test IP.
Siemens Tessent ScanPro places test points in netlist for compression.
Adding 1%-2% area for a 3X to 4X reduction in ATPG test patterns.
If 100X compression with Synopsys TestKompress, Mentor ScanPro gets
300X to 400X. VersaPoints for hybrid ATPG/BIST coverage. OCC
insertion, X-bounding for logic BIST. Improves logic BIST coverage
by 2%-4% and gets to 90% coverage 8x faster. ISO 26262 likes this.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer.
Synopsys SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
(booth 2456) Ask Ravi Subramanian. Freebie: pens
Siemens Tessent IJTAG lets IEEE 1687 compliant blocks be hierarchically
scan accessable. Automatic ICL design and PDL retargeting at any design
level. New this year -- you can run IJTAG faster using TCK clock
stretching as well as ICL visualization and faster debug capabilities.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
Siemens Tessent RISC-V Trace Encoder does post-silicon debug and software
dev on RISC-V designs by monitoring program execution in real time. It
encodes program execution (instruction trace) and the data from "load and
store" instructions (data trace), outputting trace in compressed format.
It's a cycle-accurate trace so the user can optimize software performance.
Competes with SiFive Insight. Seagate uses our Tessent RISC-V traces.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer.
Siemens Tessent Embedded Analytics is a bucket of IP, embedded, and host-
run software and software development kits to "slash SoC validation cost,
provide system-wide real-time debug, and post-deployment analytics based
on functional monitoring." Competes with Synopsys SiliconMAX. Showing
a new powerful software stack letting users develop/debug/monitoring
applications running either embedded on the SoC, or on a separate host.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer.
NEW! -- Siemens Tessent LogicBIST-OST software improves BIST coverage and
reduces time-to-coverage for ISO 26262 by inserting patented Observation
Scan Technology (OST) test points. These points are observed every shift
cycle meaning less patterns are needed. Renesas, Intel, Microchip.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
ROLL-YOUR-OWN EDA SOFTWARE STUFF
23.) Verific sells System Verilog, VHDL, UPF parsers with C++ interfaces
to EDA developers. Perl and python APIs. Synopsys, Cadence,
Mentor, Ansys, Xilinx, Altera, AMD, Nvidia, Infineon, Samsung,
AMD users. Has Invio, a collection of high-level Python APIs that
make it easier to interface with their core Verific parsers.
(booth 1413) Ask for Michiel Ligthart. Freebie: stuffed giraffe
Mirabilis Collaborator generates docs and javascript for executing
models within a web browser. Used as specification or a customer
demonstration tool. Does parameter/algorithmic/topology changes.
(booth 2217) Ask for Deepak Shankar. Freebie: Indian candy
NEW! -- Mirabilis VisualSim MBSE SoC Designer lets you import your SysML
to use Model Based Systems Engineering (MBSE) as the front-end for your
design process. VisualSim maps the behavior to a hardware platform, runs
simulation to estimate runtime and power of the proposed system. There
is no emulator, RTL or software code required for this process. It is
done using a virtual simulation model. Cuts development costs by 40%.
Northrop Grumman, Sandia National Labs, Shenzhen ICC, and Denso.
(booth 2217) Ask for Deepak Shankar. Freebie: Indian candy
WORKSPACE, DESIGN DATA MANAGMENT, & IP TOOLS
24.) IC Manage Holodeck bursts your on-prem chips and EDA tool flow into the
AWS/Azure/GCP cloud. It does intelligent data cheery-picking and only
uploads what the EDA needs on demand. With Holodeck, Xilinx got a 99%
faster 1st EDA tool launch, 99% smaller cloud footprint, used 41% less
CPU time in the cloud. Demoing VCS, RedHawk-SC, Virtuoso, Calibre
Dean on IC Manage Holodeck hybrid/native cloud speedup & less storage
IC Manage GDP design & IP data management system lets digital/custom
designers find, modify, release & track design data through tapeout.
Bug interdependency management. Multi-tier web stuff. Samsung, AMD,
Intel, Xilinx, Nvidia, Nokia, Northrop Grumman, Viasat, Aquantia.
IC Manage GDP-XL adds the following features to GDP: Customizable
schemas by project or component, with easily extendable templates.
Supports central, distributed & hybrid development. Web UI, REST API.
AMD, Nvidia, Samsung, Infineon, NXP, Microsoft, Qualcomm, Microchip, Rios
(booth 2317) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
IC Manage PeerCache for "hybrid cloud bursting & HPC cloud apps". Run
existing jobs in cloud in minutes, with minimum cloud storage costs.
PeerCache dynamically determines exact data needed by a job for fast
upload, with no data duplication or synch needed. ESNUG 582 #8. Also
supports pure cloud apps. Delivers scale out I/O. On-prem & cloud
infrastructure-compatible. Got top 5 "Best of 2017". (DAC'17 #5)
(booth 2317) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
Siemens Questa VRM is verification run management system that combines
coverage metrics from formal, CDC, simulation, and emulation engines.
Accellera UCIS standard, and Jenkins regressions. Competes with Cadence
vManager and Synopsys Execution Manager. Now swimming with AI/ML stuff
everywhere; plus Questa VRM does AWS/Azure/GCP. Nokia, Micron users.
(Booth 2521) Ask for Mark Olen. Freebie: espresso & beer
Cadence vManager is just like Questa VRM, but has an API bug systems,
source systems, or agile development systems. Very verificationy.
Deep hooks with Cadence Incisive, Palladium, Xcelium, and JasperGold.
Fujitsu, Analog Devices, ST, Qualcomm, Allegro, Infineon, Teradyne.
"Hey, everyone! vManager is on both AWS and Azure clouds now, too!"
(booth 1511) Ask for Matt Graham. Freebie: lotto stamp
NEW(ISH) - Siemens Solido CrossCheck (formly from Fractal) is a weird
all knowing, all seeing IP checker. It literally compares IP that's in
33 different formats (Verilog, VHDL, .lib, LEF, DEF, GDS, schematics,
etc.) to see how equivalent they are. Sooooooo I can cross check
my Verilog RTL to my GDS2 version of a block to see if they're equal?
Here's the backstory to how CrossCheck ended up in Sawicki's hands:
How Amit & Ravi staged a (tiny) Pearl Harbor on Anirudh & Aart
It does "in-view and cross-view checks to Qualib Enable your IP"??? It
has 300+ IP validation checks across 33 formats At this DAC'23 they'll
be showing its zippy parsing speeds with Calibre DRC. Used by 50+ semi
companies with public endorsements from STMicro, Samsung, and Mixel.
(booth 2521) Ask for Siddharth Ravikumar. Freebee: espresso & beer
Empyrean Qualib also does format consistency checks on hard IP?
But whatever it is, Marvell, SMIC, and HiSilicon use Qualib.
(booth 2537) Ask for Jason Xing. Freebie: fluffy animal
Keysight HUB (former ClioSoft) manages IP enterprise wide. HUB Crawler
crawls internal IP repositories and design data management solutions to
locate and catalog enterprise-wide IP. HUB Security does traceabilty
and geofencing capabilities for IP security and export controls.
Full hierarchical traceability for the Bill-of-Materials (BOM) through
the silicon lifecycle from SoCs to chiplets. "We got lots of customers."
(booth 1531) Ask for Karim Khalfan. Freebie: pens
Keysight SOS7 (former ClioSoft) does HW configuration mgmt
and rev control for Virtuoso, Laker, Custom Compiler, and Keysight ADS.
Built-in IP management and reuse. Soft integrations with in-house
flows. Better security, improved IP traceability, Jenkins integrations.
"SOS7 does cloud, too!" Sparce populate. Hooks to JIRA, Trac, Bugzilla.
Claims new technology results in "97.3% disk file storage savings."
Google, Analog Devices, Infineon, Toshiba, Marvell, TSMC, HiSilicon
(booth 1531) Ask for Karim Khalfan. Freebie: pens
OpenText (Hummingbird) TurboX gives you secure remote access to UNIX
or Windows apps in datacenters. Competes against VNC, RDP. ETX has
20-50% faster response time than VNC for most UNIX apps. Can handle
high latency access (up to 165 msec) pain free for the EDA tool user.
Support for Nvidia GRID-optimized virtual desktop infrastructure.
(booth 1362) Ask for Rod Simon. Freebie: ear buds
Amazon AWS is easily the #1 host for EDA, but not showing at DAC.
Microsoft Azure is now the #2 host for EDA tools. (booth 1443)
Google Cloud is a distant #3 host for EDA tools. (booth 1460)
IBM Cloud is very distant #4 mostly for IBM tools. Not at DAC.
Alibaba Cloud only in China and is unknown in EDA. Not at DAC.
EDITOR'S NOTE: This NOT just a DAC guide. This Cheesy List will get roughly
70,000 pageviews over the next 9 months because engineers use it as a quick
EDA tool shopping guide. If you're an EDA vendor and your tool is missing
(or you have more data for it) send that info to me ASAP. This offer ends
July 19th. After July 19th this document is frozen. - John Cooley
Anyway, I hope this helps! I'm easy to spot: just look for a tall, fat confused
white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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