( ESNUG 438 Item 1 ) -------------------------------------------- [01/18/05]
Subject: the Cooley Analysis of the $285 Million Cadence-Verisity Merger
Hi, ESNUG readers,
I thought before I compiled the user responses, I'd write my own reactions
to this surprise Cadence-Verisity merger news.
My gut reaction is "What the heck is Cadence thinking?!"
With $285 million in cash for Verisity, Cadence is pretty much getting:
1.) The Verisity proprietary language and simulator Specman "e"
plus the verification IP libs written in proprietary "e".
2.) The Axis emulator.
3.) A negligible (under 10%) gain in marketshare in the limited code
coverage/linter market.
Last May I published the DVcon'04 Trip Report and it had a lot of user
survey data showing how speciality functional verification languages
like Verisity Specman "e" and Synopsys Vera were both dying.
From http://www.deepchip.com/items/dvcon04-05.html
"Where do you think specialty functional verification languages be in
5 years? Dead or a growing part of the chip verification process?"
Dead : ########################################################## 81%
Growing : ############## 19%
I consider Vera and e niche languages. SVC-SystemC/System Verilog
eventually obsoletes them.
- Karl Kaiser of EcoLogic GmbH
No Specman. No Vera. We don't use stuff that will be dead in 5 years.
- Winston Worrell of Microsoft
Since SystemC didn't cut it for us, we'll probably use Verisity (for the
first time). I have no real experience of Vera. I hate the idea of yet
another specialty language, so I hope that SystemC SCV or System Verilog
will win out over time. Eliminating PLI/FLI also seems like a win in
terms of sim time.
- Christine Gerveshi of Agere Systems
We've been using "e" for the past design, and it has heavy usage among
our company -- a lot of the IP receive internally comes with "e" code
for verification. Verisity has a pretty mature flow, usage, and
user base.
Janick Bergeron's presentation during SNUG was impressive, and we look
forward to his Verification Methodology Manual. If his methodologies
work well with one language -- System Verilog -- then I can see us
moving in this direction, rather than staying with proprietary solutions.
- Mark Curry of Texas Instruments
We have tried some of the SystemC SCV techniques. Not interested in
the e vs. Vera language war.
- [ An Anon Engineer ]
We use SystemC. There won't be much need for SystemC/Vera/E in a few
years after System Verilog comes on line.
- Mark Dorland of Banderacom
---- ---- ---- ---- ---- ---- ----
Three public languages/approaches are going to replace Verisity Specman "e"
and Synopsys Vera: SystemC, System Verilog, and Assertions.
Cadence has a strong position in SystemC with its NC-SystemC and TestBuilder
tools. Synopsys has a strong position in System Verilog. And Assertions
are still anyone's game.
From http://www.deepchip.com/items/dvcon04-03.html
"Do you see your project using SystemC in the next 6 months?"
not in the
next 6 months : ################################## 68%
yes we will : ################# 32%
I use NC-SystemC to make a tool to analyze STBUS. It's been a valuable
tool to analyze the STBUS Bus. I used NC-SystemC with SimVision for
analyzing the transactions. I feel it will be good if Cadence can come
up with something that is a level higher than transactions, such as a
message so that we can analyze a group of transactions. I also feel that
more demos should be given by Cadence telling about new features of
products and briefly mentioning the old ones.
I was not at all happy with the use of the debugger with NC-SystemC and
wasn't able to use it for my design. Even with help of local Cadence
engineers it took a lot of time to resolve the problem. I finally found
a small work around to do things which was very crude and takes lot of
time to debug.
Code Coverage is not available for C++ code. As I use mostly NC-SystemC,
I want a coverage tool for C++ (NC_SC, SystemC). It is usually needed
for the end of design when the time is less, so I guess most designers
skip this part due to tight deadlines.
- Sudhanshu Chadha of STmicroelectronics
We will go down the SystemC route with out current project and will be
using it principally for verification - including HW/SW co-verification.
We are likely to use the Cadence SystemC tools.
- Fraser Dallas of Motorola GSG (Scotland)
We are actively using SystemC now, and have been for over 1 year for
system level modeling (performance and architecture).
- Scott Runner of Qualcomm
From http://www.deepchip.com/items/dvcon04-04.html
"Do you see your project using System Verilog in the next 6 months?"
not in the
next 6 months : ######################################## 79%
yes we will : ########## 21%
I'm "play using" with the System Verilog features now. We're seriously
considering using many System Verilog 3.0 design constructs, and likely
System Verilog 3.1 testbench constructs in our next design (starting
Q2 2004). I can say it's almost a certainty that we will use some of
the System Verilog 3.0 design features. The "play use" right now is
just to see which features are worth persuing, and which aren't
useful/would cause too much trouble.
This is pushing us towards Synopsys tools; we were impressed by Synopsys
coverage of System Verilog at SNUG. (Although MTI looks good, too.)
- Mark Curry of Texas Instruments
Yes to System Verilog, high level sim, also verification.
- Stefan Rohrer of Micronas GmbH
Yes. I'm looking at the possibility of including System Verilog
verification functions with our delivered coreware. Currently, I'm
playing with a small project using VCS NTB to learn OpenVera to see
if System Verilog will work for us when it has the verification
function (3.1a?)
- George Gorman of LSI Logic
From http://www.deepchip.com/items/dvcon04-06.html
"What do you think of assertion languages and assertion libraries
such as SVA, PSL, OVL, 0-In CheckerWare? Useful or busy work?"
don't use : ############################################### 47%
IBM Sugar/PSL : ################################## 34%
0-in Checkerware : ################## 18%
Verplex OVL : ################# 17%
System Verilog SVA : ####### 7%
Synopsys Vera OVA : ####### 7%
We are writing properties in PSL and our own interface specification
language, named CWL. (PSL is for white box property, CWL is for
black box property.)
- Satoshi Kowatari of Fujitsu
We support SVA/OVA and PSL. Going to try 0-in.
- Umberto Rossi of STMicroelectronics
We use ABV everywhere - designers write PSL to capture assumptions, spec
teams propose white box assertions. We have ABV on std (OCP) interfaces.
We use PSL to trigger coverage and reactive testbenches. SVA looked
attractive but in our time window PSL was ahead in tools support.
- Pete Cumming of Icera Semiconductor
---- ---- ---- ---- ---- ---- ----
On the emulator front, all my evidence points to the fact that Cadence
Palladium owns this turf. Verisity Axis is a 2nd place runner up. There's
even a direct Palladium vs. Verisity Axis benchmark in ESNUG 428 #1 were
Palladium kicks Verisity Axis butt.
From http://www.deepchip.com/items/dvcon04-11.html
"Does your company use HW emulators/accelerators like Cadence
Quickturn Palladium, Mentor IKOS/Meta Systems, Verisity Axis,
Tharas, Pittsburgh Simulations, EVE, or Aptix?"
don't use : ########################## 52%
homebrew with FPGAs : ########## 20%
Cadence Palladium : ###### 11%
Verisity Axis : #### 7%
Mentor IKOS : ## 3%
Mentor Celaro : # 2%
EVE : # 2%
Tharas Hammer : # 2%
Aptix : ## 4%
Alatek : # 1%
Pittsburgh Sim : 0%
Subtracting out all 72% of the "don't use" and "homebrew FPGA" people
leaves only the commercial emulators:
Cadence Palladium : ####################################### 39%
Verisity Axis : ######################## 24%
Mentor IKOS : ########### 11%
Mentor Celaro : ###### 5%
EVE : ###### 5%
Tharas Hammer : ###### 5%
Aptix : ############# 13%
Alatek : ### 3%
Pittsburgh Sim : 0%
Palladium. We regress on Palladium instead of workstations. The setup
depends on the mode used and the size of the design -- no more than
a 1-2 weeks.
- Carl Harvey of Cirrus Logic
Overall, Palladium's ICE is a key tool of our verification process and
low level driver development. It's now well integrated in our design
flow and we use it heavily -- 24 hours per day over 7 days. We plan to
continue using Palladium for larger SoC verification assuming its run
time performance is improved.
- Patrick Rousseau of Philips
From http://www.deepchip.com/items/0428-01.html
When we benchmarked Palladium vs. Axis, Cadence got the in-circuit
emulation working in less than 2 weeks. Axis could not get it working.
When you are not capturing waveforms, Palladium's speed advantage over
Axis is minor. But once you start capturing waves, Axis slows down by
a factor of 4, while Palladium maintains its speed. Once you actually
try to debug something, suddenly Axis is 4 times slower.
- [ The Black Knight ]
---- ---- ---- ---- ---- ---- ----
On the financial side:
Revenue Net Income
--------- ----------
Verisity 2001: $38,737,000 $4,698,000
2002: $52,524,000 $13,350,000
2003: $48,500,000 $8,670,000
Verisity made money for these last 3 years.
Not all the data for 2004 is in yet, but:
Revenue Net Income
--------- ----------
Verisity 2004 Q1: $11,042,000 -$2,212,000
Q2: $13,701,000 -$2,450,000
Q3: $15,519,000 -$3,287,000
Which totals to $7,949,000 in Net Income losses on $40,262,000 of Revenue
for the first 3 quarters of 2004 for Verisity. Ouch! Unless there's
some miracle turnaround in Q4 that wipes out those losses of the prior
3 quarters, Verisity will have been losing money in all of 2004.
---- ---- ---- ---- ---- ---- ----
So, from where I sit, Cadence was going great guns in a growing SystemC;
"me, too" in a growing System Verilog; and it was playing respectfully
in the unresolved but growing Assertions wars. Now for $285 million in
cash, Cadence is getting an EDA company that's lately been losing money
selling what surveyed users say is a dying proprietary functional
verification simulator along with some proprietary verification IP, and
a 2nd rate Axis emulator that Cadence Palladium already beats.
Hence my question: "What the heck is Cadence thinking?!"
This could be some sort of genius move by Cadence, but I just don't see
it from where I'm sitting.
Now let's read what the others have to say about this merger...
- John Cooley
ESNUG/DeepChip.com Holliston, MA
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