( DVcon 04 Item 6 ) ---------------------------------------------- [ 05/26/04 ]
Subject: IBM Sugar/PSL, 0-in Checkerware, Verplex OVL, System Verilog SVA
GIVE ME SOME SUGAR A simple majority (53%) of users are planning on using
some flavor of assertion in their current project. The most popular appears
to be the open IBM Sugar/PSL, followed by the proprietary 0-in Checkerware
and the open Verplex OVL.
"What do you think of assertion languages and assertion libraries
such as SVA, PSL, OVL, 0-In CheckerWare? Useful or busy work?"
don't use : ############################################### 47%
IBM Sugar/PSL : ################################## 34%
0-in Checkerware : ################## 18%
Verplex OVL : ################# 17%
System Verilog SVA : ####### 7%
Synopsys Vera OVA : ####### 7%
The System Verilog SVA and Synopsys Vera OVA assertions are obviously tied
to their respective languages' success. No surprises here. One is seen as
growing (contingent on Cadence and Mentor System Verilog support) while the
other is seen as part of a dying proprietary testbench language.
We will likely use PSL assertions in anger for the first time in our
current project.
- Fraser Dallas of Motorola GSG (Scotland)
We plan to use SVA (currently PSL).
- Stefan Rohrer of Micronas GmbH
We are planning on using assertions. We would like to use OVL because
they did a good job of porting the Verilog assertions to PSL as soon as
PSL has become a standard. I am hoping that they will upgrade the OVL
to System Verilog once the language and tools available.
- [ An Anon Engineer ]
Use 0-in assertions extensively.
- Tom Heynemann of Hewlett-Packard
I'd strongly recommend library-based vendors, such as 0-in, to support
PSL/SVA type assertions as well, which allows the best of both worlds.
- Ambar Sarkar of Paradigm Works
We use OVL for assertions and feel they are useful in both documenting
requirements/assumptions and as an alternative to passive monitor models.
- Mike Peters of Digeo, Inc.
We plan on adding PSL assertions, but not started yet!
- Tom Paulson of QLogic Corp.
We are using assertions now (OVA), and will likely use SVA assertions.
- Scott Runner of Qualcomm
We use ABV everywhere - designers write PSL to capture assumptions, spec
teams propose white box assertions. We have ABV on std (OCP) interfaces.
We use PSL to trigger coverage and reactive testbenches. SVA looked
attractive but in our time window PSL was ahead in tools support.
- Pete Cumming of Icera Semiconductor
We are writing properties in PSL and our own interface specification
language, named CWL. (PSL is for white box property, CWL is for
black box property.)
- Satoshi Kowatari of Fujitsu
Off-the-shelf assertions might be welcome, but as of now, I can't
envision our designers actually writing their own assertions into
their code.
- Aviva Starkman of Northrop Grumman
We use OVL assertions. I consider assertions quite effective way to
prevent bugs.
- Karl Kaiser of EcoLogic GmbH
We support SVA/OVA and PSL. Going to try 0-in.
- Umberto Rossi of STMicroelectronics
We use 0-in assertions now and will add PSL on the next design.
- [ An Anon Engineer ]
Did experimental usage on OVA assertion with VCS. Still feel that
Verilog is sufficient for next project.
- Ajit Madhekar of ControlNet India Pvt Ltd.
Never used assertions. However my opinion on this is a waste of time.
If the assertion is not complete, or certain rules being masked out by
mistake, you still will get non-working chips.
- Alex Chao of Topspin Communications
We have looked at using assertions, but they turned out to be fairly
useless for us at the top-level verification level. We may decide
to phase them in at the design level.
- John Ford of SolarFlare Communications
We are using library based assertions now, and plan to use PSL very soon.
- [ An Anon Engineer ]
I am planning to use assertions and that is going to be PSL.
- Jithendra Madala of QuickSilver Technology
We will use assertions and they will be System Verilog type assertions.
- Sandro Pintz of Precision IO, Inc.
We are definitely plan to use assertion in 2004. Currently, we have not
determine to use language based or library based.
- Hsing Hsieh of Hitachi
PSL and 0-in; started last year. No Vera or "e". Too complicated, too
expensive, and we can do things with C that they can't do.
- [ An Anon Engineer ]
We may use assertions.
- Chandresh Patel of Ciena Corp.
We are planning on using assertions in 2004. Library based. We have
dabbled with OVA and SVA assertions, it seems like a great idea, but it
is hard to get people to really embrace them.
- Mark Andrews of EFI, Inc.
I hope that we include assertions -- don't know what direction yet.
- George Gorman of LSI Logic
For SystemC SVC, it is a good idea and publically available. It's
a good start. More EDA vendors should continue to contribute to it.
We're already using PSL and OVL assertions. We think the 0-in
assertions are too closely tied to 0-in. The 0-in assertions are
well written and supported but it would tie us into the company. We
don't want to be tied down to one specific company.
- [ An Anon Engineer ]
As for where I see assertion tools going? They'll be around in 5 years,
but not everywhere. Constrained random, coverage driven V&V is great,
but I can do that with a Perl script and Verilog simulator just as easy.
- Michiel Vandenbroek of China Core Technology Ltd.
We are also using assertions this year, the library based approach
from 0-in.
- [ An Anon Engineer ]
May use Vera assertions some on the next project, not sure.
- Brad Hollister of NetSilicon, Inc.
We already use assertions, and I think they are essential. We currently
use OVL, but plan to migrate to PSL as it is supported by multiple tools
(Affirma, Specman etc). PSL supports a write once use multiple times
methodology.
- [ An Anon Engineer ]
Yes, we'll be using PSL -- no link to a specific EDA vendor.
- Boaz Ben-Nun of Starcore DSP
I would like to use language specific assertions in the next project.
- Bill Dittenhofer of Starkey
Yes, we are using assertions starting in 2004. On the Verilog side, we
have chosen 0-in. For VHDL, we are looking at 0-in and Cadence.
- [ An Anon Engineer ]
Plan to use PSL
- Ross Smith of Theseus Research
We've been using the OVL library of assertions as a baseline for the past
couple of projects. We chose OVL because it is pure Verilog, we can edit
and modify them, and we're sort of waiting to see what fleshes out in
this area before making any commitment to a more powerful approach. I'm
leaning towards a language-based approach (SVA) when we do switch.
- Jonathan Craft of McData Corp.
We're using the OVL assertions now in a limited way, and starting
to expand. We're also looking at formal property checkers such
as IBM's tools.
- [ An Anon Engineer ]
We are not using Vera or Specman. We have our own assertion generation
method included in our test bench generator utilities.
- Premysl Vaclavik of On Demand GmbH
I believe that System Verilog with SVA will really take off in the USA
once vendors start to support it in a reliable manner. Europe will
stick to VHDL. PSL will be used by Europe and by people in the US who
still use VHDL and Verilog (and who not not transition to System
Verilog). The biggest obstacle for System Verilog is the wealth of
the language, and the fear of newness.
- Ben Cohen
Using some PSL, migrating to SVA as soon as supported.
- [ An Anon Engineer ]
We use/have used several flavors of assertions (OVL to "e" to 0-in).
- [ An Anon Engineer ]
Vera and e will co-exist with tools that support assertion based
methodology. Next project we are definitely planning to use assertions
for the ASIC verification.
- Inder Singh of iVivity, Inc.
We've been using OVL assertions for the last few years, and have been
using Synopsys OVA assertiosn for functional coverage.
- [ An Anon Engineer ]
We used assertions since a long time but more on a module level. I think
to use it on a system level we would need some more conceptual work to
make them really useful.
Since we do have a powerful model checker solution in house we use it
quite heavily on the module level. Once PSL support for this tool is
mature we consider to use PSL with it.
- Thomas Langschwert of Infineon
We will use assertions in 2004, specifically 0-in. Personally I think
a language-based tool is superior to library-based. The trickiest
interfaces in your design usually have properties that don't fit well
with what the library provides. So you need to do some very ugly
hacking. A language-based tool gives you the ability to craft an
elegant solution. Plus, you can always build a library on top of a
language; the reverse clearly doesn't work.
- [ An Anon Engineer ]
I would like to see better assertion support for VHDL -- what is
preventing this?
- John Dean of Philips Research USA
We will use assertions when System Verilog becomes more mainstream.
- Samuel Russell of Ceva, Inc.
We think assertions are the way to go. Just what flavor? We've dabbled
with OVL, but will probably move towards SVA.
- Mark Curry of Texas Instruments
PSL is the way to go for portability and worth it (from my perspective).
- Carl Harvey of Cirrus Logic
Have plans to get lots of 0-in Checkerware inserted into our code.
- Tomoo Taguchi of Hewlett-Packard
We have access to some 0-in Check licenses. So far, it has actually
been helpful although I think the selection of checkers could
be broader.
- Greg Arena of Intel Corp.
We find this very useful and have written it into our verification
process. In future designs we will have the RTL designers use both the
0-in Checkerware assertions and PSL (whichever gets the job done
quicker.) 0-in can target both types of assertions with their formal
tools. In addition, we have successfully used the 0-in "seedless" mode
to capture a known bug and then verify the fix.
- [ An Anon Engineer ]
I think assertion is useful.
- Luo Min of Northwestern Polytechnical University, China
Some PSL, but extra work adding auxilliary HDL statements and module
binding. Difficult to get designer buy-in. Looking forward to SVA as
solution to these issues in PSL. Without enough assertion density the
formal tools not useable.
- [ An Anon Engineer ]
Assertion libs will be great if we can get them for industry standard
buses like PCI-Express, ethernet, etc.
- Terry Doherty of Emulex Corporation
I think assertions are great and wish they were more widely used.
- Maynard Hammond of Scientific Atlanta
Tools like 0-in and Magellan are looking very interesting. We'll
probably try to use them once we'll have some assertions in our RTL.
So we'll start by using assertions for simulation and once it's there,
try them with formal proof.
We'll start using assertion for the next project. Probably PSL or OVA.
- Laurent Claudel of Wavecom
We're leaning towards SVA, so Ketchum is in the lead. A shift away
from spending months and months of time writing directed and semi-
random tests towards a more efficient approach involving assertions
keeps me hopeful.
- Jonathan Craft of McData Corp.
Assertion libraries are good, as they increase observability. Get
designers to sprinkle them within their code. It speeds up debug no-end
by highlighting much earlier where failures have occurred, and minimises
the amount of time spent tracing through design. We use OVL at the
moment; great for Verilog, but too clunkly for VHDL, where you might as
well use the VHDL assert statement. PSL is the way to go, as it works
in both languages, and can be read by multiple tools. In the ideal
world, you would write a set of temporal checkers in PSL which can be
used for checking and constraints in a random tool, and used as dynamic
assertion checks during simulation.
- [ An Anon Engineer ]
We do use OVL.
- [ An Anon Engineer ]
We have had a lot of internal controversy over using an open "free"
assertion library like OVL versus purchasing a library such as 0-in.
We prefer the library approach over language based solutions because
it seems to reduce the effort to put checks in the code, and makes it
more likely designers will add sufficient number of checks to do some
good. We have gone with the 0-in tool because it gives the most "ease
of use". The jury is still out on whether it will ultimately pay off,
but we have found the checks we have added so for to save time in
debugging because the check points out right where the problem is.
On the down side, the compiling of 0-in Checks takes considerably
longer that the OVL approach. Run time overhead is small.
- [ An Anon Engineer ]
We like PSL due to publically available language and its powerful
constructs. Somewhat easy to debug. OVL is great but too simplistic.
PSL can support coverage capabilities, which is quite useful. 0-in
assertions are quite good but it's too much tied into one company.
- [ An Anon Engineer ]
Assertion languages/libraries seem like a good idea, but RTL designers
need to put them in the code as they are writing it. Retrofitting
coverage checkers into existing RTL does not seem worth it. We are
catching many of our bugs these days with assertion checkers written
in Verilog. But debugging the assertion checkers takes a lot of time,
and this would be a much worse issue with coverage checkers which
designers will not be forced to debug due to test failures. Overall,
they are another tool to have in the kit bag but are not going to
solve any revolutionary problems.
- Nathan Dohm of StarGen, Inc.
We went for @HDL @Verifier for PSL static functional verification but
holding it till the PSL next version get approved from Accelera. My
vote is for PSL as lot of EDA vendors are supporting it and can be used
for both static and dynamic functional verification. Also PSL can be
used for functional coverage.
- Jithendra Madala of QuickSilver Technology
We have been using assertions. They are based on modified OVL.
- Robert Young of Intel
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