( DVcon 04 Item 5 ) ---------------------------------------------- [ 05/26/04 ]
Subject: Verisity Specman "e", Synopsys Vera, SystemC SCV, JEDA
DOOM & GLOOM After all that hoopla about Vera and "e", I was surprised to
see 42% of engineers don't even use either of these proprietary testbench
verification languages in their projects!
"What do you think about Verisity Specman "e" vs. Synopsys Vera?
Does your project use either of these?"
don't use : ########################################## 42%
Verisity Specman "e" : ############################ 28%
Synopsys Vera : ########################## 26%
we use both : ### 3%
Even the alternatives get short shrift:
"What about alternatives like JEDA or SystemC SCV?"
we use SystemC SCV : ######### 9%
we use JEDA : # 1%
And this don't look good either:
"Where do you think specialty functional verification languages be in
5 years? Dead or a growing part of the chip verification process?"
Dead : ########################################################## 81%
Growing : ############## 19%
I'm reading waaaaay too many user comments where they're either cheering on
SystemC, System Verilog, or both to eliminate Specman "e" and Vera. Ouch!
I consider Vera and e niche languages. SVC-SystemC/System Verilog
eventually obsoletes them.
- Karl Kaiser of EcoLogic GmbH
No Specman. No Vera. We don't use stuff that will be dead in 5 years.
- Winston Worrell of Microsoft
Since SystemC didn't cut it for us, we'll probably use Verisity (for the
first time). I have no real experience of Vera. I hate the idea of yet
another specialty language, so I hope that SystemC SCV or System Verilog
will win out over time. Eliminating PLI/FLI also seems like a win in
terms of sim time.
- Christine Gerveshi of Agere Systems
We've been using "e" for the past design, and it has heavy usage among
our company -- a lot of the IP receive internally comes with "e" code
for verification. Verisity has a pretty mature flow, usage, and
user base.
Janick Bergeron's presentation during SNUG was impressive, and we look
forward to his Verification Methodology Manual. If his methodologies
work well with one language -- System Verilog -- then I can see us
moving in this direction, rather than staying with proprietary solutions.
- Mark Curry of Texas Instruments
We have tried some of the SystemC SCV techniques. Not interested in
the e vs. Vera language war.
- [ An Anon Engineer ]
We use SystemC. There won't be much need for SystemC/Vera/E in a few
years after System Verilog comes on line.
- Mark Dorland of Banderacom
Is there support for Vera left after Aart de Geus' statements about
System Verilog? Where he predicted the end of VHDL? Assuming that
Aart only wants to suppport System Verilog, he probably does not want
to support Vera, also, as a tool and a language. With Synopsys not
clearly committed to verification we are glad that we decided in favour
of Verisity.
Can anyone remember that Synopsys was in the emulation business - and the
IKOS deal obviously was also not important enough? Who still knows
something about Model Sources or LM1xxx-boxes at Synopsys? Has anybody
heard of Arkos? What happened to Eagle-I or Cyclone? Wasn't Scirocco
announced to be the leading VHDL simulator? ... is it necessary to give
more examples concerning the obscure verification stategy of Synopsys?
Against the background of these experiences it is not very convincing to
read that Synopsys is committed to verification -- and therefore I'd
expect the Vera tool to suffer the same fate of Eagle-I, Arkos...
- Andreas Dieckmann of Siemens AG
Now we are using Vera. This decision wasn't up to us, but according to a
customer request. We used to use Specman in the previous project, and we
were very pleased with it. The only problem with Specman is its
constraint solver, which can't solve many basic cases. I know that they
are working on better constraint solver. I think that "e" is a simpler
language, and more powerful one.
- Dorit Moshe of IBM Israel
I am currently using only Specman. I have never taken a look at Vera
since it's not part of our process. I believe "e" will grow in
importance over the next 5 years. It's already been very helpful
identifying things we overlooked and will only become more important
as our designs become more complicated.
- Greg Arena of Intel Corp.
Based only on reading Janick Bergeron's book "Writing Testbenches" it
looks like "e" is a better language, but I have no experience.
- John Dean of Philips Research USA
Tried both, for general usage I prefer unified language/simulator (System
Verilog).
- Stefan Rohrer of Micronas GmbH
We are using Specman more frequently. It has proved to be a useful tool.
We've had some who have tried Vera. This has not been as successful as
Specman. I see Vera morphing into System Verilog. I'm not sure what the
future will bring in this area.
- Maynard Hammond of Scientific Atlanta
We use Vera for test environment.
- Tom Heynemann of Hewlett-Packard
We use Vera and 0-in assertions. All indications are that Vera will die
if System Verilog delivers. Don't know if there are any VHDL designers
that use Vera. I am curious to find out if they have started to abandon
Vera already.
- [ An Anon Engineer ]
We have been using Vera heavily for the past 7 months.
Prior to mid 2004, IMO, Verisity was ahead in coverage and GUI in
particular. However, Synopsys has made great improvements and built
their solution around a practical methodology (RVM). In constraint
solving, language, and methodology, Synopsys is a better solution.
Verisity still may have a better GUI.
- Scott Runner of Qualcomm
I saw "e" at DAC last year and it looked extremely complicated. Have
never looked at Vera. There has been interest in Verplex BlackTie.
- Aviva Starkman of Northrop Grumman
We have used Vera. It can help for complexed things, but can make easy
thing complexed also. We don't currently use it because it isn't worth
the tradeoff on this project. Haven't use Specman myself, but have
heard it is also complexed. Higher level solutions will be part of the
future, but haven't investigated enough yet to tell which type.
- [ An Anon Engineer ]
We use Specman. I have not looked closely at Vera lately. Specman was
significantly ahead when we made our decision. Pre-silicon validation
has to increase in productivity. These tools allow that. Naturally, if
something comes along that is better, they will go away. We are
building validation IP. Anything that comes along will have to address
this investment.
- Robert Young of Intel
e is probably still slightly ahead in term of power of the language.
However, Vera, especially when merged into System Verilog, will benefit
from tighter integration with Synopsys simulation tools.
We already do use SystemC for some complex verification activities. e is
also widely used. Not Vera. Personal guess would be that SystemC and
System Verilog will share the majority of the market in 5 years from now.
- Frank Ghenassia of STMicroelectronics
We have one engineer that has used Synopsys Vera and has expressed
satisfaction with it. I also saw a demo of Specman once and it seemed
impressive. But here, we write our own verification tools in Tcl.
Modelsim's integrated Tcl support makes this a very viable option.
- [ An Anon Engineer ]
We use both. Verisity is ahead in a number of areas: the GUI, coverage
monitors, and I particularly like the ability to create a signal access
using string manipulations on the fly (no "ports" like in Vera).
Cadence's TestBuilder seems good as well, especially since it uses C
rather than a proprietary language. I don't see any use for any more
proprietary languages. SystemC is coming, but I personally will wait a
generation or two before trusting it the tools. We have been using
assertions for years, and we plan to continue. I prefer library based,
since they are probably less error prone, and are easier to use/insert
(leading the designers to insert more of them).
- [ An Anon Engineer ]
I think people will continue to use Vera and E for a short while. System
Verilog verification extensions will be the way of the future. People
with a large investment in the old languages will lag in adopting
System Verilog.
- James Lee of the ASIC Group
Don't use either.
- Tomoo Taguchi of Hewlett-Packard
We use Specman. We evaluated Vera 4 years ago and decided to go with
Specman based mostly on gut feel that Specman would get better market
place penetration, they had more knowledgable AEs, and more mature
documentation/methodology. The tools looked relatively equal all
considered. I think in 5 years it will extremely difficult to justify
and expensive HVL when SystemC SCV has a few more critical features
added (like functional coverage).
- [ An Anon Engineer ]
I don't need anything other than normal Verilog myself.
- Doug Hester of Chip World Consulting
We use static formal and neither Specman nor Vera. For verification we
have a combination of FPGA based platforms and an extensive test plan
based on golden-model simulator to generate our reference test vectors.
- Yuval Itkin of Metalink Broadband, Ltd.
Dead. Replaced by System Verilog.
- [ An Anon Engineer ]
Vera seems to be ahead. Everyone is talking about it. We are also
planning to use it.
- Sachin Mohan of Cypress Semiconductor
no Vera, removing e
- Ross Smith of Theseus Research
Currently using Vera. Used Specman at my last company. Both are good.
I would say they are equivalent. I think they will be going strong in
5 years.
- Brad Hollister of NetSilicon, Inc.
I have not used Vera, but have used Specman. I would love to see the
third party, specialty languages go the way of the dinosaurs. I have
not had time to delve into System Verilog, but I like the sound of it.
I have bought into the usefulness of the *methodology* behind the
Specman/Vera world (randomized testing of blocks), and the Specman tool
offers ways of controling/viewing/analyzing the results, so they are
"convenient" in that sense, but learning a new language is cumbersome
(though I suppose that System Verilog will have some "new" concepts
and syntax, too).
- [ An Anon Engineer ]
We've evaluated Vera and Cadence TestBuilder. Vera definitely seems
easier to use. It has the "look and feel" of Verilog and its object
oriented capabilities are more restrictive than C++. This is good for
hardware engineers, who are very likely to get into trouble with the
nuances of C++. Unfortunately half our licenses are Cadence NC-Verilog,
and so we need to go with TestBuilder.
Hopefully System Verilog will obviate the need for specialty HVLs.
Everything should go smoothly now that it's in the hands of an IEEE
committee (NOT!) There's too much talk about the language; not enough
about the tools. Time for Synopsys to man up and release a solution.
Once a good one is out there, it will be adopted and no one will care
about the standardization process.
- [ An Anon Engineer ]
We like Specman, but couldn't afford it. So we ended up with Vera.
Both are better than coding testbenches in RTL Verilog. Vera and e will
be dead in 5 years if System Verilog takes off.
- Terry Doherty of Emulex Corporation
We've been using Specman for 2.5+ years. Definitely an important part
of our overall strategy.
I've used both and Specman's defintely ahead. Verisity's focus on all
aspects of functional verification, rather than viewing this as a tool
to push more licenses of other products, is a sure thing.
That plus the Synopsys sales folk aren't the easiest to deal with...
As things progress, high level of abstraction functional verification
languages are going to become more and more important.
- [ An Anon Engineer ]
I prefer C/SystemC over other HVLs; I think it's better for portability
and more people know it.
- Carl Harvey of Cirrus Logic
We use Vera. Currently Specman is better but not as much as it used to.
Verisity's future is to be bought by one of the 2 or 3 big ones or to be
dead due to $ issues. I think that this verification lang issue is
growing but not as much as it growth in the past. Assertion is (to my
opinion) is a must.
- [ An Anon Engineer ]
We rely heavily on Vera to perform our ASIC verification, and have been
doing so for more than four years. We did an initial comparison of the
two languages early on, and went with Vera due to its similarities with
Verilog and C. Can't do much of a comparison beyond that. I think Vera
and Specman will be nearly gone in 5 years if System Verilog finds
its stride.
- Jonathan Craft of McData Corp.
We've been using Vera for the last 3 years. We have 250,000 lines of
code of Vera and are true Vera experts. But, we're working to migrate
off these proprietary languages like Vera and "e" because of lack of
library support, lack of tool support, and they make marginal resume
"fodder" for the bulk of our group.
- [ An Anon Engineer ]
We use Specman. Verisity guys do a very good job here giving some basic
consulting. Also Specman is acknowleded as the more mature tool. We
will continue with Specman because they also have some good concepts
in the area of verification IP and verification strategies. I think
functional verification will grow. At least the functional coverage
part is becoming more important so that we need to hold on using these
kind of tools.
- Thomas Langschwert of Infineon
Synopsys Vera seems to have a stronger hold here in Moto Munich.
- [ An Anon Engineer ]
We are a Synopsys Vera company, we are happy with Vera even though it
slows down our simulation down. But we feel it has good, near term
future with integration with VCS. Specman probably doesn't have the
same luxury. Vera/Specman will probably die or evolve itself to do
something similar what SystemC folks are talking about.
- Subbu Muddappa of Woodside Networks
Do not use either. Do not have dedicated verification engineers and
design teams don't see enough value to merit purchase and learning
curve. No plans for assertion usage this year.
- [ An Anon Engineer ]
We've used "e" on several projects - hands down a winner relative to
Vera. It's hard to say where they will be in five years, although one
thing is for sure - the functional verification languages will have to
figure out a price structure that keeps them competitive as the simulator
vendors keep bundling verification features into their simulators.
- [ An Anon Engineer ]
Have not used either tool. We don't want to get tied into a proprietary
tool because we supply IP.
- Samuel Russell of Ceva, Inc.
We've used Specman on a limited basis to do some block-level
verifications. It does work, and the support is pretty good, but from
a project management perspective there's always the uneasy question of
how much time to budget for the learning curve of YACVL (Yet Another
Convoluted Verification Language), whether the design team's time is
better spent on tasks other than verification, versus the cost/risk of
looking for outside (and potentially unproven) resources to do the
verification work in a more independent manner, etc.
- [ An Anon Engineer ]
Like Specman a lot. We have some designers who used Vera before but
they prefer Specman now. Specman is our first choice.
- Inder Singh of iVivity, Inc.
No verification language outside the simulator has a future.
- [ An Anon Engineer ]
We are using Specman. When we did an evaluation of Specman and Vera
two years ago, it looked much better to us than Vera was. But it looks
like Vera as filled the gap since that time (for instance, you have now
the "aspect oriented" coding style available) and being much cheaper
make it very interesting. It looks like being the first with a serious
tool on the market, Specman still has an edge but Vera is catching up.
In 5 years .... Vera will be System Verilog and if all the simulator
supports it, Specman could have a hard time then. Having verification
and RTL running with the same tool makes life easier.
- Laurent Claudel of Wavecom
We are a Verisity e house. Versity is definitely ahead in technology
while industy usuage seems to be split 50-50 between e vs Vera. My
personal opinion is that high-level-verification-languages will
eventually be taken over by the simulators (System Verilog), at
least my hope.
- [ An Anon Engineer ]
We use Specman. Vera is not on our radar.
- [ An Anon Engineer ]
We use Specman e. The methodology and techniques developed by Verisity
are about 1.5 years ahead of Synopsys Vera (and why did they buy Qualis
to get input to help close the gap). I see speciality functional
verification languages as still being necessary in five years time
(however much you kludge things together, a design language will never
be rigorous enough for design and verification), and will be increasingly
"glue" languages which allow multiple tools to work together.
- [ An Anon Engineer ]
Specman "e" is better after examining both. We use it. Specman is
ahead, Vera is behind. Specman will alive and kicking 5 years from
now. This is the future.
- Boaz Ben-Nun of Starcore DSP
We only use Vera, so I cannot judge them. I believe SystemC SCV will
end these two languages.
- Gao Peng of Tongji University, China
We used "e" on our previous project and it worked well in general, but
we decided to switch to SystemC/SCV because of cost, and a desire to
use an open standard language. We don't think specialized languages
will survive long term unless the cost structure radically changes.
- [ An Anon Engineer ]
We use Synopsys Vera, the verification team seems to like it. No
experience with Specman.
- Nathan Dohm of StarGen, Inc.
Used Specman and E. Nice tool and language, easy to use and we got
some bugs with it, but also missed many other bugs which had to be
found using Verilog and assembly tests, both hand-written and
generated using Perl scripts. So, it is a useful addition, but not
the be all and end all. Don't use Vera because they showed up on
our doorstep a year after Verisity with a too-juicy marketing spin
and no discernable differences with (advantages over) Specman/E.
- Michiel Vandenbroek of China Core Technology Ltd.
We're not current users of e or Vera. For the future we're focusing on
the System Verilog 3.1 testbench constructs, but those are probably
12-15 months out. Yes, we'll use assertions in 2004, starting with the
canned OVL superset provided with VCS and then branching out into
building our own using System Verilog assertion syntax (not PSL).
- [ An Anon Engineer ]
Touched some of "e" before, a good language. Just heard of Vera, no
depth knowledge.
- Fred Liao of S3 Graphics
Have not used Vera for a long time. Never used Specman. The
functional verification languages will continue to be used more by
others.
- Chandresh Patel of Ciena Corp.
We don't specifically use Vera. But our DesignWare VIP requires Vera.
- [ An Anon Engineer ]
We currently use Specman 'e' and are not considering alternatives such
as Vera for the time being. It is posible we will drop 'e' in favor
of PSL and System Verilog constructs.
System Verilog and Verilog 2001 look very exciting. They adopt much
of the system language features that VHDL has had, like configurations,
plus sucking in random testcase generation capabilities, temporal
assertions, interfaces, classes, and simplified interconnection. When
System Verilog is available, we should be able to eliminate Specman
from our tool box. If it is available in our synthesis tool and
Modelsim, maybe we should begin using it.
- Jim Lear of Legerity
I'm playing with Synopsys NTB now to learn OpenVera to compare it with
my Specman experience. I like the idea of OpenVera moving into System
Verilog. I don't have a good picture of how we will use them yet. We
found great resistance to including Specman ecode in our coreware
deliverables. I'm hoping that System Verilog will be better accepted.
- George Gorman of LSI Logic
These are yet another language. We don't use either.
- Mark Andrews of EFI, Inc.
No comment on 'e' vs Vera. Porting from Vera to System Verilog is easy,
so that drives the decision. I think both languages are dying. Why do
we need more languages when System Verilog solves the testbench issues
(mostly). I think SystemC and SCV will be around but for the more high
level architectural phases of projects.
- Sandro Pintz of Precision IO, Inc.
Current under evaluation stage but "e" seems has more complete approach
to verification. Our current project doens't user neither but plan to
migrate. Current enviornment is all VHDL testbench. Most people think
"e" is ahead, may be better or more aggressive marketing. I think these
language "e" or Vera will not converage on language but it's feature
will be more alike. HVL will probably evolve and more verification
focus construct will be adopt into VHDL 200x.
- Hsing Hsieh of Hitachi
I have no plans to use either of these languages. It seems like System
Verilog is more where we would like to be. Its backwards compatibility
with Verilog makes it more desirable.
- Greg Schmidt of General Dynamics
I used Specman before and also used little bit of Vera. Both tools are
good and especially Specman was better than Vera a year back. But I
recently heard that Vera improved its constrained random generation,
aspect orient concepts and added functional coverage. The only problem
with these tools are that they are expensive. Currently I am using SCV
for constrained random generation and for testbench transactors and it
is going well. The only disadvantage of using SCV is that currently
it is lacking of functional covergae and dynamic constraints. (There
are indirected ways to get this working).
- Jithendra Madala of QuickSilver Technology
There is too much overhead for e or Vera. I have used Vera sometimes
ago, never used e. There is always need for those special functional
verification languages, but I don't think they can grow.
- Edmond Tam of Global Locate, Inc.
We don't use any of those types of tools. We have our own tools built
around PLI, perl, etc. I've looked at them before, but am not really
that high on most of those tools.
- Jerry Roletter of ATI
Well versed with Vera, but peers prefer Verisity.
- Shivi Sidhu of Crimson Microsystems
We have an enormous amount invested in Vera at this point (probably 5+
man-years of dev time). I used Specman long ago, at that point I think
they were neck-in-neck (possibly Specman ahead on features and Vera on
ease-of-use). We have looked into JEDA as an alternative. We are
definitely investigating assertions, language-based.
In five years, I think it will be hard to justify these languages at
all. Synopsys has nearly doubled the price of a Vera runtime in the
last 4-5 months (from $12k to $20k -- don't believe me? try to get a
quote right now). System Verilog is the _right_ way to do it, just
bundle all this up into one tool again, with one simulator core engine.
Even our Vera-advocates agree with that.
- [ An Anon Engineer ]
Do not use either Specman or Vera. I believe they will both go away as
System Verilog becomes more robust with assertions.
- Don Monroe of Enterasys Networks
We will not use Vera nor Specman. They are expensive, hard to use, slow
(don't compile directly into the kernel as SystemC does via direct
compile). If I were to use either one, it would probably be Vera.
- Bill Dittenhofer of Starkey
We are going to use SystemC SCV to run transaction-based verification
at unit level and system level. We also intend to run HW/SW co-sim
under SystemC (with either or both C & C++ SW).
- Fraser Dallas of Motorola GSG (Scotland)
There is something that I think is not well-known that I would like to
share: Anyone doing verification can use SCV -- even those that don't
model in SystemC. An engineer who is writing tests at the transaction-
level can use SCV to generate constrained random transactions. I have
a standalone SystemC program that generates a file of instructions. This
could easily be ARM, PCI, or any other type of transaction. These
transactions are read by the testbench and the test begins. I used to
try to generate the transactions in Verilog, but Verilog doesn't provide
good randomization functions or constraints. Some people use Specman to
generate these vectors, and Specman does have good randomization, but it
is expensive and "e" is not easy to learn, where as most people already
know C. I personally think using SCV to generate the transactions is an
effective approach -- and it can be downloaded for free.
- Greg Tumbush of Starkey Labs
Have not seen JEDA. Doubt SCV will be used.
- Winston Worrell of Microsoft
We used SystemC SCV for 2 projects, forget it ... un-practical. Usable
but hard to set up, so we switched to Vera. We're now using 0-in
assertions at the moment.
- Remi Francard of STmicroelectronics
I still have to explore SCV. I need randomization capabilities but I
feel the documentation is not explanatory enough, and should be
supported by more some more usage tips and examples. Additionally I
feel some demonstration by Cadence would be useful.
- Sudhanshu Chadha of STmicroelectronics
Don't know anything about JEDA or SystemC SCV.
- Brad Hollister of NetSilicon, Inc.
JEDA is a little too late to market, although may gain a place in
universities as a free language to try.
- [ An Anon Engineer ]
JEDA and SystemC SCV? Don't know but probably too high level.
- Boaz Ben-Nun of Starcore DSP
Not JEDA. Maybe SCV.
- [ An Anon Engineer ]
JEDA is a non-starter, yet another proprietary tool with far less
support than Vera or "e". SCV is a rational alternative to some
people, at least it uses a standard language C++ so it has tools
and libraries support.
- [ An Anon Engineer ]
SystemC SCV is interesting, but there are two problems most RTL coders
can barely spell C++ and the technology is still somewhat immature.
- Terry Doherty of Emulex Corporation
We briefly looked at JEDA. Maybe they have good technology, but they
couldn't clearly articulate why their tool is superior to Vera, which
is now bundled "free" with VCS.
- [ An Anon Engineer ]
I'm not familiar with JEDA.
- Dorit Moshe of IBM Israel
I haven't worked directly with JEDA, but the key attraction behind both
SystemC and JEDA is the lure of independence from being stuck on one
major EDA vendor.
- Ambar Sarkar of Paradigm Works
I have no idea on JEDA as I know that it came from the people who created
Vera.
- Jithendra Madala of QuickSilver Technology
JEDA I know very little about.
- Sandro Pintz of Precision IO, Inc.
I can not answer alternative like JEDA but SystemC is definitely worth
considering for high level modeling.
- Hsing Hsieh of Hitachi
I like the idea of JEDA but don't think it's viable unless its well
supported. Maybe it should be open sourced.
- [ An Anon Engineer ]
We also engaged with the JEDA folks (B1Lab?) but chose Specman due
to greater maturity.
- Michiel Vandenbroek of China Core Technology Ltd.
We are exploring using JEDA and have it installed.
- Shivi Sidhu of Crimson Microsystems
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