( ESNUG 428 Item 1 ) -------------------------------------------- [04/28/04]
From: [ The Black Knight ]
Subject: One Designer's Cadence Quickturn Palladium vs. Axis Benchmark
Hi John,
Please keep me anonymous.
At the time we started our eval, Axis said they had a procedure to allow
them to run hardware and software on a computer, so that what didn't
run on their emulator box would run on a workstation. Unfortunately,
it turned out that the Axis Verilog simulator wasn't IEEE compliant, so
we had to modify our Verilog code to do this. It took almost 2 months
to do this with the Axis AE here most of the time.
Cadence, on the other hand, was quite open that they couldn't do this
automatically. Actually, being up front about what they had and didn't
have worked in Cadence's favor during our eval. (Back in 2002 - 2003,
Palladium's bring-up procedure needed a lot of hand manipulating.) This
time around, the Palladium AEs were able to port and compile our design
in one week.
Palladium & Axis vs. VSC & NC-Verilog:
For simulation/acceleration (SA) only, you can take your circuit and
create a testbench on the box/host computer, maybe running at speeds of
1 - 10 KHz (not anywhere near full speed of ~100 KHz), and both Cadence
and Axis emulators were okay for this purpose. We were able to look
at internal signals, displaying them with the Debussy waveform
viewer on the host.
Neither emulator is useful for small circuits (under 50K gates) due to the
overhead for set up and compiling. In contrast, a software simulator
has less overhead, because you just compile and run it. For 40 to 60K
gates, a software simulator is as fast or faster than an emulator. For
500,000 to 1,000,000 gates, an emulator is much faster if it is a long
run, but not necessarily for very short runs. A software simulator could
simulate a few hundred-thousand cycles of a one million gate circuit in
30 minutes to an hour.
Axis had a fancier front-end for SA, which shows better in evaluations.
However, I'm not convinced that it results in more productivity in the
long run. Experienced users typically shy away from GUIs and fancy
interfaces once they become familiar and comfortable with a product.
They typically write scripts to hide all these features, and run in
batch environments. This is how to get the most performance.
Palladium vs. Axis In-Circuit Emulation:
With Palladium, we had a processor and other logic inside it running
software code, connected up with external devices through speed bridges
and JTAG pods. We took real communication ports and put them through
the speed bridges. The other side interfaced to the Palladium box
buffering the data coming in and playing it out slowly with a 1000:1
speed conversion.
Cadence (first as Quickturn, then as Cadence) has agreements with most
manufacturers of speed bridges, so the Cadence team had the connections
and the experience. Axis didn't and it showed glaringly in the
in-circuit benchmarks we tried with their emulator.
In the in-circuit mode, the emulator must run full speed, and never break
the connection with the external speed bridges. If the clocks or control
signals stop for any reason, (such as displaying internal signals), the
speed bridges and/or JTAG pods crash, severing the connection. This
forces us to reset the design and start over, making in-circuit emulation
useless.
Also, we needed an operating system and debugger (e.g. VxWorks Wind River,
MetroWerks, Linux) to view, run, modify, and control our software code.
Most users like us do not have the expertise to easily get such an
operating system / debugger to run quickly. We depended on Cadence and
Axis to help us with this task. This is a specific one-time task that
requires a great deal of intimate knowledge of the chosen operating
system (e.g. MetroWerks), emulator, and the chip design. Excellent AE
support is critical to the success of this task.
When we benchmarked Palladium vs. Axis, Cadence got the in-circuit
emulation working in less than 2 weeks. Axis could not get it working.
They tried for many months, and they still don't have a usable system
to debug code. It was hard to tell whether it was a lack of knowledge
of the Axis AEs or inherent limitations of the Axis system itself
that caused this.
Palladium vs. Axis Speed Comparisons:
There are two main areas here -- compilation speed and run speed. The
Palladium is processor based, and as such, it is easy to compile the
design into the box. Their compile speed is on the order of 30,000,000
gates / hour on a single fast CPU. Cadence also supports incremental
RTL compile, further reducing compilation time.
Axis is FPGA based. They have many (80 - 240) FPGAs that all need to be
programmed, so to get any reasonable compilation speed, the user must
have a farm of 80 - 240 CPUs all running the place and route software.
This consumes the farm completely for the entire process, which many
times takes well over an hour. If multiple designers want to recompile
their design at the same time, they either fight for the same 80 - 240
CPUs (doubling the compile times of both designs), or one will have to
wait until the first user is finished.
Palladium is multi-user. For example, for a 16 million gate box, we
could fit two 8 Million gate designs simultaneously. We would
have multiple engineers using Palladium at once, and we wouldn't even
know that the other engineers were there. Axis keeps promising this
same feature, but haven't delivered it so far as I can see.
With both Palladium and Axis, we could easily look at internal signals.
When you are not capturing waveforms, Palladium's speed advantage over
Axis is minor. But once you start capturing waves, Axis slows down by
a factor of 4, while Palladium maintains its speed. Once you actually
try to debug something, suddenly Axis is 4 times slower.
For simulation, both Palladium and Axis was 100K to 300K times faster
than VCS/NC-Verilog simulation. The Axis emulator was slightly slower,
but that wasn't important as far as we were concerned.
At the time, Cadence had the only viable in-circuit emulator around.
After this eval, we leased Palladium last year.
- [ The Black Knight ]
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