( DVcon 04 Item 4 ) ---------------------------------------------- [ 05/26/04 ]
Subject: System Verilog
WAITING FOR GODOT Not wanting to get trapped into using a proprietary
language in their own chip design, the bulk of chip designers are waiting for
the Mentor and Cadence toolsets to fully commit to Synopsys System Verilog,
leaving only 1 in 5 engineers today actively using System Verilog.
"Do you see your project using System Verilog in the next 6 months?"
not in the
next 6 months : ######################################## 79%
yes we will : ########## 21%
And asking only those who are or will be using System Verilog:
"Do you plan on using the System Verilog 3.0
designer or the verification extentions, or both?"
verification : ##################### 63%
design : ## 6%
both : ########### 32%
In contrast with the SystemC phobia most chip designers have, a whopping 38%
of today's System Verilog users are talking about using it for design. Why
that's interesting is that the System Verilog capabilities in Design Compiler
are still in beta right now. That is, these designers are commiting to
System Verilog now even though they can't actually design in it today. Whoa!
Still, if we're talking purely about user verification market share here,
SystemC's 1 in 3 use vs. System Verilog's 1 in 5 use does bear noting...
I do not see my project or me using System Verilog any time soon. I can
see System Verilog trying to use me, though.
- Simon Ramirez of Synchronous Design, Inc.
I'm "play using" with the System Verilog features now. We're seriously
considering using many System Verilog 3.0 design constructs, and likely
System Verilog 3.1 testbench constructs in our next design (starting
Q2 2004). I can say it's almost a certainty that we will use some of
the System Verilog 3.0 design features. The "play use" right now is
just to see which features are worth persuing, and which aren't
useful/would cause too much trouble.
This is pushing us towards Synopsys tools; we were impressed by Synopsys
coverage of System Verilog at SNUG. (Although MTI looks good, too.)
- Mark Curry of Texas Instruments
System Verilog use is in planning stages. Will use it for RTL design of
internal and customer designs. System Verilog adds some really nice
features to Verilog, esp for interfaces and data structures that removes
lots of hassles one frequently bumps into in bus-based SoC designs.
- Joachim Strombergson of InformAsic AB
No plans for System Verilog, although my bad experience with SystemC
makes me want to investigate System Verilog more.
- Ty Gallander of Conexant
Yes, Test benches, mainly verification extensions, partial designer.
Modelsim and Systemsim moving to Modelsim only.
- Winston Worrell of Microsoft
Our plan is to use the designer extentions in the next 6 months. NC-Sim
and VCS. Will evaluate the System Verilog for our next design.
- [ An Anon Engineer ]
We do not intend to use System Verilog until there is better
standardised implementation from the major EDA vendors.
- Samuel Russell of Ceva, Inc.
System Verilog looks promising. We like the concept. We won't use it
until all of our tools in the flow support it. We've barely gotten to
this point for Verilog 2001. I don't think we will adopt it yet
for a few years.
- Maynard Hammond of Scientific Atlanta
Yes. Future projects internally and with different customers. Design
extensions first, then verification extensions as needed. Currently
doing some experimentation. Vendor is TBD.
- James Lee of the ASIC Group
No immediate plan to use System Verilog, except for System Verilog
assertions (SVA) which are eminent.
- Scott Runner of Qualcomm
Yes. We are considering using it for verification extentions; will wait
on designer extentions till System Verilog is more widely supported. We
plan to start out using Synopsys' VCS.
- [ An Anon Engineer ]
God, I hope so... designs that go from SystemC to VHDL suck.
- [ An Anon Engineer ]
We plan on using the System Verilog 3.0 (design) and we will start using
3.0a (verification) as soon as the EDA vendors start supporting it in
their flows (simulators/debuggers etc). We may change our plans if
there is no EDA support for 3.0a
- [ An Anon Engineer ]
NO
- S.K. Rajadurai of Lattice Semiconductor
No.
- Frank Ghenassia of STMicroelectronics
Yes to System Verilog, high level sim, also verification.
- Stefan Rohrer of Micronas GmbH
No System Verilog yet.
- Pete Cumming of Icera Semiconductor
Not in the next 6 months, although System Verilog is an attractive idea.
- Christine Gerveshi of Agere Systems
Not in the next 6 months, but I think in the next year, I think there's
a good chance, so long as the tool support is there.
- John Ford of SolarFlare Communications
Yes... I have some whining to do here. System Verilog has been out for
almost two years and there are already books selling at $180 a piece.
But the tools are not ready for production use yet. They are still
Beta level. I am finding that we will have to pay more money to for
System Verilog from EDA companies. No wonder EDA companies are the ones
that are sponsoring proliferation of new languages.
- [ An Anon Engineer ]
Not using System Verilog, no current plans to use it. VHDL meets our
needs for the present, it was always a system-oriented language.
- [ An Anon Engineer ]
No.
- Greg Arena of Intel Corp.
No view for time being, except perhaps to improve RTL productivity.
- Benoit Clement of STMicroelectronics
No.
- Tomoo Taguchi of Hewlett-Packard
We'll be using System Verilog feature whenever all the tools that we are
using will be suporting it for RTL as we've done for Verilog 2001.
- Laurent Claudel of Wavecom
Not sure about the testbench part (as in Vera), but I definitely expect
using SVA (assertions). However, will probably not start using
productively until Cadence/Mentor support this as well.
- Ambar Sarkar of Paradigm Works
Yes, System Verilog will be used. Superlog was already used on projects.
Initially 3.0, using Verification features of 3.1a as they become
available. Looking for support from the "3rd" vendor (Cadence).
System Verilog in Synopsys HDL Compiler.
- [ An Anon Engineer ]
We cannot afford to make such a major shift so early. We have to wait
for the battles around System Verilog to be settled, and then the tools
have to mature, and then the first projects have to be carried out
successfully.
- Andreas Dieckmann of Siemens AG
No System Verilog in plan for us.
- Thomas Langschwert of Infineon
We are planning on "seriously" using System Verilog in the near future
for two main purposes: Assertions and Behavioral models in our test
bench. We have chosen SV/SVA support from Synopsys VCS. Our first goal
is to code up our own SVA assertions in our RTL, and get the benefit
from dynamic checking. Later on, we will evaluate formal tools for
static checking/proof of our assertions. In addition, we will use
System Verilog to add modules to our test bench in a more C-like fashion
(e.g., using structures, etc.)
- Dan Steinberg of Integrated Device Technology
Yes, use Synopsys System Verilog.
- Luo Min of Northwestern Polytechnical University, China
Yes. Verfication extensions for module level and chip level testbenches.
We are using Mentor's Modelsim, again Modelsim supports Verilog, VHDL,
SystemC & System Verilog. I'd like to use a simulator that supports all
the current & emerging standards.
- Shreyas Shah of Aasan Networks
No.
- Carl Harvey of Cirrus Logic
No, we are VHDL house.
- Alex Chao of Topspin Communications
On the verification side, all of our work goes on in Vera. We like most
aspects of the language except that it is proprietary and Synopsys
changes little things from time to time without warning. We very much
want to move to System Verilog on the verification side when it is ready
for primetime. That won't happen in the next six months. I don't see
any of our designs moving away from vanilla Verilog any time soon,
although some of the 3.0 features (interfaces come to mind first)
may pull us there sooner than later. It will probably boil down to when
third party tools (waveform viewers, linters, etc.) fully support 3.0.
I'm sure we'll stick with the VCS flavor of System Verilog, regardless.
- Jonathan Craft of McData Corp.
No
- [ An Anon Engineer ]
No
- Willem Sloof of Philips Microdisplay Systems
We don't currently use System Verilog and don't plan to within the next
6 months.
- Michael Condon of the Naval Research Lab
No for all the questions. We develop all our designs and sometimes
test-bench in VHDL.
- [ An Anon Engineer ]
We don't use System Verilog at the moment, and I can't see us using it
for the foreseeable future.
- [ An Anon Engineer ]
Yes, SVA (assertions), Synopsys
- [ An Anon Engineer ]
No. Although Mentor claims to have added some support in Modelsim, we
have not tested. Probably will take a look when more mature, and when
supported from all tools (e.g., synthesis).
- [ An Anon Engineer ]
Won't be using it.
- [ An Anon Engineer ]
No plan for System Verilog in the next 6 months or even more. We are
an IP company so we sell RTL. We cannot use System Verilog until the
majority of our customers wants it -- otherwise we will have to maintain
both System Verilog and Verilog 95 code.
Assertion -- we will use PSL since it is widely supported my multiple
EDA vendors. Verification extensions: we use Specman and we are
happy with it.
- Boaz Ben-Nun of Starcore DSP
No.
- Wim Meeus of Universiteit Gent, Belgium
No to all System Verilog questions. Verilog-2001 combined with a true
verification language fits our methodolgy needs.
- [ An Anon Engineer ]
No
- Inder Singh of iVivity, Inc.
No, we will not use System Verilog in next 6 months.
- Gao Peng of Tongji University, China
No
- Stone Shi of STmicroelectronics
No plans.
- [ An Anon Engineer ]
NO
- [ An Anon Engineer ]
Even less plans for System Verilog than for SystemC.
- [ An Anon Engineer ]
We are not using System Verilog currently.
- Chandresh Patel of Ciena Corp.
No. Bad C-Level and SystemC experiences have been more than enough.
- Michiel Vandenbroek of China Core Technology Ltd.
I will definetly want to use System Verilog in the next 6-9 months, but
for now the focus is Java based hardware verification. One of our
company's goal is to integrate some of the System Verilog with
our own Java based tools
- Mohammad Bhaiji of Ontic Technologies, Inc.
We're starting to use System Verilog assertions in VCS, purely for
verification purposes. This is enabled by the new sv_pragma statement
in VCS 7.1.1, which allows VCS to use System Verilog assertions while
other tools see them as comments.
For System Verilog we're targeting the Synopsys tools (DC, VCS,
Formality) and Novas (Debussy). Expect Formality to come in dead last,
with production support for System Verilog design constructs no sooner
than December and possibly as late as March, 2005. Take Synopsys claims
of "Q2 2004" Formality support with a big grain of salt. They mean beta
in June, and it'll be at least 6-9 months longer to production status.
But for any normal design cycle it should be safe to start using System
Verilog design constructs in September/October, which is just within
your 6 month window. That's our own target. Support for System Verilog
testbench-related constructs won't surface until 2005.
- [ An Anon Engineer ]
No plans to use, although there is some interest.
- Nathan Dohm of StarGen, Inc.
No, but expect to start using it for testbench work in the next project.
Our testbenches are currently 5% Verilog, 5% PLI and 95% Tcl. We expect
to be able to switch over to System Verilog on projects that start in
2005. Thinking verification mostly. Synopsys VCS
- Mark Andrews of EFI, Inc.
Possble, but would need to make sure language constructs are the same
between Cadence and Synopsys.
- [ An Anon Engineer ]
No.
- Hsing Hsieh of Hitachi
No.
- [ An Anon Engineer ]
No.
- Jerry Roletter of ATI
Yes, System Verilog would be used in the future project. The assertion
of the System Verilog would be used. We may port the testbench and test
program to the System Verilog. If the functional coverage is available,
we may use that, too. We use VCS as main verification engine.
- Edmond Tam of Global Locate, Inc.
Yes. I'm looking at the possibility of including System Verilog
verification functions with our delivered coreware. Currently, I'm
playing with a small project using VCS NTB to learn OpenVera to see
if System Verilog will work for us when it has the verification
function (3.1a?)
- George Gorman of LSI Logic
Yes, verification extensions, Modelsim and VCS
- Greg Schmidt of General Dynamics
Yes. We'll use System Verilog for RTL and testbench. Again, it will
probably be a Vera to System Verilog migration as System Verilog
support becomes available.
- Sandro Pintz of Precision IO, Inc.
No System Verilog. Perhaps in the 1-2 year timeframe.
- [ An Anon Engineer ]
Not using System Verilog.
- Jithendra Madala of QuickSilver Technology
Using System Verilog on a current project. Using Synopsys VCS. Today
we are using the extensions. In the future we will be using assertions.
- Don Monroe of Enterasys Networks
We are strongly leaning toward adopting System Verilog upon
implementation by the EDA vendors. However, excessive license fees
could derail that adoption.
- Jim Lear of Legerity
We would probably use the designer version, as most of our verification
is done in SystemC.
- Bill Dittenhofer of Starkey
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