( DVcon 04 Item 3 ) ---------------------------------------------- [ 05/26/04 ]
Subject: SystemC
THE VERIFICATION DIFFERENCE In my prior surveys over the years, chip
designers have been quite vocal about how they hate SystemC and that they're
in no way, shape, or form going to use SystemC to design. This year in a
purely verification survey (i.e. NOT design, but verification), it appears
that 1 out of 3 verification engineers are going to use this SystemC
beastie in some form on their project.
"Do you see your project using SystemC in the next 6 months?"
not in the
next 6 months : ################################## 68%
yes we will : ################# 32%
And asking only those who are or will be using SystemC:
"Are you using SystemC for high level modeling,
or verification, or for design?"
high level modeling : ######################## 72%
verification : ##################### 64%
design : ## 5%
Overall SystemC smartened up and stopped trying to be an extremely painful
chip design language that just evoked Pavlonian fear responses from the
experienced design engineers. Instead, the verification folk use SystemC
in a niche where it peacefully and non-threateningly thrives as a speedy
architecture and high level modeling simulator. And 1 in 3 is impressive...
I use NC-SystemC to make a tool to analyze STBUS. It's been a valuable
tool to analyze the STBUS Bus. I used NC-SystemC with SimVision for
analyzing the transactions. I feel it will be good if Cadence can come
up with something that is a level higher than transactions, such as a
message so that we can analyze a group of transactions. I also feel that
more demos should be given by Cadence telling about new features of
products and briefly mentioning the old ones.
I was not at all happy with the use of the debugger with NC-SystemC and
wasn't able to use it for my design. Even with help of local Cadence
engineers it took a lot of time to resolve the problem. I finally found
a small work around to do things which was very crude and takes lot of
time to debug.
Code Coverage is not available for C++ code. As I use mostly NC-SystemC,
I want a coverage tool for C++ (NC_SC, SystemC). It is usually needed
for the end of design when the time is less, so I guess most designers
skip this part due to tight deadlines.
- Sudhanshu Chadha of STmicroelectronics
Yes, for high level modeling and verification. CoCentric and OSCI.
- Frank Lier of PACT XPP Technologies
We do not intend using SystemC.
- Samuel Russell of Ceva, Inc.
Absolutely Not! I'm a hardware designer, not a software weenie.
C is for 'C'issies.
- Ray Andraka of Andraka Consulting
We will go down the SystemC route with out current project and will be
using it principally for verification - including HW/SW co-verification.
We are likely to use the Cadence SystemC tools.
- Fraser Dallas of Motorola GSG (Scotland)
No, my current project is Verilog.
- Greg Arena of Intel Corp.
Anyone using SystemC should be immediately fired and their degree(s)
revoked by their school. I've had a SystemC/VHDL design in my hands
for a year now. A complete disaster.
- [ An Anon Engineer ]
We do already use SystemC in production for more than 10 designs. We use
SystemC to build virtual prototypes shipped to software (drivers) teams.
The same modeling environment is reused to build RTL testbenches for
functional verification and the high-level (TLM) model of the DUT is used
as the reference model. We've been in production for 1 year now.
For a few months now, we also have 4 SystemC platforms in production for
architecture analysis. These platforms most often integrate some RTL
models. Hence need cosimulation capabilities.
Virtual prototypes use the OSCI SystemC simulator. Functional verif.
environment relies on Cadence NC-SystemC (NC-Sim).
- Frank Ghenassia of STMicroelectronics
No application of SystemC. Not great for our designs.
- Andreas Dieckmann of Siemens AG
We are actively using SystemC now, and have been for over 1 year for
system level modeling (performance and architecture).
- Scott Runner of Qualcomm
No -- and though I'd like to get our systems guys to use SystemC to
make the transfer from algorithm to implementation a bit less painful,
I doubt we'll go there.
- John Ford of SolarFlare Communications
No. We used SystemC for verification in a previous SoC and now we switch
to Vera. SystemC makes little sense for verification. We are still
using it for system description but still I think it make sense only for
algorithmic validation. For system we are Cocentric or CoWare for their
conformance telecom system tests. But this not really SystemC is it?
- Remi Francard of STmicroelectronics
We use SystemC to connect between C models & Verilog (for verification),
nothing else. We link NC-Verilog to our C model via SystemC: this seems
to be easier and higher performance for our needs than using PLI/VPI.
- Pete Cumming of Icera Semiconductor
No. We aren't using SystemC, and I don't think that we will use it in
the next year.
- Dorit Moshe of IBM Israel
I experimented with converting our present design to SystemC. We used
Modelsim's SystemC tools, since the present chip's testbench was built
assuming Modelsim. The constraints of our existing system (proprietary
PLI-based C testbenches) made the conversion prospect too difficult to
contemplate for this chip. If we were starting from scratch, we'd
probably have done SystemC.
- Christine Gerveshi of Agere Systems
Apparently we are using SystemC now, for high-level behavioral modeling.
We're in the architecture and definition phase of a large subsystem,
and 2 or 3 units are either seriously considering or already using
SystemC. I believe we have Synopsys Cocentric Studio.
- Aviva Starkman of Northrop Grumman
We tried some SystemC modeling already, but found the verbosity and poor
support for bit manipulation of ports to be too much trouble for the
benefit. Compile times of SystemC were terrible, too. We quickly
converted the SystemC model we had to RTL. It wasn't modeling any
complex algorithmic function, so we didn't see any speed penalty. In
fact, since the RTL compiles faster than the SystemC did, we probably
saw in increase in debug productivity. We were using Cadence NC-SystemC.
- Ty Gallander of Conexant
We're just starting to use it for system and behavioral modeling. No
real experience yet. We will integrate SystemC models into the Specman
environment for output prediction versus writing models in "e" on our
next project. I have a lot of CPUs that can run C. Specman licenses
are limited.
In previous experience, we used C/C++ and integrated it with Vera and
were very pleased with the success of that endeavor.
- [ An Anon Engineer ]
Heavy usage of SystemC for verification. Cadence Incisive.
- Mark Dorland of Banderacom
We designed our initial architecture in SystemC to assess size and power
tradeoffs, then started RTL development. As our RTL progressed, we
would run both SystemC and RTL simulations in parallel and compare
interesting points to determine if the RTL/SystemC were behaving
correctly. Being a processor, we were able to test at the instruction
level.
We also used the SystemC verification library (SCV) to randomly generate
many instructions. It's easy to do this. The key is to use the
constraint facilities provided in SCV to keep those instructions
meaningful and reduce the debug time of bad tests.
One area that I would like to see improved is visibility into the SystemC
model by the simulator companies. Ideally it should be as easy to probe
SystemC signals as it is in RTL and all SystemC constructs should be
supported.
Overall, it was much more efficient to use SystemC as part of the design
and verification process than designing in RTL and writing self checking
testbenches. Testing and debug was much faster with a "golden" model to
compare against, so we were able to create many more test cases and
identify more bugs in a shorter time.
- Greg Tumbush of Starkey Labs
We use Perl (from a company called GreenLight) as our HVL. We are
investigating SystemC/Vera/System Verilog for the next generation
of products.
- [ An Anon Engineer ]
Yes, we'll be using SystemC for all 3: high level modeling, verification,
and design. We'll be using Cadence/CoWare.
- Umberto Rossi of STMicroelectronics
We use SystemC for all these items and intensively. OSCI, Cadence
NC-Sim, CoWare ConvergenSC
- Benoit Clement of STMicroelectronics
Yes. Primarily for verification, but will also use for high-level
modeling. Both Synopsys and Cadence tools. If a customer uses MTI,
then will use that tool as well.
- Ambar Sarkar of Paradigm Works
We've been using SystemC for the last 3 years. We used it originally
for high level modeling and continue to use it for detailed performance
modeling. We're using the open source SystemC simulator.
- [ An Anon Engineer ]
No SystemC usage.
- Tomoo Taguchi of Hewlett-Packard
Yes, we are in a process of moving from C/FLI to SystemC. We plan to
use SystemC for verification of HDL as well as early development of
software/firmware/drivers. Since we are MTI users, we'll simply use it.
- Alex Chao of Topspin Communications
No. We were using SystemC experimentally, but with ModelTech 5.8 we
need to pay extra for it, so we stopped playing with it.
- [ Kenny from Southpark ]
Yes. High level modeling and verification. Modelsim SystemC.
Modelsim has an integrated kernel for SystemC. I've used other
simulators for SystemC, Modelsim treats SystemC just like VHDL or
Verilog. No restrictions on the code.
- Shreyas Shah of Aasan Networks
We have already used SystemC for high level modeling, and will use
again in the next 6 months. We are using the reference simulator and
NC-SystemC (coupled with a Verilog TB)
- [ An Anon Engineer ]
I may use SystemC in the near future for high level modeling if I can
convince mgmt to foot the bill for the Modelsim license. But the
odds are less than 50%.
- [ An Anon Engineer ]
No. We probably will in 1 year.
- Carl Harvey of Cirrus Logic
No SystemC in next 6 months. Still the old way of Verilog + PLI.
- Ajit Madhekar of ControlNet India Pvt Ltd.
No. Maybe within the next year will be using SystemC.
- Reza Shirali of Orbital Sciences Corp.
No.
- Javier Jimenez of DS2 Spain
Not yet. We are evaluating.
- Sachin Mohan of Cypress Semiconductor
No SystemC in actual use but planned for simulation. We use Axys tools
for high level modeling this means models are written in Lisa/C/C++.
- Thomas Langschwert of Infineon
Yes. SystemC for HL modeling, verification.
- Ross Smith of Theseus Research
We use C++ with a propriatory SystemC-like library for a while and have
started to develop all new code in SystemC. We use Cadence NC-SystemC
as simulator.
- Karl Kaiser of EcoLogic GmbH
Yes. We use SystemC for system level modeling. We use Summit Design's
Visual Elite though I don't use the graphical entry part.
- Terry Doherty of Emulex Corporation
I am not using SystemC and have never used it. I am a C programmer so I
know what it's all about. But the simple fact is that I do not have a
need nor see a need for SystemC (nor Handel-C) in the next six months.
When I do get ready to use C as an HDL, I know of a company in Mexico
that is going to blow away the competition.
- Simon Ramirez of Synchronous Design, Inc.
No usage, went to the class, you need to be a good C++ developer (not
fair, but good -- really into templates and stuff.) Ny neighbour works
as a developer in Microsoft, and developes in C++ and did not know a
lot of the aspects covered in SystemC classes. Cadence Incisive looks
the best, but also lacks capabilities.
- [ An Anon Engineer ]
We are using SystemC now. This past year we replaced our PLIs with
SystemC. We use it to drive and control our simulations. We have
a SystemC stub that mimics our processors bus. We are using the
NC-Sim but are also making sure our SystemC will run under VCS-MX.
- Maynard Hammond of Scientific Atlanta
We do not use SystemC at all at present. There is some level of interest
in moving over to a design flow that uses SystemC, but I can't see it
happening in the next 6 months due to the amount of work that would be
involved in changing mid-project. Hopefully asking the same question in
6 months time will lead to a different answer.
- [ An Anon Engineer ]
We don't currently use SystemC and don't plan to within the
next 6 months.
- Michael Condon of the Naval Research Lab
We are already using SystemC in a design. We use it for high level
modeling and processor modeling and for pre-RTL FW development. We
also use the models as part of the verification environment. We use
the free SystemC simulator but we plan to take a look at the Modelsim
SystemC interface.
- [ An Anon Engineer ]
We don't expect to be using SystemC in the next 6 months, except possible
to develop test-benches, replacing are current C test-benches. We are
experimenting with the Modelsim SystemC integration.
- [ An Anon Engineer ]
We are not seriously consider using SystemC. Aldec's Active-HDL will
be our first choice tool if when we start to use SystemC.
- Peter Tan of Transcore
No plans.
- [ An Anon Engineer ]
We are planning to serious use SystemC for modeling our 802.11 MAC. We
will probably use Synopsys version of SystemC.
- Subbu Muddappa of Woodside Networks
We are using SystemC for micro-architectural (eg. behavioral) modeling
as well as performance modeling for customers. We haven't bought any
commercial SystemC tools yet as we feel they are too immature. We rely
solely on gdb.
- [ An Anon Engineer ]
Yes, for modeling and verification. Based on Cadence libraries.
- [ An Anon Engineer ]
No SystemC.
- Boaz Ben-Nun of Starcore DSP
No.
- Mike Murphy of Syracuse Research Corp.
We are starting to use SystemC for system level modeling and we are
currently evaluating tools for that.
- Laurent Claudel of Wavecom
No.
- Lutz Naethke of Atmel
Some SystemC reference models only. No verification or design with
SystemC. System Studio for capture. NC-Sim to encapsulate reference
models for simulation.
- [ An Anon Engineer ]
We have a project now on multimedia which uses SystemC for design. The
starting point for this project was a few thousand lines of reference
code in C, so SystemC was an obvious choice.
Actual design flow: Synopsys dc_shell / compile_SystemC (SystemC-to-VHDL)
+ Altera QuartusII (synthesis + P&R). The VHDL from Design Compiler
sometimes requires some manual editing. This has improved a lot however
when we switched to a newer release (U-2003.06).
- Wim Meeus of Universiteit Gent, Belgium
No
- Inder Singh of iVivity, Inc.
No current plans for SystemC.
- Mark Curry of Texas Instruments
No, so far I have not seen any benefit to using SystemC.
- Brian Kahlig of DRS Signal Technologies
Not using SystemC, not planning to.
- Rainer Mueller of Oasis Silicon Systems
No plans to use.
- Nathan Dohm of StarGen, Inc.
Not using it.
- [ An Anon Engineer ]
We started experimenting with Cadence TestBuilder-SC about a year ago,
then we switched to using SCV and SystemC for verification. We are also
considering use of SystemC for high level modeling, but have not started
doing that yet.
- [ An Anon Engineer ]
No. Tried both with C-Level and SystemC, didn't like it. Results were
crap for C-Level-to-Verilog to gates synthesis, at the cost of lower
productivity. SystemC verification provided no clear advantage over
other methods, e.g. Verilog/Perl/C mix and match.
- Michiel Vandenbroek of China Core Technology Ltd.
We decided to use SystemC in our next project; we want to use it for high
level modeling and verfication. We use VC and CoWare's ConvergenSC.
- Gao Peng of Tongji University, China
No use expected.
- [ An Anon Engineer ]
In another project, we use SystemC for verification. Synopsys SystemC.
- Stone Shi of STmicroelectronics
We are using SystemC for reference modeling for our ASIC verification
and also for the testbench for all checkers and monitors along with the
ASIC wrapper that co-sims to the RTL in Verilog. We are using the
public release of the SystemC with in-house co-sim PLI interface
between the two simulators.
- Chandresh Patel of Ciena Corp.
Yes, for architecture performance, we are using SystemC.
- Fred Liao of S3 Graphics
We're using Verilog for RTL, regular C for testing. We have some really
cool stuff we're doing with C, but I can't say more than that. It's
free, and it's saving us man-months that the EDA vendor's tools
couldn't do.
- [ An Anon Engineer ]
I am not going in the direction of SystemC, simple reason, our company
develops Java based hardware tools.
- Mohammad Bhaiji of Ontic Technologies, Inc.
We may be using SystemC within the next 6 months for verification;
specifically the Cmodel to generate golden results and compare it
against Verilog.
- [ An Anon Engineer ]
No
- Mark Andrews of EFI, Inc.
Not using SystemC.
- Don Monroe of Enterasys Networks
No. I like SystemC and would consider adopting it, but right now I think
our best bet is to go with System Verilog, even though there is not
enough tool support yet, we can start with a Vera based verification
strategy and then migrate (and port the environment) onto System Verilog.
- Sandro Pintz of Precision IO, Inc.
No SystemC, period.
- Edmond Tam of Global Locate, Inc.
No.
- Jerry Roletter of ATI
No, we are not doing high level SystemC modeling or verification for our
design. SystemC is definitely worth considering for high level modeling.
- Hsing Hsieh of Hitachi
No!
- James Lee of the ASIC Group
We will not use SystemC.
A lot of companies are using SystemC right now. It's fast and it's
cheap, according to some of the presenters I talked with. Also,
Modelsim 5.8 now has support for SystemC. Previously, a lot of these
companies encountered big headaches in creating the FLI/PLI interface
to SystemC code. That's automatically handled by 5.8c now.
However, most of the companies using SystemC have extensive software
they must co-develop on their systems. So, wireless phone companies
that have hundreds of thousands of lines of software for their handsets
would be typical adopters. I don't recommend SystemC for us
at this time.
- Jim Lear of Legerity
No, No
- George Gorman of LSI Logic
No.
- [ An Anon Engineer ]
We presented a SystemC paper as such at DVcon. Our partner uses SystemC
as well. We used the SystemC library, as well as SCV for random
verification support.
- Bill Dittenhofer of Starkey
No plans.
- [ An Anon Engineer ]
We are using SystemC for verification (SCV) purpose. All of our tests
(assembly/C programs) are generated through SCV. Also for testbench we
have transactors in SystemC. Currently we have few licenses of Cadence
Incisive but most of our verification we just use SCV and all
transactors communicate to Verilog thorugh PLI (Cadence tbscScHdlSdi
which is also free).
- Jithendra Madala of QuickSilver Technology
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