If I were a CAD manager having serious troubles using tools from Cadence or
Mentor Graphics, I'd currently be very cautious of salespeople from these
companies visiting my VP of Engineering or CEO. Having just confirmed the
EE Times article's contents with its author, Cadence & Mentor appear to be
quite serious about taking over customer's internal CAD departments and the
design engineering functions they can land. I expect these sales pitches
will be made to CEO's & VP types (who are motivated by tax and accounting
reasons to minimize permanent employee headcount) in hopes of convincing
them that internal CAD support & design engineering are just two more
generic functions that can be farmed out like payroll accounting -- instead
of being the crucial life's blood of a high tech firm.
It's bad enough to be trying to figure out why an EDA tool isn't working as
expected -- you shouldn't also have to be watching your back to see if that
same tool's vendor isn't trying to get you fired.
- John Cooley
the ESNUG guy
( ESNUG 211 Item 1 ) ---------------------------------------------- [3/2/95]
Subject: (ESNUG 192 #1 206 #5) "Anyone Using Synopsys's Static Timing Analyzer?"
> The problem was that Synopsys was not doing a very good job of handling the
> elimination of multi-cycle paths.... The main problem was that you didn't
> know that Design Compiler didn't understand your multi-cycle command.
From: sgolson@trilobyte.com (Steve Golson)
I've encountered this problem also. After much experimentation what I found
is, if you want to specify the path from one flop to another as multi-cycle,
the start point should be the CLOCK PIN of the first flop and the end point
should be the DATA INPUT PIN of the second flop, thus
set_multicycle_path 2 -setup -from find(pin,lbarb1/Q_reg[0]/CK) \
-to find(pin,datapath1/mpar*lt/ff1/D)
set_multicycle_path 1 -hold -from find(pin,lbarb1/Q_reg[0]/CK) \
-to find(pin,datapath1/mpar*lt/ff1/D)
Yes, that's right, you need to specify the path twice if you want to get
rid of bogus hold problems.
You can tell when you do it right, because report_timing shows twice the
clock period when it reports the path.
Do not trust report_timing_requirements -- it will show a path as multicycle,
but it may not actually be a legal timing path.
> The other problem was that the more mulit-cycle paths specified, the more
> likely to run very slow or even crash and burn, Synopsys-FATAL style.
This was supposedly fixed (in 3.0c, maybe?).
- Steve Golson
Trilobyte Systems
( ESNUG 211 Item 2 ) ---------------------------------------------- [3/2/95]
From: rray@poci.amis.com (Russell L. Ray)
Subject: (ESNUG 206 #4 208 #3 209 #4) Set_Driving_Cell Is A Useless Command
John,
I have to tell you this because I think you will get a kick out of it. I
just received a call from a Synopsys AE with a problem that they thought was
due to our library. I had just read my ESNUG post yesterday and the problem
they described to me was exactly what ESNUG 209 Item 4 ("Set_Driving_Cell Is
A Useless Command") talked about. I quickly pointed this out. They thanked
me and said they would read ESNUG.
Thanks for the good work!
- Russell L. Ray
American Microsystems, Inc.
( ESNUG 211 Item 3 ) ---------------------------------------------- [3/2/95]
From: dreed@vnet.ibm.com (Dan Reed)
Subject: VSS (VHDL) Compiled Engine Problems on IBM RS6000's
Hi John,
Ever since Synopsys came out with the compiled VSS engine, we have been
struggling to get the darn thing to work. We have no problem with the older
interpreted engine (-fi_all is our workaround). We have a STAR open with
Synopsys, but the testcases I send them work fine at Synopsys, so they have
been unable to duplicate the problem.
Are there other VSS users out there that have compiled engine problems on an
RS6000? By problem I mean "vhdldbx" or "vhdlsim" takes an especially long
time during elaboration, then it crashes with a message like this:
dump: ...../WORK/rs6000/libCsa023840.so.1.0:
dump: 0654-106 Cannot open the specified file.
**Internal Error: vhdlsim: Please report (Can not link shared object file).
Smaller pieces of our design will work OK compiled, but larger ones do not.
I have tried lots of things (NFS vs. /afs, the STAR 20116 workarounds) and I
have sent my FAE my vhdl.uof and environment data, but they see nothing
unusual. I'd really like to get our Synopsys simulations going as fast as
our (now Mentor) Model Tech ones do, but no luck so far. Other than
switching more licenses to Mentor/Model Tech, any ideas?
- Dan Reed
IBM Microelectronics
( ESNUG 211 Item 4 ) ---------------------------------------------- [3/2/95]
From: lfchao@cpre1.ee.iastate.edu (Liang-Fang Chao)
Subject: Two Newbie Design Compiler and Design analyzer Questions
John, we're new to HDL's and synthesis. Using Synopsys's Design Compiler
and Analyzer I have the following questions:
1. In Design Analyzer, how do you find a realistic minimum cycle period for
a sequential circuit? (The critical path reported by the tool seems much
too short. I did specify the clock, but the critical path reported is
6.26 nsec when there was a combinational path of over 19 layers.)
2. What is *GEN*167 box in the initial schematic, when I used a "case"
statement. Where can I find descriptions of these generic cells used
by Synopsys tool?
- Liang-Fang Chao
Iowa State University
( ESNUG 211 Item 5 ) ---------------------------------------------- [3/2/95]
From: danj@mpd.tandem.com (Dan Joyce)
Subject: Use set_max_fanout With Much Caution!
John,
USE CAUTION WITH SET_MAX_FANOUT ON THE ENTIRE DESIGN! Our methodology used
to have as part of the process a "set_max_fanout = 10" on the entire design.
This caused timing problems on our modules which drove the outputs of the
ASIC. (For those modules, we had very large loads applied on the outputs to
get large drivers - since the outputs of these modules were going to drive
across the die and needed to be as fast as possible.)
We were trying to drive 4 outputs with the same logical value.
Synopsys Design Compiler correctly used the largest buffers available
(BUFF3 - which had a fanin of 3 inputs attributed to their inputs). The
set_max_fanout caused Synopsys to only drive 3 BUFF3's with a single BUFF3,
and the worst path for these outputs was a string of three BUFF3's in a row.
Since these buffers were actualy able to drive about 100 loads, a single
BUFF3 could have driven 15 or 20 second level BUFF3's to give a tree with a
worst case delay of only 2 BUFF3's. This would have worked with 15 - 20
outputs.
Synopsys Design Compiler gave this:
__|\_____
| |/
|
___|\____|\__|__|\_____ delay of 3 - BUFF3's
|/ | |/ |/
|
|_|\___________
| |/
|
|_|\___________
|/
Where this would have been more than sufficient:
_|\________
| |/
|
___|\__|_|\________ delay of 2 - BUFF3's
|/ | |/
|
|_|\________
| |/
|
|_|\________
|/
We later found that set_max_transition, used correctly was the command that
made more sence for this logic. set_max_transition made sure that all of
the nets were sufficiently driven according to the load and the drive
strength of the output.
- Dan Joyce
Tandem Computers Inc.
( ESNUG 211 Item 6 ) ---------------------------------------------- [3/2/95]
From: menne@pasta.enet.dec.com (Mike Minne)
Subject: Dissimular Libs Affecting ASIC to FPGA Technology Translation?
John,
I have a design that was originally entered schematically with Viewlogic and
was translated by Synopsys from a Toshiba 1.0 micron library to VTI653 ASIC
technology.
I want to hardware emulate it in large Altera or Xilinx FPGA's. How can I do
a Synopsys technology translation between such dissimilar libraries ? (The
goal is to get hardware emulation working, then begin coding the hierarchical
blocks into Verilog HDL, and synthesize and emulate until we have a completely
architecture independent Verilog design.)
- Mike Menne
Digital Equipment Corp.
( ESNUG 211 Item 7 ) ---------------------------------------------- [3/2/95]
From: kaylak@pogo.wv.tek.com (Kayla Klingman)
Subject: Looking For Gotchas In Using Synopsys With Cores
Hi John !
When are you going to marry this girl friend you always talk about in your
ESNUG postings and think about little Cooleys instead of sheep ?
My new ASIC project is contemplating using an outside vendor with Application
Specific cores (like UARTs and SCSI) with Synopsys/Verilog as the design
vehicle. Do you know of any caveats with this design combination ? Are
there any specific questions I should be asking the vendor when using this
approach?
- Kayla Klingman
Tektronix
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