Last week I had this conversation with Aart (the Synopsys CEO; not my goat):
Aart: "Hi, John. I'm phoning to personally invite you out to California
for training on a completely new product we're announcing on Tuesday,
Feb. 7th. This is one of our bigger annoucements for the year. In
fact, we're inviting the trade press, the industry and financial
analysts, the beta customers and the ESNUG community for a hands-on
look at this new category of EDA tool. It's that big."
me: "Wow. That's pretty ballsy to let users give unedited comments to
the financial analysts & press. Don't you read Dilbert? -- unlike
marketing managers, engineers will give frank opinions that you may
or may not like! Mind if I ask what this product is?"
Aart: "Let's just say you've got to *see* it in action."
- John Cooley
the ESNUG guy
( ESNUG 208 Item 1 ) ---------------------------------------------- [1/95]
Subject: (ESNUG 206 #1 207 #2) Same Code & Scripts, Results Vary 3.0b&c, 3.1a&b
>We used design compiler v3.0b... we received version 3.1a. With the
>same scripts and the same VHDL code ... I was not too thrilled when the
>results gave me a larger design (area) and a MUCH slower design (slack)...
From: rm@hoy.nsc.com (Robert Marshall)
John, I suffered similar experiences when changing from version 2.2 to 3.0.
It was necessary to recompile the Synopsys ASIC libraries used as well as the
design, in order to get to optimum results with the new release. Perhaps
the same is true for 3.0b to 3.1a transition?
- Robert Marshall
National Semiconductor
( ESNUG 208 Item 2 ) ---------------------------------------------- [1/95]
Subject: (ESNUG 205 #5 206 #2 207 #4) Synopsys->Mentor w/ "db2eddm" Sucks
>When we asked both Mentor & Synopsys about going from EDIF to EDDM, the
>answer was a definite "NO". We have encountered some problems with the
>db2eddm path (nets crossing bus rippers that were shorted in Mentor and not
>in Synopsys, etc.) Do you have any suggestions from any of your readers?
From: duclos@ws077.bytex.network.com (Michael Duclos)
John,
Someone here at Bytex went through this path a year ago, and encountered the
same problems. Here's their notes on to getting from the Synopsys Integrator
for Mentor's Falcon Framework:
A- Start Synopsys' Design Analyzer. Set libraries including symbol library.
Toshiba provides a Mentor symbol library for Synopsys, in our case
tc140g.mentor.sdb. Setting the symbol library to mentor before reading
the Synopsys database causes the symbols to automatically convert to the
new ones once the database is read. note: (I found that we could set
the Synopsys database to any of the symbol libraries available for the
technology. We could have used tc140g.valid.sdb, or one extracted from
the Mentor symbol library.)
Example of Synopsys script to set libraries:
/* load Toshiba TC140 libraries */
link_library = /toshiba/synopsys/v3.0a/lib/tc140g/tc140g.db;
target_library = /toshiba/synopsys/v3.0a/lib/tc140g/tc140g.db;
symbol_library = /toshiba/synopsys/v3.0a/lib/tc140g/tc140g.mentor.sdb;
B- Read design database. In our case, IMA_CHIP_synop.db.
C- Set schematic variable gen_cell_pin_name_separator equal to "_"
(gen_cell_pin_name_separator = "_"). This eliminates the "/" character
from some of the busses when executing the create_schematic command.
This character is placed in busses from equal blocks. The name of the
busses become the instance name of the block and the bus name separated
by the "/" character.
D- Execute create_schematic command. (This part is not documented in the
maunual for db2eddm.) Select the top level block and use the following
command: create_schematic -hierarchy . The Synopsys transcript window
should tell you the blocks created.
E- Save new db file. After several tries, I found that if the design is
saved into a db file with the same name as the top level block the
db2eddm program does not work. So when I save the design to IMA_CHIP.db
db2eddm did not work. But when I save the design to dummy.db then
db2eddm worked. The save command was: write -f db -hierarchy dummy.db
F- Run db2eddm to extract the database. Make sure that the transcript of
the command displays the blocks and schematics created. The command
used was: (one line) "db2eddm -db dummy.db -map tosh.map -add_comp
-add_inst -add_model -target_dir DESIGN2"
G- It is important that the map file specify a parameter for the technology.
The -PARAMETER option of the map file is explained in appendix G of the
IFFF documentation. The top of the map file I got from the tutorial.map
that comes with the IFFF installation. To create the list of symbols
after setting the -SYMBOL keyword I did the following steps:
a- I used ls | grep -v mgc > list on the mentor symbol directories to
create a list of the symbols.
b- awk '{print "$TOSHIBA_LIB/part_lib/",$1," ",$1}' list > temp1
was used to create a list with the path to the symbols.
c- awk '{print $1}' list > temp2 to create a column of Synopsys names.
d- with vi I changed the case of the symbol names in temp2. These are
the symbol names in Synopsys. (I could not guarantee that the
Synopsys symbol names were case insensitive.)
e- paste temp1 temp2 > temp3 merges the four columns. The paste
command was very helpful in pasting columns.
f- With textedit I merge column 1 and 2 to create a path to each symbol
as you can see below.
g- awk '{print $1," ",$2," ",$3}' temp3 > tosh.map (This awk
command gives me spaces between the columns.)
The following is part of the map file used:
# Map File for Synopsys Integrator IMA_CHIP
#
# Special Symbols
-POWER
# ComponentName MentorSymName SynopsysSymName
$SYNOPSYS_IFF_ROOT/symbols/vcc vcc vcc
-GROUND
# ComponentName MentorSymName SynopsysSymName
$SYNOPSYS_IFF_ROOT/symbols/ground ground ground
-PORT_IN
# ComponentName MentorSymName SynopsysSymName
$SYNOPSYS_IFF_ROOT/symbols/portin portin portin
-PORT_OUT
# ComponentName MentorSymName SynopsysSymName
$SYNOPSYS_IFF_ROOT/symbols/portout portout portout
-PORT_BI
# ComponentName MentorSymName SynopsysSymName
$SYNOPSYS_IFF_ROOT/symbols/portbi portbi portbi
-OSC_BI
# ComponentName MentorSymName SynopsysSymName
$SYNOPSYS_IFF_ROOT/symbols/offpag.bi offpag.bi offpag.bi
# Technology Parameter -- Here you specify what the technology parameter in
# the Toshiba symbol is going to be set at. Without this you will get errors
# running db2eddm
-PARAMETER
# mentor parameter name mentor parameter value
technology tc160g
# The component name is the path to the symbol in you system
-SYMBOL
# ComponentName MentorSymName SynopsysSymName
$TOSHIBA_LIB/part_lib/b1 b1 B1
$TOSHIBA_LIB/part_lib/b12 b12 B12
$TOSHIBA_LIB/part_lib/b12rp b12rp B12RP
$TOSHIBA_LIB/part_lib/b16 b16 B16
$TOSHIBA_LIB/part_lib/b16h b16h B16H
$TOSHIBA_LIB/part_lib/b16if b16if B16IF
# END of Map File
The user has to make sure that the TOSHIBA_LIB and SYNOPSYS_IFF_ROOT
environment variables are set correctly on the Mentor location map for the
process to work.
- Michael Duclos
Bytex Corporation
( ESNUG 208 Item 3 ) ---------------------------------------------- [1/95]
Subject: (ESNUG 206 #4) Set_Driving_Cell IS A Useless Command
>What you would expect is set_driving_cell compile the block assuming that
>the input port is being driven by the specified cell and that ALL of the
>rules pertaining to that cell would be considered during optimization. (It
>turns out that this is not at all the case.) The only thing that the cell
>is used for is to check timing. What this means is that the max_fanout and
>max_capacitance attributes on the specified cell are ignored during
>optimization!
From: jlohman@boris.convex.com (Jeff Lohman)
We ran into this in August. (I tried to convince them it's a STAR, but who
knows with Synopsys, Inc. sometimes.) The problem is set_driving_cell sets
the transition attribute on the pin but also deletes the attribute(s) which
cause fanout and capacitance violations to be fixed. The set_drive command
sets this/these attribute(s) but deletes the transition attribute. If you're
using the table lookup timing model with input transition and load capacitance
as parameters, you really need the transition attribute -- because of the
default transition if there's no attribute is 0 delay, a perfect edge, which
in our case results in 0 gate delay. We also found this counterintuitive and
expected set_driving_cell to operate as the user describes, i.e.
set_driving_cell replaces and supercedes set_drive.
- Jeff Lohman
Convex Computer Corp.
( ESNUG 208 Item 4 ) ---------------------------------------------- [1/95]
Subject: (ESNUG 207 #5) LMC's Hotline In Slump Since Being Bought By Synopsys
>Is it me or has LMC's hotline went down hill since Synopsys took over?
>Lately more and more users complain about it and I used to remember they
>where one of the best a few years ago. I notice more delays when I do
>use it (which is less frequent than a few years ago).
From: jcooley@world.std.com (John Cooley)
After some checking around I can confirm that, yes, the LMC hotline did have
a slump because they lost four out of their normal contingent of nine AE's
this summer. (Two people transfered to other departments and another two
went on maternity leave.) Everyone I spoke with said that the work load was
crazy during the summer because of they were short staffed. Anyway, this
was transitory because the two AE's who had kids returned *plus* they've
hired three new AE's *plus* they're planning to add an additional two more
AE's by June -- making a grand total twelve AE's on the LMC hotline. If
anything, it appears that the Synopsys purchase of LMC has encouraged hiring
more hotline AE's at LMC; but that's only a bit of conjecture on my part.
- John Cooley
the ESNUG guy
( ESNUG 208 Item 5 ) ---------------------------------------------- [1/95]
From: jackm@synopsys.com (Jack Marshall)
Subject: Seeking Confessions From The Speed Freaks
John,
I'd like to see on ESNUG the techniques people use to get high speed designs
from synthesis. Assume you are starting out with good coding style, good
partitioning for synthesis, and a good synthesis library. Assume the default
compile ("compile") doesn't meet your timing goals. What do you do next?
Map effort high? How do you overcome local minimums? What if that doesn't
work? What do you try next? I would like to see ESNUG answers posted as:
First, I try this ....
Second, If that doesn't work I try ...
Third, If that doesn't work I try ...
I would also like to know "rules of thumb". For example: "If the design
isn't meeting timing by 20% of the clock period I try ... If it is only
missing by 5% - 8%, I try ..."
Also: how often do your techniques work? For example: "default compile works
30% of the time. Map effort High, with -incremental works 80% of the time
based on the 8 ASICs I have designed with Synopsys"
- Jack Marshall
Synopsys - Austin, Texas
( ESNUG 208 Networking Section ) ---------------------------------- [1/95]
Andover, MA, document imaging company, Pixel Magic, needs perm ASIC designer
Verilog, Synopsys, C, DSP exp. No headhunters. "berger@pixelmagic.com"
Dublin, Ireland, VHDL/Synopsys perm. ASIC designer with 4-7 yrs exp. w/
telecomm, DSP. Must live in Ireland. No recruiters. "bernie@s3dub.ie"
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