Subject: Crummy Gift Exchange
Every year after X-mas I hold a party at the Poor Farm to celebrate the
dregs of the holiday season. It's called "Crummy Gift Exchange." (The
theme is for everyone to bring the worst gift they received that year to
trade in for someone else's lemon.) Last year's winner for MOST TACKY
was a two way tie between the 70 page autobiography of rap star "Vanilla
Ice" and a 100 piece puzzle depicting the cast of the soap opera "Days
of Our Lives". (When I saw these gifts I silently asked myself: "What
*kind* of relatives do my unfortunate friends have !?!!")
- John Cooley
the ESNUG guy
( ESNUG 206 Item 1 ) ---------------------------------------------- [1/95]
From: dstroup@vnet.ibm.com (Dennis Strouphauer)
Subject: Same Code & Scripts, Results Drop From v3.0b->v3.1a->v3.1b (& 3.2a?)
Hi John,
We recently completed a design in which we used design compiler v3.0b. During
the end of the design cycle we received version 3.1a. After our design was
completed I made the upgrade (downgrade?) to version 3.1a. (This is where I
ran into some problems.) Starting with the same scripts and the same VHDL
code that was used to complete our design, I re-synthesized using version
3.1a. Naturally, I was not too thrilled when the results gave me a larger
design (area) and a MUCH slower design (slack). I called my FAE and told him
about the problem, and sent him all my scripts and VHDL code. After a few
weeks, I was told that I had to switch to version 3.1b. Well, I've made the
switch to version 3.1b and the results were better, but not as good as the
original design which was synthesized using version 3.0b. In the meantime,
I've been trying a lot of different things in version 3.1b, but I can never
seem to get the design as good as version 3.0b. And now they want me to
switch to version 3.2a....
Anyway, sorry about the long winded story. I'm just curious to know if other
Synopsys users have seen this problem and if they did, what did they do?
- Dennis Strouphauer
IBM Corporation
( ESNUG 206 Item 2 ) ---------------------------------------------- [1/95]
Subject: (ESNUG 205 #5) Headaches Going Synopsys To Mentor Using "db2eddm"
>We have a group within our company that is trying to go from Synopsys
>database (.db files) into Mentor by using their db2eddm product. (When
>we asked both Mentor & Synopsys about going from EDIF to EDDM, the answer
>was a definite "NO".) We have encountered some problems with the db2eddm
>path (nets crossing bus rippers that were shorted in Mentor and not in
>Synopsys, etc.) and find this problem time consuming and cumbersome. Do
>you have any suggestions from any of your ESNUG readers?
From: Sean_Atsatt@notes.seagate.com (Sean Atsatt)
John,
We have been having the same problem with db2eddm although it appears that
Synopsys has partially fixed the problem in later releases. The majority of
the problems we had, were when the translated schematic had a wire
incorrectly shorted to a bus when the wire crossed the bus at a ripper. (This
appears to have been fixed in version 3.0b.) We are still seeing busses
shorted to busses when they cross at a ripper (so far it only seems to happen
on busses that are connected to ports, but that may just be coincidence). We
found no general solution to this problem other than to go in and fix each one
by hand. Luckily there are usually only a couple of these shorts and the
Mentor tool reports them (although it might not if the bus shorts were not on
a port). I'm hoping that Synopsys will do a complete the fix to this problem.
- Sean Atsatt
Seagate
---- ---- ---- ----
From: philip@old_zelda.mti.sgi.com (Philip Schmidt)
John,
I also encountered a problem with using busses and rippers. I went from a
Synopsys db file to an EDIF schematic and found out that when the wires
crossed a ripper symbol in Synopsys v3.0b that a short resulted in the
schematic! This was supposed to have been fixed in v3.0c but I decided
to not use rippers and busses by then. Instead I flattened the design prior
to writing it out of Design Compiler and generated the schematics as a flat
design. (This does have a problem in that if you have too many signals at
the top level, you will get a symbol which is way too big for any schematic
page. I use Concept and so I just created a bussed symbol outside of
Synopsys to represent the schematic generated. The I/O signals are connected
by name and thus does not cause a problem.)
- Philip Schmidt
Silicon Graphics
---- ---- ---- ----
From: jgais@wd.estec.esa.nl (Jiri Gaisler)
John, I've transferred designs from Synopsys to Mentor using the Mentor
generic netlist editor (Neted), bundled with Autologic. The transfer is
performed in four steps:
1. A EDIF netlist is created in Synopsys (netlist view only)
2. A patch script is run on the netlist to remap cell names, which for some
reason, never seems to be the same in Mentor as in Synopsys.
3. The patched EDIF netlist is read by Neted and written out in Mentor EDDM
4. The schematic generator (Schemgen) and view point editor is run on the
EDDM to create the Mentor schematics and hierarchy.
The process is automatic once the map file for renaming of the cells is
generated. Depending on how the EDIF netlist is generated, some signals
(buses) might change name. I can post the relevant scripts if anybody is
interested. Currently, I have map files for GPS 1.5 um and HAFO 2.5 um
libraries.
- Jiri Gaisler
European Space Research and Technology Centre
[ Editor's Note: Jiri (and other ESNUG readers), if you have a script that's
handy please send it in when you write me. That way I don't have to chase
*you* later when people chase *me* to get *your* script! ;^) -John ]
( ESNUG 206 Item 3 ) ---------------------------------------------- [1/95]
From: swanson@romulus.cray.com (Gary Swanson)
Subject: If Reading Flat Verilog Chokes, Try Reading In EDIF!
John, we've discovered a problem in Synopsys when trying to read in large
flat Verilog files. In a nutshell, Design Compiler hangs, creates a extra
large core dump, then exits with a segmentation error or fills the disk up
while dieing un-gracefully.
The problem appears to only happen when reading in a flat Verilog file of
a full ASIC design. If you want to read in the flat design, you should read
in the EDIF version of the design. The Verilog files we found this problem
on work correctly with Verilog-XL or any other Verilog tool.
- Gary Swanson
Cray Research
[ Editor's Note: Thanks for the tip. Finding out what rev of Synopsys you're
using & your follow-up to this problem will make interesting ESNUG. -John]
( ESNUG 206 Item 4 ) ---------------------------------------------- [1/95]
From: uunet!fmicos!splinter!flieder (Jeff Flieder)
Subject: Set_Driving_Cell IS A Useless Command
John,
I just got an answer to a query to the support center that I thought all your
readers would be interested in. It has to do with the set_driving_cell
command in dc_shell. The problem is in the way that design_compiler uses this
command.
What you would expect the command to do is compile the block assuming that
the input port is being driven by the specified cell and that ALL of the
rules pertaining to that cell would be considered during optimization. (It
turns out that this is not at all the case.) The only thing that the cell is
used for is to check timing. What this means is that the max_fanout and
max_capacitance attributes on the specified cell are ignored during
optimization!
In my opinion, this makes the command almost useless because now the designer
has to know what the max_fanout and max_capacitance limits are and put them
on the port manually. This is tedious if the designer has access to the
source for the library, and impossible if the library is only available in
compiled form.
I have filed a STAR with Synopsys to fix the problem, but I thought that your
readers would want to know about it. This is one of those things that is not
obvious from the documentation but it can really kill you in real life.
- Jeff Flieder
Ford Microelectronics, Inc.
( ESNUG 206 Item 5 ) ---------------------------------------------- [1/95]
Subject: (ESNUG 191 #2 192 #1) "Anyone Using Synopsys's Static Timing Analyzer?"
>> And, is anyone really using Synopsys as a static timing analyzer?
>> I don't find it accurate.
>
> In internal tests we have found that with a correct SDF file, the timing
> analyzer is as good as the numbers back-annotated... I am interested in
> the limitations you found. Can you expand on this some more on ESNUG?
From: ann@sioux.apple.com (Ann Nunziata)
John, I need to clarify what I meant by accurate. By the other user's reply
I can see that he thought I meant that the actual numbers might not be
accurate. This was not our problem.
The problem was that Synopsys was not doing a very good job of handling the
elimination of multi-cycle paths. I could not get accurate results because
DC did not always handle my multi-cycle paths correctly. I carefully watched
a synthesis in progress and discovered that in some cases, DC would accept
the multi-cycle command, appear to work on it, but in reality, it really
didn't like how I specified the start or endpoints, so the directive was
ignored. The path kept showing up. Sometimes this could be corrected
switching from specifying a pin to specifying a cell, but it was not clear
why DC couldn't handle it since the from-list and to-lists are supposed to
handle clocks, ports, pins or cells. The main problem was that you didn't
know that DC didn't understand your multi-cycle command. It was pretty
frustrating, and not nearly as useful as a real static timing analyzer like
Motive. (Perhaps this problem has been corrected, we were using 3.0a at the
time.)
The other problem was that the more mulit-cycle paths specified, the more
likely to run very slow or even crash and burn, Synopsys-FATAL style.
- Ann Nunziata
Apple Computer
( ESNUG 206 Item 6 ) ---------------------------------------------- [1/95]
From: [ Anon ]
Subject: How To Get Design Compiler To Use D-latch w/ AND On Data Inputs
Hi John, (please keep me anonymous),
In our in-house good old standard cells library we have latchs with AND gates
on the data pin. Is there some way to impose that Synopsys to use this AND
gate during HDL compilation?
--- -------
A in---| & \__| D Q |---- X out
B in---| / | |
--- | E |
--------
enable ----'
- [ Anon ]
( ESNUG 206 Networking Section ) ---------------------------------- [1/95]
San Franciso - Consultant fresh from Moto/Philips Europe after completing
Verilog/Synopsys MPEG design available. Kevin Deierling, "SchrodiCat@aol.com"
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