It's like preparing for a hurricane to hit. Every year during the summer
on my usually tranquil sheep farm, my landlord has one gargantuan end of
summer bash. This year he's billing it as the "Poor Farm Woodstock." (He's
already sent out party flyers telling people to "Bring your kids, dogs,
horses, ex-wives, or any farm animals - all are welcome to camp over and
enjoy our 6 live bands!" and "Clothing Optional, but No Bras Permitted!"
The sheep look rather curious around the big circus tent he's set up in the
back pasture. They don't know what to think of the three portapotties for
the 300 to 500 expected "guests." I don't what to think of a landlord who
asks me: "John, know any slutty women? Have them come to the bash this
weekend! We'll have bikers, divorcee's, beer & dancing!" ( Oh, joy! )
And to think most renters complain that landlords frown on big parties...
- John Cooley
the anxious ESNUG guy
( ESNUG 192 Item 1 ) ---------------------------------------------- [8/94]
From: Ken.Kappeler@FtCollinsCO.NCR.COM (Ken Kappeler)
Subject: (ESNUG 191 #2) "Is Anyone Using The Synopsys Static Timing Analyzer?"
> And, is anyone really using Synopsys as a static timing analyzer?
> I don't find it accurate.
As an ASIC vendor, we have a small number of customers wanting to use
Synopsys as a static timing analyzer. In internal tests we have found
that with a correct SDF file, the timing analyzer is as good as the
numbers back-annotated. In prelayout, the timing will be subject to
the timing model chosen, the implementation of the ASIC library, and the
wire load model(s) provided. In postlayout, the only dependence is the
source of your SDF file and its correlation to silicon.
For NCR libraries and layouts we have seen good correlation between what
Synopsys static timing analysis reports and what is calculated and
reported by our timing calculator and layout tools. Admittedly we have
limited exposure to the Synopsys static timing analyzer to date.
I am interested in the limitations you found. Can you expand on this some
more on ESNUG?
- Ken Kappeler
NCR
( ESNUG 192 Item 2 ) ---------------------------------------------- [8/94]
From: ivo@easics.be (Ivo Vandeweerd)
Subject: Count Those Flip-Flops If Using VHDL & Design Compiler Rev 3.1a!
Dear John,
The following bug has appeared in Synopsys 3.1a, which was not present in
Synopsys 3.0c, or older. Both Synopsys VHDL simulation results from 3.0c
and 3.1a agree, so you won't notice anything if you do not start counting
flip-flops yourself !!!
The problem appears when a variable (Kilroy in the SHIFT example below)
is conditionally updated and used in a clocked process. In the example
below, the input A is loaded into Kilroy when the Load signal is active.
If Load becomes inactive low after that, the previous value of Kilroy
should be used.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity SHIFT is
port (
B: out unsigned(1 downto 0);
A: in unsigned(31 downto 0);
Load: in std_logic;
Clock: in std_logic;
Reset: in std_logic
);
end SHIFT;
architecture RTL of SHIFT is
begin
SHIFTPROCESS: process (Clock, Reset)
variable Kilroy: unsigned(31 downto 0);
begin
if (Reset='0') then
B <= (others => '0');
Kilroy := (others => '0');
elsif (Clock'event and Clock='1') then
if (load = '1') then
Kilroy := A;
end if;
B <= Kilroy(1 downto 0);
Kilroy(29 downto 0) := Kilroy(31 downto 2);
end if;
end process SHIFTPROCESS;
end RTL;
---- ---- ----
Using Design Compiler 3.0c I get a healthy:
Statistics for inferred devices in process at line 45 in file
'/home/duvel/ivo/design/txc/CUBIT/scratch/SHIFT/SHIFT_RTL.vhd'
(clock = Clock)
====================================================================
| | Three | Memory | |
| Variable | State | Devices | Width | Conditionally Driven
====================================================================
| B | No | Flip-flop | 2 | No
| Kilroy | No | Flip-flop | 32 | Yes (56)
====================================================================
But when using Design Compiler 3.1a, Kilroy is no longer here!
Inferred memory devices in process 'SHIFTPROCESS' in routine SHIFT line 52
in file '/home/duvel/ivo/design/txc/CUBIT/scratch/SHIFT/SHIFT_RTL.vhd'.
=========================================================================
| Register Name | Type | Width | Bus | AR | AS | SR | SS | ST |
=========================================================================
| B_reg | Flip-flop | 2 | Y | Y | N | N | N | N |
=========================================================================
^
'------ NOTE: Kilroy was never here!
In some way, Design Compiler version 3.1a didn't infer the 32 necessary
flip-flops for the Kilroy variable. In contrast, in version 3.0c there was
no such problem. Be warned !!! Expect lost registers !!!
- Ivo Vandeweerd
Easics, BELGIUM
( ESNUG 192 Item 3 ) ---------------------------------------------- [8/94]
From: bishop@utica.ge.com (David W. Bishop)
Subject: Updating Keys Using Solvit Doesn't Work
John,
I tried updating my keys via Solvit. The keys were promptly delivered,
however the following keys:
FEATURE SynLib-ALU synopsysd 3.1 31-May-1994
FEATURE SynLib-AdvMath synopsysd 3.1 31-May-1994
were already expired! When I contacted Synopsys about updating their
key database on Solvit, I got the reply:
"Unfortunately, the updating of the solvit electro keys is only done
at the time of a new release, due to the fact that it is time consuming
to make updates in the database for even one customer. So the new keys
that were sent to you on paper are not available by Solvit, and the next
time all of the keys in solvit will be updated is planned for August.
I realize that this is not convenient for customers, but that is our
policy right now."
I had to have new keys (perminant ones) faxed to me from back on the 15th
of June!
- David Bishop
Martin Marietta
( ESNUG 192 Item 4 ) ---------------------------------------------- [8/94]
From: oliveira@hpanub.an.hp.com (Chuck Oliveira)
Subject: DesignWare Costs Too Much!
John,
We use the DesignWare library quite routinely here. Are we getting our
money's worth? I am not sure. We seem to only reference DesignWare for
ADDERS/SUBTRACTORS/MULTIPLIERS and a occasional INCREMENTOR. Is there
anyway to design your own DesignWare library? Are there any companies in
the DesignWare library business?
We have one DesignWare library (SynALU and SynAdvMath) for each Synopsys
Design Compiler. We spend about 15% more in maintance for the DesignWare
licenses as we do the Design Compiler licenses. However, I never recall
calling the hotline with any DesignWare problems or questions. If you recall,
DesignWare use to be a "buy 1 get N free" sort of deal. The Synopsys
salesmen did not tell me, "Don't get to hooked on the DesignWare", because
we will soon up your support charges by 300%!"
Any ideas?
- Chuck Oliveira
Hewlett-Packard
( ESNUG 192 Item 5 ) ---------------------------------------------- [8/94]
From: fjm1@tr.rb.unisys.com (Frank J Malloy)
Subject: Can Synopsys Fix Hold Time Violations?
John,
We have been having a very difficult time getting Synopsys to properly fix
hold time violations. "set_fix_hold" currently seems to be a poor
implementation. Here are some of the reasons why:
1. It does not insert delay based upon best case conditions, where hold time
violations can be the worst - it uses whatever operating conditions are
set at the time. If your default is worst case, hold time will NOT be
fixed under best case conditions. Synopsys needs to time using both
best case and worst case conditions in order to correctly fix design
rule violations.
2. It often inserts delay into the path in such a way that can affect a
completely different critical path, possibly making your worst path worse!
Synopsys needs to intelligently insert the delay element, impossible
since it fixes design rule violations at the end, without regard for the
original timing constraints.
3. It inserts delay haphazardly in paths that cross module boundaries,
unless you always do top-down compiles - rarely feasible!
We have had multiple meetings with Synopsys and they are aware of the
problems, but admit they won't be fixed anytime soon. Has anyone else had
problems with set_fix_hold? Any workarounds or suggestions?
- Frank Malloy
Unisys Corp.
( ESNUG 192 Item 6 ) ---------------------------------------------- [8/94]
From: ashok@parcom.ernet.in (B K Ashok)
Subject: Creating SGE Schematics AFTER The Verilog/VHDL Code Was Written
Hello John,
We bought Synopsys recently. Before this, we were using lots of VHDL code
for modeling and simulation with some other tool. This code was enormous
and now, I am finding a need to generate some schematics in SGE for some
higher level modules. (It makes more sense to have pictures at a relatively
high level and then handle the code itself at lower levels.) One main
problem I am facing is that I find no way of attaching a file attribute to
a Symbol in SGE. It is always possible to create a VHDL/Verilog template
from a symbol but the reverse is not ture. Typically, I want to:
Create a SGE symbol from the existing VHDL/Verilog code
- or -
If I already create a symbol manually, how can I attach it to
a corresponding existing Verilog/VHDL file?
Any help would be appreciated.
- B.K. Ashok
Centre for Development of Advanced Computing, Pune, INDIA
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