( SNUG 01 Item 8 ) --------------------------------------------- [ 3/28/01 ]
Subject: Synopsys "Chip Architect" -- A Problem Child
ONE UGLY BABY: When I said I was floored by Aart's "it's a pricing issue"
response to my Chip Architect question, it was because of Chip Architect's
bizzare history. A little over 2 years ago, Jon Stahl of Avici wrote the
first customer review of Chip Architect in ESNUG 338 #1. It was a glowing
report. Then, 2 months ago, Jon Stahl *retracted* his endorsement because
Chip Architect, a hierarchical floorplanner, has problems with *hierarchy*!
"18.) What is your physical design methodology?"
Flat Only ######## 17%
Hierarchical Only ########### 22%
Mixed (Flat & Hier.) ############################### 61%
"It did not completely meet timing and the ECO timing improvement
features of the tool were broken.
I attempted and was able to write a complex script to have Chip
Architect do repeater insertion, but it would only work after I
flattened the entire design (a hierarchical attempt only produced
core dumps). This resulted in timing being met, but led to further
misery as the tool only had the ability to produce a flat netlist
from the flattened physical hierarchy and did not keep separate
logical and physical views. This in itself was ugly, but only
a show-stopper when we attempted to run several other tools which
couldn't handle a totally flat netlist for a design of that size."
- Jon Stahl of Avici ( in ESNUG 363 #1 )
This was a first! Never before in the history of ESNUG had anyone ever
publically endorsed a product and then later retract that endorsement.
Never. And then others started seeing what Jon saw:
"We have a copy of the Chip Architect tool and have attended the
training sessions. While they loudly tout that it supports
hierarchical placement, what is really true and mentioned offhand
by John Stahl is that it can ONLY do separate placement on each
and every hierarchical block.
That means that even DesignWare inserted levels of hierarchy must be
physically regioned on the die if left in the netlist. This is
absurd for large designs with hundreds of hierarchical instances!
You can only run placement starting with lowest levels of hierarchy
and work up. No logical/physical variation is allowed, which is just
a downright odd choice for a company who sold Floorplan Manager
suggesting that you regularly encounter logical/physical mappings."
- Thomas Ayers of Believe, Inc. ( in ESNUG 364 #1 )
"I think that Chip Arch works well as a front end to PhysOpt, but we
don't use it to do placement. Hopefully, Chip Architect will be priced
according to this new (more limited, I guess) role. :-)"
- Lars Bo Graversen of MIPS Technologies ( in ESNUG 365 #4 )
So, basically, Chip Architect is one ugly EDA tool -- which is why I asked
Aart that question during the Q&A after his SNUG'01 Keynote address.
"PhysOpt fits easily in a Synopsys flow. I will have a try on it
(they promised testing licenses). I do not see the use of FlexRoute
or Chip Architect."
- Klaus Vongehr of Philips Semiconductors
"I presented a paper on the breakdown of Synopsys Floorplan Manager
at SNUG'01. We are currently working on the next generation of the
chip I presented and again are improving our flow to solve some of
the problems we had. I am currently looking at using either Chip
Architect or Silicon Perspective's First Encounter for design planning.
We plan on using our front end flow with DC as was presented in our
paper. Both tools have very similar attributes but I feel First
Encounter had done a more complete job of pre-route analysis and
estimates and I am personally leaning that direction. The proof
will be in how either of these tools work with our foundry supplier;
so until that is determined I am keeping an open mind."
- Tom Tessier, t2design
"I benchmarked PhysOpt and got excellent results. I am very happy
about it. I don't see the usefulness of Chip Architect. FlexRoute...
Hmmm. Can not comment as I haven't used it."
- Himanshu Bhatnagar of Conexant
"Chip Architect -
I spent a lot of time learning design flows for Chip Architect and am
concluding that Synopsys may have missed the boat this time. At the
R&D demo Tuesday night I thought I had the scenario figured out. When
I went to the tutorial on Wednesday morning, the scenario started
falling apart when the speaker said CA was the first hierarchical
floor-plan tool on the market. If they really are the first, they
should have asked why.
Chip Architect has all of the ills associated with doing floor-planning
hierarchically. Strict hierarchical approaches divide the die into
non-overlapping regions with logical and physical bounds necessarily
the same. Doing this limits the floor-planner's ability to move cells
anywhere on the chip. I/O cells, hard blocks like RAMs and cores,
clock buffers, and repeater buffers tend to have strong physical
constraints and need to be placed anywhere on the chip regardless of
of their place in the logical hierarchy. Because of the strict
physical constraints on these blocks one solution is to put cells like
I/O cells and hard blocks at the top of the hierarchy. Doing this in
the logical world makes the interconnect a mess. Changing the
hierarchy in the physical world, which CA can do, messes up the formal
verification. The presenter did not have an answer when I questioned
the impact on Formality, but one of the users in the audience was clear
that Formality could not handle the changes in the hierarchy and I
don't think Chrysalis can either.
Without a lot of scripting to reserve space in blocks for logic from
other blocks it is not clear that Chip Architect is usable to do the
type of floor planning we have traditionally done. It may be usable
to do some of the individual tasks in the process like sub-block pin
placement for budgeting, but I'm not sure I'd want to have our
physical/synthesis process revolve around it. The scenario it might
be usable for is the one we originally envisioned for the next
generation of chips. In this scenario we were assembling chips from
chiplets, which were totally self-contained sub designs with
controlled interfaces and buffered inputs and outputs. If you could
rely on Physical Compiler to do all of the internal chiplet placement,
it might be a viable process, but I would not throw out our proprietary
Vimplan-based process just yet."
- Ken Merryman of Unisys
"Did you notice Aart "promising" discounts on Chip Architect to
everyone? :-)"
- Paul Gerlach of Tektronix
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