( ESNUG 364 Item 1 ) --------------------------------------------- [02/01/01]
Subject: ( ESNUG 363 #1 ) Chip Architect (Ironically) CAN'T Do Hierarchy!
> ... although the placement Chip Architect produced was very good, it did
> not completely meet timing and the ECO timing improvement features of the
> tool were broken.
>
> I attempted and was able to write a complex script to have Chip Architect
> do repeater insertion, but it would only work after I flattened the entire
> design (a hierarchical attempt only produced core dumps). This resulted
> in timing being met, but led to further misery as the tool only had the
> ability to produce a flat netlist from the flattened physical hierarchy
> and did not keep separate logical and physical views. This in itself was
> ugly, but only a show-stopper when we attempted to run several other tools
> which couldn't handle a totally flat netlist for a design of that size.
>
> - Jon Stahl
> Avici Systems N. Billerica, MA
From: "Tom Ayers" <tomayers@believe.com>
John,
We have a copy of the Chip Architect tool and have attended the training
sessions. While they loudly tout that it supports hierarchical placement,
what is really true and mentioned offhand by John Stahl is that it can ONLY
do separate placement on each and every hierarchical block.
That means that even DesignWare inserted levels of hierarchy must be
physically regioned on the die if left in the netlist. This is absurd for
large designs with hundreds of hierarchical instances! You can only run
placement starting with lowest levels of hierarchy and work up. No
logical/physical variation is allowed, which is just a downright odd
choice for a company who sold Floorplan Manager suggesting that you
regularly encounter logical/physical mappings.
I would also suspect that this choice has some impact on utilized die area
as it seems like driving hierarchical placement down to the lowest levels
of the netlist and as we know, there is a die area savings by running flat
P&R over hierarchical P&R.
We are currently doing our FPGA prototypes and I promise some material on
that once we have boards up and running.
- Thomas Ayers
Vice President, HW Engineering
Believe, Inc.
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