( ESNUG 365 Item 4 ) --------------------------------------------- [02/15/01]
Subject: ( ESNUG 364 #1 ) Chip Architect Is Over-priced For What It Does
> We have a copy of the Chip Architect tool and have attended the training
> sessions. While they loudly tout that it supports hierarchical placement,
> what is really true and mentioned offhand by John Stahl is that it can
> ONLY do separate placement on each and every hierarchical block.
>
> That means that even DesignWare inserted levels of hierarchy must be
> physically regioned on the die if left in the netlist. This is absurd
> for large designs with hundreds of hierarchical instances!
>
> - Thomas Ayers
> Believe, Inc.
From: Lars Bo Graversen <larsg@mips.com>
Hi John,
At MIPS, we have been evaluating Chip Architect as a front end to Physical
Compiler and have been happy with the results.
We have used Chip Arch to do floor planning before taking the design into
PhysOpt. This has worked well for us, once we got the 3.0 release of Chip
Arch, because the previous version of Chip Arch could not interface
directly with PhysOpt using a .db file. We have used the ChipArch/PhysOpt
flow with several different configurations of a 64 bit processor core
(different technologies, cache RAM sizes, etc.) Not multi-million gate
designs, but designs where timing (speed) is the most important parameter.
We plan to continue to use ChipArch/PhysOpt in our flow in such a way that
a design project will be responsible for iterating on the floor plan using
Chip Arch and PhysOpt before handing off the design to our Avanti backend.
In other words, I think that Chip Arch works well as a front end to PhysOpt,
but we don't use it to do placement. Hopefully, Chip Architect will be
priced according to this new (more limited, I guess) role. :-)
- Lars Bo Graversen
MIPS Technologies Copenhagen, Denmark
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