> Yup, it's that time again. I'm doing the annual DAC Trip Report and
> I'd greatly appreciate it if you took 10 minutes to write what you
> honestly think about the EDA tools that you use in your job. - John
From: John Busco <jbusco=user domain=nvidia spot calm>
Hey John,
Just a Q, why is it called the "DAC" report? Is it in theory based on
this year's DAC? Do you mainly want feedback from people who went to
DAC? (I didn't go.) Keep up the good work.
- John Busco
Nvidia Santa Clara, CA
Editor's Note: Thanks for the question and I understand the confusion.
Don't get caught up in the name "DAC Trip Report". It's just a name.
I call it the "DAC Trip Report" because that's how it started 11 years
ago as a 3 page review I wrote alone. It's now evolved into a massive
annual user survey on all EDA tools. Last year it involved 492 users
thoughts on 252 pages. That's why I publish it in late January; that's
the best time to review the prior year (plus it gives me Christmas
break to put this monster together!) You could have done benchmarks
2 months ago. Or you could have seen one of the 172 online demos at:
http://www.deepchip.com/demos/demos.fhtml
last week. This survey is to give EDA users one annual chance to say
what they think about _any_ EDA tool they've used or considered using
at work. So, yes, even if you were not at DAC, please send in your
thoughts on specific EDA tools in the "DAC Trip Report" survey. - John
( ESNUG 435 Subjects ) ------------------------------------------ [12/08/04]
Item 1: EDA Developer Curious Of Whether Or Not Tera Systems Has A Future
Item 2: Cooley Slapped For No Magma In The Power Part Of The DAC Survey
Item 3: ( ESNUG 433 #1 ) Two Hands-On Users Report On Sierra Pinnacle
Item 4: User Wonders How Aldec's Active-HDL Stacks Up Against Modelsim?
Item 5: ( ESNUG 433 ) AMI Is Still Doing Its Netlist Conversion Service
Item 6: How Do I Get DC To Show Just The Clock Tree And Loads By Itself?
Item 7: ( ESNUG 434 #5 ) Manny Is Fairly Happy With Jupiter-XT, Too
Item 8: ( ESNUG 431 #5 ) Pessimism And PrimeTime-SI Path-Based Analysis
Item 9: Cooley Chastened For No Cadence Testbuilder In The DAC Survey
Item 10: ( SNUG 04 #14 ) SNUG Trip Report Caught PrimeTime-SI Gain Early
Item 11: ( ESNUG 426 #4 ) Mentor On Precision vs. Leonardo Spectrum
Item 12: ( ESNUG 426 #3 ) Mentor On The Precision Slow Runtimes Problem
Item 13: ( ESNUG 426 #6 ) Mentor On The Precision Scripting Problem
Item 14: ( ESNUG 426 #5 ) Mentor On The Precision Stop And "|" Issue
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
============================================================================
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( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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