( ESNUG 435 Item 6 ) -------------------------------------------- [12/08/04]
From: David Tester <david.tester=user domain=diasemi spot calm>
Subject: How Do I Get DC To Show Just The Clock Tree And Loads By Itself?
Hi John,
Do you think the ESNUG community will show mercy for an ex-ASIC guy who
jumped the fence from digital IC design into analog IC design? I hope
so...
I'm working with a mixed signal design, looking at some logic. Not a
huge amount of logic, but enough to make me wish I remembered more of
the Design Compiler manuals from the last time I used Synopsys. That was
a while ago... I'm interested in a clock tree that's already been
inserted and would like to have Design Compiler strip out all the gates
that are not clock tree or it's immediate load (i.e. gate capacitance).
Ideally when I do this I'd like to collapse the hierarchy, too, so I've
got one single schematic (it's not a huge design).
Maybe one of the ESNUG folks have a script they could share to perform
this task?
- David Tester
Dialog Semiconductor Swindon, UK
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