Editor's Note: I'm going to Silicon Valley next week and it looks like
I'll be swinging by the annual Mentor User's Group (MUG) gathering to
give it a look see. The Mentor folk tell me that this year they're
trying to shift their user group focus away from mostly PCB designers
and to mostly chip designers. I've been personally invited in something
they're calling the "Engineering Olympics". Problem is they won't tell
me *anything* of what it is; just that's its fun & technical. I dunno...
Whenever you say the phrase "Engineering Olympics", my mind can only
conjure up images of the Special Olympics -- and my gut tells me that
there's probably not all that much difference between the two. :)
- John Cooley
the ESNUG guy
P.S. I see that Boston SNUG Call-For-Papers is up on its web site now at
http://www.snug-universal.org/northamerica/na_boston.htm . Cool.
( ESNUG 427 Subjects ) ------------------------------------------ [04/14/04]
Item 1: ( ESNUG 426 #1 ) Synplicity vs Xilinx ISE vs Mentor vs Synopsys
Item 2: ( ESNUG 426 #6 ) Two Users Share Their Experiences With DC-FPGA
Item 3: This Magic Switch Gets PrimeTime To Report Unconstrained Paths
Item 4: ( ESNUG 425 #5 ) Neolinear Rebutts Aart's Open Access Stance
Item 5: ( ESNUG 417 #8 ) Interfaces & Vera/VCS vs. Vera/NC-Sim Runtimes
Item 6: How To Specifically Limit DC Synthesis Cell Types And Numbers?
Item 7: What's The User Story On AccelChip's Matlab-to-RTL Converter?
Item 8: CeltIC 4.2 Benchmarks 2x Faster Plus Its PrimeTime Correlation
Item 9: ( ESNUG 421 #2 ) One Customer's Impressions Of Nassda Lexsim
Item 10: 65 nm Is Going To Be Hell If The Fabs Won't Release The Rules!
Item 11: One Man's Review Of The DesignCon East Last Week In Boxboro, MA
Item 12: ( ESNUG 422 #6 ) Silicon Canvas Rebutts The User Review Of Laker
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
============================================================================
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!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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