( ESNUG 427 Item 5 ) -------------------------------------------- [04/14/04]
Subject: ( ESNUG 417 #8 ) Interfaces & Vera/VCS vs. Vera/NC-Sim Runtimes
> Our Synopsys AC is saying that we can improve our Vera simulation run
> times by a factor of between 1.8X and 6X by using Vera/VCS instead of
> Vera/NC-Sim. The reason is that VCS implements a direct kernel interface
> whereas Cadence NC-Sim uses the slower PLI interface. However, when we
> run our testcases, we find that the two approaches are actually quite
> competitive. What's going on? Are we missing out on some performance
> increases that everyone else is getting?
>
> - David Sawey
> Vitesse Semiconductor Corp. Richardson, TX
From: Charles Dawson <chas=user domain=cadence spot calm>
Hi John,
It's my experience that a well behaving simulation spends an insignificant
amount of its time in the actual interface code, whether that interface is
VPI, PLI 1.0, or DKI (or any other proprietary interface for that matter).
If you find that there's a significant difference between a VPI application
and an equivalent DKI one, I would consider that to be a bug. Please let
me know if you see any performance problems and I'll help address them.
The profile options for ncverilog are
+ncprofile +ncsimargs+"-plidebug" +ncprofthread
Using ncsim, the options would be:
-profile -plidebug -profthread
The specific simulation will write an ncprof.out file at the end of the run
containing the profile data. Chapter 14 of the NC-Verilog Simulator Help
Manual will help you understand the data within this file.
- Charles Dawson
Cadence Chelmsford, MA
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