From: SOGLE@cti-main.mhs.compuserve.com (Sean Ogle)
Subject: "Synopsys" Associated With "Peace", "Joy", & "Harmony" ??!
John,
While synthesizing my VHDL code for an ASIC which will eventually go
into a smart bomb, I recieved a year-end politically safe non-religious
greeting card from Synopsys. The card had three words displayed as:
PEACE JOY HARMONY
^%$^$%^ ((@@$#$ |+_%+|!
#%^_%@$ ##)_&^( $$)!@$$
)&*&^^$ *^&*((& ((^%$#@
These are not three words I would normally associate with Synopsys. Do
you have any idea what the correlation could be??? :^)
- Sean Ogle
( ESNUG 205 Item 1 ) ---------------------------------------------- [12/94]
Subject: (ESNUG 204 #5) How Do I Get The "Journal of High-Level Design" ???
> Wow! There's a "Synopsys Journal of High-Level Design"? How do get it?
>
> [ Editor's Note: The Journal is the new name for their old Methodology
> Notes. Meth Notes changed name around August of this year. And, as with
> the Meth Notes, the Journal's published every quarter. (You can get back
> issues of Methodology Notes by calling 800-388-9125.....
From: kdf@aluxs.att.com (Ken Fitch)
Also, the JHLD is available through WWW with the following URL ->
http://www.synopsys.com:80/support/JHLD/
From there, articles can be downloaded in various formats (text only,
PostScript, etc.) and printed locally... I've done it, it really works!
- Ken Fitch
AT&T Bell Labs
---- ---- ---- ----
From: kchung@synopsys.com (Kevin Chung)
John,
Sixteen of the old "Methodology Notes" are in the v3.2a Synopsys Online
documentation. From the main online documentation screen, double click on
the hyper-text link box next to the words "Methodology Notes" and you'll
jump directly to the list of the available Methodology Notes.
- Kevin Chung
Synopsys SolvIt Team
( ESNUG 205 Item 2 ) ---------------------------------------------- [12/94]
Subject: (ESNUG 204 #4) I Want Real MUXes -- Not Logical Equivalents!
>I've got a situation where an asynchronous external signal must be sampled.
>The signal comes from an A-to-D converter with variable sampling clock.
>There is no fixed relationship between the ADC clock and the logic clock,
>except that there are many cycles of the logic clock between each sample.
>The ADC clock can shift across a range of +/- one CLK period, in steps of a
>small fraction of a CLK period.
>The requirement is easily met: use a MUX to hold the old sample until the
>new sample has settled (the actual requirement includes peak-following...see
>the VHDL fragment below). Using a MUX to block the ADC input during
>transitions also means there's no meta-stability risk.
From: greg@cqt.com (Greg Bell)
How about just demetastablizing (sp?) the tc_data_in signal with F-F's
clocked with the logic clock? That's where you send the asynchronous signal
through a couple flip-flops in a row. This greatly reduces the chances that
the signal will be metastable by the time it gets into your design.
FF1 FF2
+---+ +---+
tc_data_in ----D Q-----D Q----> synchronized signal
+-C-+ +-C-+
logic_clk ------^---------^
Your solution *should* work though... Try synthesizing with no constraints
and see what you get. Maybe Synopsys is moving logic around in funny ways
trying to make your timing requirements.
- Greg Bell
CommQuest Technologies
( ESNUG 205 Item 3 ) ---------------------------------------------- [12/94]
Subject: (ESNUG 204 #6) "Seeking Best Verilog to FPGA Design Path"
>We're interested in putting together a Verilog -> FPGA development path. We
>own Design Compiler Expert, Xact, Neocad. We've identified three plausible
>paths, each with different costs and benefits and I'm interested in other's
>experiences with this problem, so we can focus on the approaches most likely
>to be successful.
From: markp@edassc.com (Mark Papamarcos)
My direct experience with using DC-Expert and FPGA Compiler on the same design
suggests that FPGA Compiler can do a substantially better job in some cases.
In particular, in a recent XC4013 design with a lot of register-intensive
datapaths and LFSR's, FPGA Compiler was able to cut out over 20% of the CLB's
simply by use of clock enables. DC-Expert did not perform this Xilinx
specific optimization. This also greatly enhanced performance by reducing
logic levels and getting logic into single CLBs which formerly couldn't fit.
The other FPGA Compiler feature which helped us a lot was the feeding forward
of timing constraints. While the timing models in FPGA Compiler are still
not great, this did save considerable effort in the normally ponderous task
of constraining Xilinx's place & route, even when the initial implementation
of this feature in 3.1a was very buggy.
- Mark Papamarcos
EDA Associates
---- ---- ---- ----
From: taub@corp.cirrus.com (Ed Taub)
John,
We did a HW emulator using a single Xilinx + Synopsys FPGA compiler to XACT.
(I am giving a talk on it at Design Supercon 95 on ASIC verification.)
The only problems we found were a failure of FPGA compiler to produce a latch
when we gave it an ...else latcha=latcha clause. We had to delete the "else"
to force a latch. Design Compiler bought the original syntax and did
synthesize correctly.
Also, there is a bit of magic to get bidi external I/O pins to work correctly.
You also need to know how to limit use of special clock driver I/O pins in
Xilinx. The XACT software foolishy assigns too many signals and exceeds the
number of pins unless you designate which pins are actually the system clock.
I heartily recommend this path if you are already using Verilog/Synopsys. We
got excellent results and barely had to read the manuals. It has saved many
many tapeouts.
- Ed Taub
Cirrus Logic
( ESNUG 205 Item 5 ) ---------------------------------------------- [12/94]
From: thug@tus.ssi1.com (Gloria Hu)
Subject: Headaches Going From Synopsys To Mentor Using "db2eddm"
I read your story in EDN "A Call for Horror Stories" and would like to
subscribe to the E-mail Synopsys User Group (ESNUG). We have a group within
our company that is trying to go from Synopsys database (.db files) into
Mentor by using their db2eddm product. (When we asked both Mentor & Synopsys
about going from EDIF to EDDM, the answer was a definite "NO".) We have
encountered some problems with the db2eddm path (nets crossing bus rippers
that were shorted in Mentor and not in Synopsys, etc.) and find this problem
time consuming and cumbersome. Do you have any suggestions from any of your
ESNUG readers?
- Gloria Hu
SSI
( ESNUG 205 Item 6 ) ---------------------------------------------- [12/94]
From: ashok@parcom.ernet.in (B K Ashok)
Subject: Have To Hand Edit Timing Specs When Using FPGA Compiler
John,
How do I guide the FPGA compiler to write out the TNM path timing attribute?
XCAT 5.0 supports this new timing specification but I have no idea how do
I do that during synthesis process. I have tried to use path timing spec in
the Design Analyzer but if I do a compile after this, it appears that Synopsys
tries to build logic with that path constraint; It does not write out the TNM
time spec on the indivudal blocks. At present, I am manually editing the xtf
file and inserting the TNM attribute. Is there any way I can do that in the
dc_shell/design_analyzer?
- B.K.Ashok
Parcom
( ESNUG 205 Item 7 ) ---------------------------------------------- [12/94]
From: fmicos!splinter!flieder@uunet.uu.net (Jeff Flieder)
Subject: Get Those SNUG Abstracts In Soon!
John,
Here's a list of the breakout leaders and how to contact them. If anyone
wants to present at SNUG '95 this upcoming March they should send a quickie,
short abstract REAL SOON NOW to the breakout leader and myself.
Design Reuse: Kurt Baty kurt@wsfdb.com (508) 429-4198
Synthesis: John Cooley jcooley@world.std.com (508) 429-4357
Verification: Erik Magdanz erikm@synopsys.com (415) 694-1522
Layout Issues: Volker Kiefer kieferv@chdasic.sps.mot.com (602) 814-4228
Clock Tree Syn: Willis Hendley willis.hendley@east.sun.com (508) 442-0444
Test Compiler: John Vogel johnv@chdasic.sps.mot.com (410) 312-5939
We're a little light at the moment in getting abstracts relating to General
Synthesis and Clock Tree Synthesis.
- Jeff Flieder
SNUG Technical Program Chair (719) 528-7718
( ESNUG 205 Item 8 ) ---------------------------------------------- [12/94]
From: slau@netcom.com (Simon Lau)
Subject: Thanks For Running ESNUG
John,
I have enjoyed reading your ESNUG posting all year long. You did a wonderful
job in putting it together. It is informative and has helped me in my work
several times. Just would like to say thank you again & have a happy holiday.
- Simon Lau
Editor's Note: I'd like to thank my fellow Synopsys users who took the time
to write up the bugs they were encountering plus replying to the problems
others published on ESNUG -- it's this honest, no-bullshit interaction that
makes ESNUG worth reading. Thanks & Enjoy the holidays!
- John Cooley
the ESNUG guy
P.S. Also a big thanks to those who sent me christmas cards. They are much
more enjoyable to read than the junk mail that usually overflows my snail
mail P.O. box each week (90% of which ends up in my woodstove.) Ho! Ho! Ho!
|
|
