Roommate matching for DAC! Send me e-mail if you're a consultant like
myself who is going to DAC on one's own money and would like to share hotel
expenses with a fellow consultant. Please specify if you smoke and which
nights you'll be needing lodging (e.g. Mon - Weds). If you already have
a hotel reservation, please include that info, too. - John Cooley
( ESNUG 130 #1 ) ---------------------------------------------------- [6/3/93]
Subject: (ESNUG 128 #2) "Revision Control with VSS"
>We are trying to implement revision control using the VSS tools.
>Does anyone have any good experiences with this type of activity?
>
>At first, we tried to use SCCS, but we gave up because it could
>not handle .sym files from SGE as they have more than the allowable
>number of characters per line.
>
>Next we tried RCS, which handles .sym files, but we are concerned
>because we cannot retrieve an old version of a .sch or .sym file
>(since we do not know how to add a literal string to these files).
-- -- -- -- -- --
From: uunet!jericho!gord (Gord Wait)
We use a Seiko licensed version of CadCam ECS tools (SGE is a Synopsys
licensed version of CadCam ECS tools). We use SCCS for our schematics
and symbols (.sch and .sym files). I think that the problem you had
with SCCS is that you did not tell SCCS that the .sch and .sym files
were binary, not text. IE try this:
sccs enter -b blat.sch
sccs enter -b blat.sym
It works fine for us.
- Gord Wait
S-MOS Systems Vancouver Design Center
Canada
-- -- -- -- -- --
From: Michael Chapman <mchapman@eis.k8.rt.bosch.de>
We are using CVS for revision control with mostly good experiences up
to now. (The bad experiences are with wholescale name/directory structure
changes).
We do not archive any .sim, .mra files but regenerate them using a makefile.
We will probably do the same thing with the synthesis stuff when we reach
that stage provided that the CPU time to regenerate the .db files is not
too high. If if takes too long to regenerate the .db files then we will
archive those with CVS as well. The real big advantage of CVS over SCCS
is the ability to give a name to any given configuration of files and
later to recover exactly that configuration.
Makefiles for VSS are tricky as simdepends just does not work when you have
multiple libraries and directories. We have been forced to write our own
version which works for our particular design methodology and model structure
and takes into account a things like automagic component generation and
include files and works directly from the source files. As this was a quick
hack there are many cases for which it does not work, but for our methodology,
(file naming conventions, library conventions, directory structure, model
source file structure etc etc) it does (just).
( ESNUG 130 #2 ) ---------------------------------------------------- [6/3/93]
Subject: Changing From Register Inferencing to Latch Inferencing
From: swoods@els.cray.com (Stephen Woods)
John,
Here's a simple question:
We have recently created a mass of verilog that uses the flip/flop inference
of "always @ (posedge clk)". Due to various reasons we have to change to a
latch based design.
Is there a simple way to have Synopsys map the flip/flop inference to a latch
without changing the verilog?
Thanks for the help.
- Steve Woods
Cray Research
( ESNUG 130 #3 ) ---------------------------------------------------- [6/3/93]
From: bugs@sh.alcbel.be (F. De Meersman)
Subject: Want to Get Rid of Escape Characters in db Files
I am investigating the transfer of a design, from the Synopsys db file via
a verilog netlist towards Cadence Opus Framework, using Opus verilogIn.
In my opinion, this way should work efficiently, but I have seen that there
are serious problems in the verilogIn once your design contains the so-called
escape characters (like a '\').
These characters need to disappear from the verilog netlist and it is my
hope to do this within Synopsys.
Remark : although there is a automatic way to to this with the Opus verilogIn
itself ( the map escape name button), this method has been rejected, because
if VerilogIn would map these characters to something else, those changes are
not present in the Synopsys db, and it will be very difficult to do a
backannotation to the Synopsys db when the layout is finished, because the
names of the instances and wires might be different.
My idea was to get a 'clean' verilog netlist out of Synopsys, that I can read
in in Opus with verilogIn, without any change at all to the netlist.
With the synopsys change_names command, I can do a lot but I still have one
problem : the \#UNCONNECTED that is inserted in the verilog netlist, when a bit of
a port a not connected.
Whatever I tried , the '\' was still present in the verilog netlist.
Does somebody have any experience with this ?
- Frank De Meersman
Alcatel - Bell
( ESNUG 130 Networking Section ) ------------------------------------ [6/3/93]
SF consultant in >100K gate ASICs, CPUs, DSP, graphics, IEEE F.P., Synopsys,
Verilog, Zycad, C, C++. - Edward Paluch (408) 252-ASIC paluch@netcom.com
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