( ESNUG 128 #1) ------------------------------------------------------------
Subject: (ESNUG 127 #4) "Q_Bar pins on DFFs"
> I thought I'd seen this mentioned before, but I can't find it:
>
> How do you get Synopsys (3.0x) to utilize the q bar pin of a d flip flop?
> Or can you? I made a simple test module in Verilog, with both q and q_bar
> outs, but Synopsys ignored the q_bar pin from the library part, and
> just added an inverter to the q output. Kind of a pain.
>
> Any suggestions besides hand instantiating? I wouldn't bother
> hand instantiating them at this point. I prefer wasting a gate
> to remain portable...
-- -- -- -- -- --
From: Oren Rubinstein <oren@waterloo.hp.com>
To start with, your flop probably has an inverter inside to generate Q_bar,
so it's only a matter of how much can that output drive. If Synopsys decided
to put an inverter on the Q output, it means that for that particular load,
this combination is faster.
I've personally seen Synopsys use the Q_bar output. The decision to use it
or not is based on the constraints that you put on the design. One sure way
to force Synopsys to use Q_bar is to put a max_area constraint on your design,
but then the speed will suffer.
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
Panacom Automation Division
Waterloo, Ontario, CANADA
-- -- -- -- -- --
From: danw@wellfleet.com (Dan Westerberg)
If a registered signal stays within the module containing the flip-flop,
I've found that Synopsys will indeed use the Q_BAR output. Depending on how
the code is written and what you're expecting Synopsys to do, I suspect
you're running into 1 of 2 things:
1) The signal leaves the module and you're not using boundary optimization.
Without BO, Synopsys cannot logically invert a signal across boundaries.
2) The library model does not correctly describe the logical relationship
between Q and Q_BAR.
- Dan Westerberg
Wellfleet Communications, Bedford MA
-- -- -- -- -- --
From: Derek L. Schwenke <derek@hri.com>
In general, the compiler does not evaluate Q/Q_bar until some
constraint forces it to optimize that net.
I have had this problem on several occasions and it boils down to
two scenarios:
SCENARIO #1: DFF and logic in the same block
If the DFF and receiving logic are on the same page,
BE SURE a clock and output constraint has been set for this block.
(check by setting current design; report_clock; report_port)
Synopsys does no (Q/Q_bar) optimization without a timing constraints set.
In order to get BOTH Q and Q_bar used, you may need to set the clock
extra small (like zero ns.) to force the compiler to evaluate the
Q/Q_bar trade off and use both outputs.
(If you are not making your clock requirement, sometimes you can get)
(an extra 5% by compiling with zero ns clock. Its a hack but it works)
(I think this forces synopsys to evaluate more possible configurations)
(Anyone else have this experience?)
SCENARIO #2: DFF and logic on different blocks
If the DFF and receiving logic are in different modules,
You need the "optimize_boundaries" command to help select Q/Q_bar.
For most real world circuits, this command does not make any changes at
all. Because "optimize_boundaries" only swithes Q/Q_bar if (1) both outputs
are available, (2) only Q OR Q_bar terms occure in your circuit (Says my FE).
"optimize_boundaries" can never route BOTH Q/Q_bar to a module,
although, we might need to do just that to make the fastest or smallest
design. I think Synopsys never wanted to change the number of ports on
a module (but they should have done it). Until Synopsys can fix their
code, you will have to route both Q/Q_bar to each receiving module.
I put in a bug report on this (STAR12656).
(This is a poor answer because Synopsys recommends that all module)
(outputs be registered, with Q/Q_bar available, yet normally)
(only one of these outputs will be used and we have to guess which)
(one will result in faster logic.)
- Derek L. Schwenke
Horizon Research Inc.
Waltham, Mass.
-- -- -- -- -- --
From: sylvie@ncrcol.columbiasc.NCR.com (Sylvie.Haddad)
The following is an example of how it is done in VHDL (I guess equivalent
Verilog code should also work.):
entity glock is
port ( clk,a : in bit;
z : out bit);
end glock;
architecture my_arch of glock is
signal tmp : bit;
begin
process (clk)
begin
if (clk'event and clk = '1') then
z <= not a;
end if;
end process;
end my_arch;
- Sylvie Feghali Haddad
NCR, Midrange Computer Products Division
West Columbia, South Carolina
( ESNUG 128 #2) ------------------------------------------------------------
From: bill@txc.com (Bill Rubin)
Subject: Revision Control with VSS
We are trying to implement revision control using the VSS tools.
Does anyone have any good experiences with this type of activity?
At first, we tried to use SCCS, but we gave up because it could
not handle .sym files from SGE as they have more than the allowable
number of characters per line.
Next we tried RCS, which handles .sym files, but we are concerned
because we cannot retrieve an old version of a .sch or .sym file
(since we do not know how to add a literal string to these files).
Finally, we have not yet decided whether we need to keep .mra and
..sim files under revision control or just to regenerate them with
a makefile. The same is true of .db files. We do not know how to
add a literal string to these binary files either.
( ESNUG 128 #3) ------------------------------------------------------------
From: epakch@epa.ericsson.se (Kenny Chow - T/HGH)
Subject: Does a Verilog Execute Path Checker Exist?
John,
I have a question concerning Verilog only. Do you know if there is any product
or s/w in the public domain that can help in RTL/behavioral model simulation
and tell you if all the lines are executed and all possible branches of 'if'
and 'case' statements are exausted during a simulation with a certain
stimulus ?
Thanks for your help & best regards,
- Kenny Chow
Ericsson Australia Pty. Ltd.
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