( DAC'20 Item 07a ) ----------------------------------------------- [11/23/21]
Subject: Empyrean Polas power MOSFET current drain tool is Best of 2020 #7a
POWER MOSFET ANALYSIS: Nearly every chip does power conversion using a power
management IC and one giant power MOSFET transistor. This is true for tiny
cell phones all the way up to industrial motors.
Because power MOSFET transistors have many fingers, the challenge is to make
sure its currents drain efficiently, reliably, and synchronously -- kind of
like lots of cars passing through a toll booth efficiently.
The four aspects that the MOSFET power design guys look at are:
EM IR-drop gate timing delays RDS(on)
Like most other chip designers, I get what those first 3 aspects are... but
that RDS(on) stuff is weird. Google it. You'll see.
But regardless, what I found out about RDS(on) is Power MOSFET transistor
designers manually calculate the RDS(on) number based on the layout of
their transistor and interconnect wiring -- and when designs become complex,
it's time consuming and hard to get the accuracy needed. What makes it
worst is there's two flavors RDS(on) -- the static value -- and the dynamic
value that's sensitive to transistor switching patterns.
This all used to be done manually. That is, by hand entering values into
spreadsheets and grinding away, etc. to get the static RDS(on). And the
dynamic RDS(on) wasn't possible. That is, until Empyrean R&D decided
to create Polas -- and integrated Polas with ALPS SPICE to provide both
dynamic analysis on top of static RDS(on) analysis.
"RDS(on) for Power MOS is very important. Calculating the resistance
manually takes a lot of effort. Using a tool to automate this
is necessary."
"Polas gives us a resistance table which shows the layer resistance
contribution. Our engineers use it as a guide when updating the
layers that have high resistance and can be bottlenecks. It helps
us to make a design better."
"The results have been very accurate for us, based on comparison to
the test results from our chips."
"Empyrean Polas evaluates the performance of Power MOSFET structures,
especially power MOSFET arrays. It's a good analysis tool, combining
simulation, circuit analysis, and parasitic R and C extraction."
"EM analysis is my favorite part of Polas. It improves reliability
a lot. I can use it to ensure a 10-year lifetime for the chip."
IT'S USED FOR SIGN-OFF: The other interesting aspect that caught my eye in
the customer responses is how many power MOSFET design groups already use
Polas as part of their sign-off.
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen in 2020? WHY did they interest you?"
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Empyrean Polas is good for the layout optimization of a circuits
that have large currents. I used it on a power MOSFET layout to
improve the reliability and yield.
Polas inputs are: LVS rules, table file, RCE layer map, model config,
and layout GDS. Polas supports both the GDSII and OA formats, but
I used GDSII format.
Some Polas features that I found useful:
- Accurate RDS(on) -- drain-source-on-resistance calculations.
I use them to check channel resistance and the resistance of
all the layers as part of optimizing our power IC layout.
The Polas layer resistance report helped us detect our
power path bottlenecks.
- Electromagnetic (EM) analysis -- to analyze the power MOSFET
layout for current density of metal layers and vias and EM
violations. I used this to find and tweak the weak spots
in the layers and vias.
- IR-drop analysis, which took contacts, vias, and metal layers
into account.
- Power MOSFET timing analysis -- analyzes the gate delay
distribution. Polas uses extraction and simulation engines.
I used Polas for optimizing power MOSFET and would recommend it to other
users.
It has good visualization of the current density of layers, vias, and
contacts -- which makes it easier to see the weak spot in layers, vias
and contact -- and then improve them.
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We use Empyrean Polas to do layout reliability analysis on our power
MOSFET designs. We run Polas as part of signoff.
I use Polas mostly with GDSII files.
Polas' takes the layout GDSII and produces a detailed analysis:
1. EM analysis. This is my favorite part of Polas.
- It analyzes the power MOSFET layout for voltage, current
density, and EM violation distribution. It checks for
mess-ups in all the layers and the paths.
- The results are detailed and accurate enough for me to
optimize the layout.
- It helps us improve our power circuit reliability a lot.
I can use it to ensure a 10-year lifetime for the chip.
2. IR-drop analysis. Does RDS(on) calcs ("layer resistance
contributions") on the contacts, vias, and metal layers to
optimize the layout -- by showing which layer(s) contribute
most to the total resistance.
3. Other Polas analysis. I haven't used these yet.
- Timing Delay. Analyzes the MOSFET gate timing delay
distribution using extraction and simulation engines.
- Crosstalk. Identifies noisy nets that may interfere
with other signal nets.
Following the Polas analysis, I go back to my layout tool to make
any needed changes.
I recommend Polas to my colleagues. It has a good compatibility
with the foundry tech files. I also like that it can co-simulate
with Empyrean Argus and ALPS.
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Empyrean Polas evaluates the performance of Power MOSFET structures,
especially power MOSFET arrays. It's a good analysis tool, combining
simulation, circuit analysis, and parasitic R and C extraction.
We use Polas as part of our sign-off for our Power MOSFETS.
The Polas analysis includes PAD-to-PAD resistance, the voltage and
current around MOS array, and even the delay on every MOS gate. All
we need as input are the layout GDS and the parasitic resistance
and capacitance extraction files; and occasionally we need the
simulation model files.
We use the Polas GUI to setup selected information based on our design,
and then get three types of analysis results:
1. RDS(on) with the resistance table -- shown in a text file,
which contains the total resistance and the resistance for
different metal layers and nets.
2. IR drop data file -- can be viewed as a graphic, which
displays the voltage and current information on all metal
shapes.
3. Timing Delay -- can also be reviewed as a graphic.
The power switch resistance is very important to the quality and
reliability of our power chip. Our steps:
- First, we use Polas to calculate the Power MOS resistance.
- Second, Polas calculates the metal wire currents -- which
are very sensitive to our design rule requirements.
- Third, Polas reports the time turn the power MOS on or off.
- After evaluating the power MOS structure using Polas, we
are able optimize the layout to improve the quality and
reliability of our power switch.
I have more details on some of Polas' features below.
RDS(on) for Power MOS
This is very important. But calculating the resistance manually
takes a lot of effort. Using a tool to automate this is necessary.
Polas gives us a resistance table which shows the "layer resistance
contribution". Our engineers use it as a guide when updating the
layers that have high resistance and can be bottlenecks. It helps
us to make design better.
The results have been very accurate for us, based on comparison to
the test results from our chips.
Timing Analysis
Polas analyzes the MOSFET gate timing delays and presents the data
visually, for engineers to use to decrease the timing delays.
This is useful and important.
IR-drop analysis
For the IR-drop result, we can review the voltage, current at every
point of metal, via, and channel. We can see the current distribution
on every metal shape. We can analyze the current from PAD-to-metal,
from metal-to-channel, from channel-to-metal in another side, then to
another PAD. All the information shows if the Power MOS works well.
We can also see voltage values on metal. The we can get an accurate
reference voltage if we want.
Fit in our Cadence tool flow
Polas works with GDSII. Other data formats such as OpenAccess data
can be exported as GDSII.
We currently use Polas with Cadence Virtuoso, it is well-integrated.
Open the GUI from the layout view and start to run the tool, just
like other tools we use with Virtuoso.
I recommend Polas. We've confirmed its accuracy, and its analysis
helped us catch and fix design issues.
Our design team must evaluate RDS(on) and IR-drop before taping out;
it is part of our sign-off process. Experienced engineers can
control the gate delay, but we also recommend engineers double
check it with Polas.
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Empyrean Polas uses parasitic extraction to analyze the RDS(on) and
IR-drop of a power MOS. We use it for our large-area power MOS
designs, usually with a multi-metal path and package frame.
The inputs are GDS, LVS deck, RC table (from itf file), layer map,
and model configuration. The tool produces analysis for IR-drop,
RDS(on), and timing delay.
We use Empyreans IR-drop and RDS(on) data to help us analyze: the
position of sense MOS; the rationality of metal path layout; and
the RDS(on) of power MOS. It lets us view the total RDS(on) of
the power MOS and then analyze the contribution of each layer to
guide layout optimization.
Polas analyzes the current density of each layer, then finds the
current density points that exceed the process regulations that
must be corrected. Moreover, we use the MOS current density info
to guide the placement of the sense MOS.
We typically use Polas with Empyrean's Aether design platform,
and with both the OA and GDS formats.
Polas is important for guiding the design of power supply MOS and
can be used for signoff. I would recommend it to others.
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Empyrean Polas is good for power transistor layout quantization.
Polas helps us improve the reliability and yield of our power
management IC by quantifying the layout index to guide our
layout modification and optimization tweaks.
We use Polas for:
1. RDS(on) calculations, with layer resistance contribution
2. Gate timing delay analysis for power MOSFET
3. Power transistor layout IR-drop, based on contact, via,
and metal layer data.
We use Polas for layout quantitative analysis and as part of our
sign-off. We use it with Empyrean Aether design environment.
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