( DAC'17 Item 1a ) ------------------------------------------------ [11/09/17]
Subject: Cadence Perspec wins #1 in #1 "Best of 2017" with Portable Stimulus
THE PSS HORSERACE HAS BEGUN!: Talk about timing the news -- the week right
before DAC'17, the Accellera PSWG announced that *both* the Breker C++ and
the Cadence/Mentor DSL languages were going to be in the Portable Stimulus
Specification (PSS), thus finally kicking off a big ...
... 4-way PSS tool horserace and judging from the user comments -- RIGHT
NOW it has Cadence Perspec in 1st, Breker TrekSoC in 2nd, and Mentor InFact
in a very distant 4th... plus a mythical Synopsys Mystery PSS tool lingering
somewhere in a less distant 3rd place. (And no, not a typo. Mentor InFact
came in 4th place, *behind* Synopsys PSS, in this user survey.)
PSS Tool Word Counts in DeepChip "Best of 2017" EDA User Survey:
Cadence Perspec: ############################### (3,097 words)
Breker TrekSoC: ############### (1,476 words)
Mentor InFact: . (24 words)
SNPS Mystery PSS: ## (188 words)
TECHNICAL NOTES: What most users complained about with Perspec was the pain
of its first set-up and on learning SLN -- but this was NOT a complaint if
they had veteran Specman 'e' users on staff. No surprise since Cadence SLN
and Specman 'e' are both Aspect-oriented (vs. Object-oriented) tools.
What most users liked about Perspec was the payoff they got with it after
the intial ramp-up. Big "likes" for it's ARM libs, it's coverage-driven
pattern generation, and of course stimulus reuse across derivative SoCs
and through all the stages of SoC development. (Hence the name "Portable
Stimulus".)
What's going to be interesting to watch is how Specman 'e' Perspec migrates
over to the official Accellera PSWG DSL standard. Will Perspec DSL play
nice with its PSS rivals? Or will it be only nice for CDNS tools?
But then again, I can't question Perspec too much, because it easily got the
most users (33) commenting on *any* one tool as the "Best of" for 2017.
"The era of gentleman racing driver is ended."
- Enzo Ferrari, Italian racecar driver (1898 - 1988)
"The trouble with the rat race is even if you win,
you're still a rat."
- Lily Tomlin, American comedian (1939 - present)
"Horse racing is animated roulette."
- Roger Kahn, American sports writer (1927 - present)
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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Cadence Perspec
Perspec automatically generates your SoC tests from models of your
design, which can save many man-months of effort. Also, the tests
are 'portable' across multiple verification tools.
We've been using Perspec for a few years now. We picked it because:
- Easy to model complex SoCs using Perspec's SLN language.
(Cadence donated SLN to Accellera as the starting point for
PSS, and the majority of PSS is now based on SLN concepts,
though Accellera changed some of the notations.)
- Cadence was the first to demonstrate multi-processor
capabilities.
Perspec has evolved. What it does now:
1. Modeling
- With Perspec it is easy to divide your entire chip design space
into small subsystems. The subsystems can be functional, as
like coherency issues, or they could be physical subsystems.
- They have a collection of actions. Input and output of an action
of a subsystem is clearly defined, as well as the use cases
between actions.
- The libraries have low-level and high-level actions. Users can
drag and customize them, then Perspec figures out the possible
inputs and and outputs, and builds the whole thing automatically
for you.
2. Test Intent
- In Perspec it's easy to describe high-level hierarchical actions.
You can also describe partial intentions, and only test what you
care about.
3. Debug
- Cadence Indago supports Perspec SLN.
4. Coverage
- Perspec has broader coverage functionality. It tells you what
your tests will cover in advance, plus afterwards, it measures
what the tests exercised. Plus the coverage information is
integrated into Cadence's V-Manager so it can be combined with
your other coverage reporting.
5. ARM Libraries
- Perspec has an ARM library, which is a set of all the actions
available for all the different ARM components. For example,
they have a lot of actions for ARM coherency and power.
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I used Cadence Perspec for the first time this year, on a project with
a tight schedule.
In our division, we traditionally write directed C patterns to address
our top use case verification.
For this project, we needed to randomize our top use case patterns to
cover more different scenarios, with random data and random sequence
of actions.
We chose Perspec cause:
- Some team members were already using Perspec at IP level and
were happy with the tool's maturity and Cadence's support.
- We knew the CDNS Perspec application engineer well - he really
helped us setting up the tool and writing the model. He's
an ex-Specman 'e' guy, so SLN is easy for him.
- Perspec's SLN model, which we used to create our scenarios, is
a good solution for us. It brings some abstraction from
our C patterns, and makes maintenance and reusability of our
patterns easy.
- Perspec's coverage-driven pattern generation allowed us to
create scenarios that we would not have created manually, due
to their complexity.
The Perspec GUI is useful when you write and review scenarios. We also
like how it works well with Indago when it comes to debugging long and
complex patterns.
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Cadence Perspec
It creates random scenarios and stresses the control flow of our entire
SoC design.
With it we randomly generate C tests that cover our complex use cases.
We also get a high level of concurrency -- based on the SW drivers
already developed for the SoC directed tests for use in our software
driver verification environment.
These random tests are integrated in our SoC non-regression database,
running on RTL and gate netlist, and contributing to code coverage.
On the first SoC we applied Perspec to, we caught a functional bug that
we would have missed otherwise.
We now plan to integrate the application drivers developed by our
software teams into the Perspec database.
We also plan to deploy Perspec on each and every SoC we are verifying.
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Cadence Perspec System Verifier
We have been using Cadence Perspec for a while now. We use it to:
1. Reuse stimulus across all our derived chips from a base chip.
2. Reuse our stimulus across platforms -- we currently use it
for Incisive simulation and Protium acceleration.
We expect the Perspec migration over to the new Accellera PSS DSL
and PSS C++ specs will be a fairly smooth transition.
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Cadence Perspec
1) Perspec can visualize complex test scenarios like use-cases
that include hardware and software behaviors. It helps
verification engineers understand and reuse the scenarios
across a series of controllers.
2) Perspec has a fast constraint solver making all parameter
combinations and constraint random tests easy to do.
3) The Perspec scenario model is structured. And it's easy
to restructure the scenario by changing the order of its
components.
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We use Cadence Perspec to generate 'C' test code for IP verification.
We use it to create a script to customize our IP input data and UVM
sequence, as well as a script to create the expected output data with
IP model.
With it, we can easily create a coherent system test based on our IP
model. (Our integrator may not need to enter in the full IP
specification to generate a valid system test!)
Perspec help us generate more tests, and more complex tests at the
system level. We are no longer limited by the time it takes to
generate good functional tests, only simulation time.
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I used Perspec at the IP verification level for a bus decoder. Perspec
automatically generated tests that randomized the accesses to all the
mapping without forgetting some zones.
It saved me a lot of time, as these checks were very important. It
also improved our overall verification, thanks to randomization.
The few weeks it took to put Perspec in place was not big compared
to the net benefit we got from it.
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Cadence Perspec
With it our early IP guys can talk to our SoC guys, who can talk
to our functional verif. guys, who could talk to our post-silicon
verif. guys.
Its automated test generation based on the formal declaration of an
*action* is great for complex system level tests -- which would not
be possible to create manually.
- Perspec actions let IP domain experts focus on their own IP.
- Chip architects or someone more familiar with system but not a
verification expert can use the actions to visually create
complex scenarios.
This was a huge improvement in productivity and quality of stimulus.
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Cadence Perspec
In principle, a portable stimulus tool (which Perspec is) should:
1. Allow easy portability of tests/stimulus across platforms
(simulation/emulation/silicon)
2. Allow easy re-use from IP-level to sub-system to SoC level.
3. Allow easy generation of stimulus in a constrained random
way and for better coverage.
Perspec enables #1 for us, because our stimulus is in C. So we can
re-use it across platforms like simulation, emulation and silicon.
Perspect supports #2 by enabling stimulus generation in either
SystemVerilog (block level) or C. (However, I have not used Perspec
to generate SystemVerilog code.)
Perspec makes #3 possible by allowing C-code to be generated using
random data/parameters which would otherwise have been difficult in
a pure C-based environment.
Perspec Test Generation: grade A+
I've found that the tests that Perspec generates are:
- Less prone to coding errors, typos etc., compared with
manual tests.
- Easily portable across projects and a lot more readable
than hand-written tests.
Perspec Set-Up: grade B+
Perspec Learning Curve: grade C-
- The time to setup the infrastructure for generating stimulus
depends based on the project complexity.
- WARNING: Initially, the set up could take months to completely
migrate your tests for a large SoC over to Perspec. A lack of
in-house expertise in Perspec's modelling language SLN would
also make it tougher during initial ramp up.
- Once the initial Perspec setup is done, developing new tests
and scenarios is much faster -- especially if your developers
have some basic training and/or understanding of the tool at
that point.
Perspec ARM Libraries: grade A+
- Perspec also provides ARM libraries.
- We use them both at the core-level (ARM subsystem) and SoC
levels.
- They provide actions for commonly used APIs/actions for
coherency, low power, exclusives, etc. for ARM based SoCs.
Languages & GUI: grade A
- We primarily use Perspec for C-based tests at SoC level. But
it also supports other languages like System-Verilog.
- The Perspec GUI is quite user-friendly -- we use it primarily
to debug Perspec stimulus-generation issues.
- It also provides a graphical representation of every test
sequence -- which is useful when trying to understand complex
testcases.
Stimulus Portability: grade B
- Since we generate stimulus as C-based tests, they are easily
re-usable across simulation, emulation and silicon platforms.
Although for silicon, we cannot develop tests that do back-door
writes/reads to memories.
- The re-use is possible mainly because the stimulus is in C.
I am not sure how effective re-use with Perspec would be for
SystemVerilog-based stimulus.
Debug and Coverage Logging: grade B+
- In general, I have found Perspec's debug capabilities to be
reasonably good.
- Although coverage is possible with Perspec, we have not used
it much -- we rely more on Real Intent Ascent RTL coverage.
Perspec Constraint Solving: grade A
- Allowing our C-based tests to be customized and randomized
in a constrained way is one of the big advantages of using
Perspec over a traditional approach.
- For example, while moving from one project to another, we only
need to customize the Perspec model with new memory
map/parameters/constraints, then re-run the tool -- we do not
need to hack every single test manually with different
parameters for each project. This is especially true when the
new project is a derivative of some previous project.
Overall, using Perspec has led to increased code maintainability,
readability and re-usability (across projects and across platforms).
It provides good hooks to generate C-code with random constraints which
would otherwise have been difficult in a purely manual C-based approach.
On the downside, it takes time to setup and migrate existing projects
completely to Perspec, as the tool is new and there are few people who
have expertise in it.
Cadence says they plan to support Accellera's new portable stimulus
standard closely following its official approval.
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Cadence Perspec:
- GOOD NEWS -- It's good in randomization SoC verification
"use" cases with C code near to the real running application.
(That is hard to do with Breker and InFact.)
- BAD NEWS -- Your engineers need new skills to use it Perspec
efficiently, in term of language and methodology mindset.
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Cadence Perspec
It looks helpful for constraint-based test case generation, which I
personally want to explore for our verification environment.
The only bottleneck is learning the "SLN" Language, which overlaps a
lot with the 'e' language -- if you don't have an engineer who is
familiar with 'e' and Specman, it might take a little time to develop
your in-house resource.
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I nominate Perspec for the Best of 2017. We use it.
It reads a series of high-level (software) models of your test
sequence, and then automatically generates detailed C test code
based on the combination of scenarios. For example, parallel
sequences on different processors and serial sequence on a
processor.
- Perspec provides easy access for creating functional coverage.
- It is very simple to set default values and soft/hard
constraints for constraint solving.
- Perspec also has ARM Libraries which are easy to use.
Could be improved: Sometimes there are issues with synchronization
between different processes which is hard to debug.
Overall, Perspec saves us a lot of time when creating complex parallel
scenarios. It's easy to generate the stimulus.
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We evaluated Cadence Perspec recently.
We are looking at it to help us generate system level tests of SOC chips
efficiently. The tests it generates are more complex than we can create
manually.
We'll start our 2nd round eval shortly and look more deeply at its
capabilities.
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Looking at Cadence Perspec for now.
We're looking at how to optimize verification reuse from IP to SOC
for new functions, to help us cope with developing more products in
shorter timeframes.
- from SoC to SoC (for derivatives)
- from verification to validation (for silicon feedback)
The portable stimulus initiative looks very attractive to us as a way
to model test sequences at a high level of abstraction and ensure
reusability across activities: architecture, design, verification, and
validation.
To try it out, we selected Perspec from Cadence. Perspec hits all
aspects of the flow we are looking at, and Cadence is active in the
standardization process.
We successfully completed our first step with Perspec -- covering
independent IP verification and SOC verification sequence randomization.
Our next step will focus on the sharing of the tests across activities,
from IP to SOC, and from the first SOC to the next one. We want to
see whether or not we can get any savings by reusing abstracted tests.
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Cadence Perspec System Verifier w/ Portable Stimulus
Perspec is a niche solution that facilitates quick validation
convergence at a SOC level.
It has lots of promise for scaling across various validation platforms
and for significant reuse across different end-user requirements.
Perspec leverages the rich Specman 'e' content, to capture/speed up the
overall SOC validation. It can be quickly integrated into any
validation stream for different usage perspectives, e.g. the end-user,
architect, model developer, etc.
I found it very useful for writing some of the complex/random SOC usage
scenarios in a very easy-to-read/implement fashion.
This methodology is now part of our SOC validation and we've gotten
significant benefit from it.
All tools have limitations including Perspec. We've requested
enhancements from Cadence and are looking for quick support to improve
the validation efficiency.
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Cadence Perspec
Perspec offers us a good environment to do SoC level verification, and
it provides an abstraction method to ease testcase development.
Although it is new, and needs more features to be added, it has already
provided us with some powerful methods to support our verification work.
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Cadence Perspec automates test case writing by generating use case
oriented C and SystemVerilog codes. It is mainly intended for SOC level
testing, but can also be used at the subsystem and IP level.
Based on our experience:
- Perspec defines a standardized and uniform structure for SOC
test cases.
- Perspec generates pseudo-random test cases
- Definite overhead in developing the SLN model -- an additional
10-15% of total DV effort. But is one time only.
- A granular approach to SLN modelling can adversely impact
Perspec performance.
- It's finicky. The smooth integration of different Perspec
SLN models requires a pre-established and consistent
methodology for model development.
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Cadence Perspec
PS is a very helpful in SOC verification -- you can repeatedly use
many testcases/stimuli in different scenarios. So far, Perspec
testcase re-use and maintenance only requires minimum effort.
(Otherwise it would be an annoying overhead for the entire SOC team.)
The pain. During my initial Perspec ramp up, I spent most of my
time learning the SLN syntax and debugging the test generation,
which I didn't like. I would rather spend the time creating new
test scenarios and exposing potential design bugs.
Following ramp-up, fine-tuning certain stimulus to adapt to a
specific use case wasn't always straight-forward.
The payoff. Once I developed the Perspec setup, it didn't take me
long to maintain it. I would say it took an equal amount of time
compared to the traditional way of maintaining stimulus.
However, when you hand over your Perspec setup to the next engineer,
it will take them extra time and effort to learn it.
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Our verification team evaluated Cadence Perspec. We concluded that:
- Perspec can generate automatically tests in a shorter time
- It saves a lot of manual effort.
We use Perspec on ARM-based designs using Cadence's pre-made libraries.
To use it on our other designs, we would need to create and maintain a
model, and we currently we do not have resources for that.
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Cadence Perspec
Our key milestone these days.
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Not a big fan of 'e'. But if it pays off with Perspec, I might give
it a try.
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SLN is a pain in the ass.
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Boss says PSS is our tech risk for the year. Perspec? Breker?
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All Cadence here. We've already had 3 visits from the Perspec
pre-sales support guys on this.
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Cadence Prospect.
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Prespec Specman e
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We don't know exactly how portable Cadence R&D will make its
DSL migration.
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Biggest lie?
Our Cadence sales guy talks to us like Donald Trump.
"Don't worry. The new Perspec will 100% comply with
PSS. It's going to be great! It's going to be the
greatest PSS ever!"
We're expecting for him to next say: "... and Breker is
going to pay for the Perspec DSL migration, too!"
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1. Mentor Veloce
2. Cadence Perspec
3. Real Intent lint & CDC
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Perspec
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Our SW guys like C, so they're cheering for Breker.
Our HW guys like e, so they're cheering for Perspec.
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Breker and Perspec
(Actually, Breker or Perspec.)
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Looking at PSS. Perspec, Breker, possibly InFact. We're
a Cadence house, so Perspec gets 1st consideration.
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Related Articles
Cadence Perspec wins #1 in #1 "Best of 2017" with Portable Stimulus
Breker TrekSoC takes #2 in #1 "Best of 2017" with Portable Stimulus
Mentor InFact was pretty much an early No Show in the PSS tool wars
Spies hint that Synopsys is making a PSS tool, but it wasn't at DAC
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