( ESNUG 589 Item 05 ) --------------------------------------------- [04/22/21]
Subject: How I convinced my boss' bosses to try Cadence 3D-IC vs. ANSS 3D-IC
Anirudh: I see talking to our customers and big partners they want
thermal analysis for 3D-IC and extraction.
With CDNS Celsius and thermal analysis, with CDNS Integrand EMX for
extraction, we can provide a pretty good solution.
This is very exciting. 3D-IC is going to be a huge thing for the
industry. Because if you look at the last 5 to 10 years, most of
the Moore's law is driven by integration -- putting more things on
the chip. The CPU runs at 3 or 4 GHz -- but instead of 1 CPU,
you have 8 CPUs.
If you look at the last 5 to 10 years, Moore's Law is driven more by
integration than transistor scaling. If you look at 3D-IC and having
multiple chips on a package, it's a natural extension of that
integration to build really big systems. So, we want to make sure
we have the best tools and technologies and IPs to support this next
wave of industry innovation.
- from Anirudh's Clarity/AWR/EMX end run around ANSS/SNPS in 3D IC
From: [ Brian from Family Guy ]
I need to be anonymous here.
It's OK to tell folks that for the past 15 years I've designed chips that go
into major consumer and leave it at that, OK?
Without bashing any specific tools, we've been finding "traditional" 3D-IC
design and analysis methodologies are breaking down. (Our 3D-IC guys aren't
concerned about individual tools as much as having a happy working flow.)
OUR MIX-N-MATCH 3D-IC FLOW IS BREAKING DOWN
Currently our work flows covers a wide range of design tools; we have used
tools from Synopsys, Mentor, Ansys, and Cadence. Below is a list of typical
tools used to design and simulate advance packaged products.
IC Design Tools:
Synopsys - ICC2, DC, PT, Star-RC, ICV, Hspice, Custom Compiler
Cadence - Innovus, Tempus, Quantus, Voltus, Pegasus, Spectre
Mentor - Calibre, Eldo
Ansys - RedHawk
PCB Design Tools:
Cadence - Allegro, Sigrity, AWR, Orbit-IO
Mentor - Xpedition
Systems Simulation Tools:
Ansys - HFSS, SiWave, IcePak
Cadence - Clarity, Celsius, Sigrity
We're seeing fundamental problems with our present day 3DIC projects in the
ability to analyze Signal Integrity (SI), Power Integrity (PI), and thermal
profile of the entire 3DIC system -- which is made of multiple fabrics --
board, package, interposers, stacked ICs with thru-silicon vias (TSV) or
thru-die vias (TDVs).
For example, while 3D-ICs have enabled much faster data rates between HBMs
and SoC die, it has exacerbated the SI, PI, and thermal problems -- which
makes it even more critical to analyze accurately from a cross fabric
point of view -- rather than simplistic models of its individual components
in silos. (In our 3D-IC project, massive switching busses create havoc for
or SI and PWR/GND networks.)
We have a high speed 128 signal bus with power and ground running through a
large interposer connecting stack of HBMs and SoC die; that extracts out to
800+ s-paramater ports. Our problems are:
1. Find an easy way to build up this 3D-IC topology across
the different fabrics -- and not have to worry about whether
signal ports are mapped and connected properly.
2. The SI/PI challenge is to be able to extract this bus as a whole
(not pieces of it or use cut and stitch methods) with high
accuracy. This requires a true 3D EM solver to accurate extract
high speed signal nets/busses across the multi-fabric boundaries.
2.5D solvers are not accurate enough.
3. Once we have extracted the bus we need a seamless way to simulate
and optimize it to meet our margins for *simultaneously* switching
noise, jitter, power noise etc, of course at high accuracy.
We are constantly looking to rid our work flows of possible sources for
inaccurate analysis -- and our biggest source of errors is moving design
data from one tool fabric to another tool fabric.
---- ---- ---- ---- ---- ---- ----
For my direct mgmt, I created this table showing how each EDA vendor covers
some part of the fabrics of a commercial 3D-IC flow.
It's surprising how close Ansys and Cadence are in tool fabric coverage
needed for 3D-IC design, implementation, optimization, and analysis.
Synopsys is missing PCB, IC PWR signoff, and FEA and CFD solvers for
systems simulation. Ansys doesn't have IC or PCB design tool, but leads
in systems simulation. Cadence is making a play in systems simulation,
so their PCB and IC tools gives them to potential to be a contender. But
their systems analysis solvers need to be robust. accurate, and reliable.
Based on above comparison we decided to look more closely at using the
new Clarity 3D solver vs Ansys HFSS.
---- ---- ---- ---- ---- ---- ----
TESTING CLARITY VS. HFSS ON A PRIOR 3D-IC DESIGN PROJECT
Our trial 3D-IC benchmark was a multi-die interposer design that we had
produced last year in 2020. It had the following details:
- 2 die: SoC + HBM memory
- 4 RDL layer with TSV
- 48 signal nets
- Total size 0.28mm x 5.2mm
- 102 ports (98 signal + 4 pwr)
- 15+ M elements
- 2um / 2um signal width/spacing
- Simulation frequency: DC to ~10 GHz
- Solution frequency: 2.5 GHz
We chose this because of issues with these types of designs are the massive
high speed busses and optimizing them to interface with other die and
communication protocols, like high speed SERDES.
Set-up was not difficult since Clarity already reads standard input formats
like GDS2 from Innovus, .mcm, .sip, spd, and .brd from Allegro. Below are
the results compared to HFSS.
Our real life measured accuracy matched our simulation data from both tools.
---- ---- ---- ---- ---- ---- ----
USING CLARITY ON OUR NEW 3D-IC PROJECT
After confirming the accuracy (along with the speed) of the Clarity and
Sigrity SI combo, we felt confident to use Clarity on our larger present
day production design project -- a 3D-IC SoC + HBM interposer design.
- 2 die: SoC + HBM memory
- 4 RDL layer with TSV
- 128 channel signal nets
- Total size 0.52mm x 9.4mm
- 800+ ports (2PWR, 2GND)
- ~40 M elements
- 2um / 2um signal width/spacing
- Simulation frequency: DC to ~10 GHz
- Solution frequency: 2.5 GHz
Because of its bus operating speed, there was potential for significant
x-talk issues. We also wanted to eliminate any potential interconnect
issues -- which is why the Clarity / Sigrity combo is sexy to us.
Yes, HFSS couldn't solve our present day 3D-IC design. But we're not stupid.
We know we could use HFSS if we cut our larger design into smaller analyzable
parts -- but that defeats the benchmark!
We cut with Ansys; Clarity lets us run without cutting. That's a big plus
for us to use Clarity. HFSS was running out of memory because it's limited
to one massive 1 TB server. Clarity has two advantages: it runs across lots
of small servers networked together -- plus it can extract signals across the
entire fabric, using distributed processing that only takes peak 8 GB per CPU
for 128 CPUs.
Clarity won because of super compact data models and distributed processing;
meaning we don't have to cut up our 3D-IC designs (like we had to do with
HFSS) to get them analyzed.
Cutting designs for analysis is murder because it introduces discontinuities
(and therefore errors and inaccuracies) in our analysis.
---- ---- ---- ---- ---- ---- ----
MOVING DATA ACROSS FABRICS IS ALSO MURDER
You think cutting designs for HFSS analysis is bad? Try moving data across
your 3D-IC fabrics with different solvers and different data structures!
Let's say we run into a x-talk issue in our 3D-IC project using Ansys HFSS,
Synopsys ICC2, and Mentor Xpedition. It's a big headache to move data
Ansys HFSS <--> Synopsys ICC2 <--> Mentor Xpedition
back and forth between 3 different tools from 3 different vendors with 4 or
5 different data formats (that are only "iffy" correlated to each other
because it's always "the other tool is messing up. Contact their support.")
Also info gets messed up and/or mistranslated -- so it requires a lot of
engineer handholding and hand tweaking every step along the way.
What Cadence is working on (that we like) is an all-CDNS 3D-IC flow
Clarity <--> Sigrity <--> Innovus <--> Allegro
where we fix 3D-IC x-talk issues across multiple fabrics that are *cleanly*
translated and *cleanly* correlated to each other. 4 different tools from
1 vendor who owns the data structures and correlation between their tools.
Right now the segments of this multi-fabric CDNS flow that we've seen are
only package and PCB related. Specifically, With Clarity and Sigrity we
were able to make optimizations that we could implement directly in Allegro
to fix x-talk and interconnect issues.
My CDNS support guy says they're close to getting Innovus added in.
---- ---- ---- ---- ---- ---- ----
WE REALLY WANT THERMAL NEXT
Digital IC PnR is nice, but Thermal is a big headache for our 3D-IC systems.
Heat dissipation is an issue for FinFETs die due to it's 3D structure. And
stacked dies poses an even greater heat dissipation problem. Cadence needs
computational fluid dynamics (CFD) solvers to address this.
We have been using Ansys (Icepak) and Mentor (FloTherm) tools. The problem
is we've always lived with tools that model the components like black-boxes
(very simplified) -- which is not the most accurate view to analyze thermal
dissipation thru the stacked devices. You only get a simple ambient
temperatures for the ICs at the boundary, but no visibility of the thermal
gradients inside the chips.
Without an integrated finite element analysis (FEA+CFD) solver these tools
lack ability to build thermal network inside ICs. The Cadence sales folks
tell me their Celsius-plus-Voltus thermal combo for 3D-ICs is "the only tools
that gives user thermal gradient of your entire 3D-IC system." Claims you
can see thermals inside individual components from chassis to board to
package to ICs to gates to probe temperature.
We already use Voltus. We are hopeful their adding Celsius to the mix will
allow us to have visibility of the thermal gradients across the entire 3D
fabric. It'll let us avoid overdesigning and to optimize for PPA thru-out
the system.
---- ---- ---- ---- ---- ---- ----
HOW I CONVINCED MY BOSS' BOSSES TO MAKE THIS CHANGE
Hi, John,
Here's the "fun" part where I have to be triple sure I personally remain
anonymous.
After I did our analysis of Clarity vs. HFSS, my boss' bosses asked me to
brief them on the technical reasons why we'd leave our current 3 vendor
flow (ANSS/SNPS/MENT that works) for a new 1 vendor flow (CDNS that's risky)
for 3D-IC design.
My boss reminded me that although they're our superiors, my boss' bosses
do not have the technical depth that we do (i.e. "make your technical talk
have simple explainations that even your grandmother would understand.")
Here's the concepts of the slides I developed for my boss' bosses.
Europe 1970 --- the state of 3D-IC design NOW
Europe 1970 EDA for 3D-IC in 2021
37 countries 4 major vendors
37 currencies 9 different tool types
24 official languages 12 data structures
200 local languages 30+? file types
A trip from Portugal to Moscow means crossing 6 borders and 6 different sets
of Customs Guards and 6 currency exchanges and 6 unique local languages.
This is just like a 3D-IC project going from IC die all the way to PCB means
going through 9 different EDA tool types from at least 3 different vendors
with 12 different data structures (that we must translate) and 30+ file types
encountered along the way.
United States -- what Cadence is promising for 3D-IC
USA 1990 Cadence for 3D-IC in 2022?
1 country 1 major vendor
1 currency 9 different tool types
2 official languages 12 data structures
165 local languages 30+? file types
A trip from New York City to Los Angeles means crossing NO borders with
NO Customs Guards and NO currency exchanges and 2 local languages.
What Cadence is promising is our 3D-IC project going from IC die all the way
to PCB still means going through 9 different EDA tool types; but the tools
come from them so Cadence owns the 12 different data structures translation
problems and 30+ file types encountered along the way.
European Union 2021 -- what Cadence has now for 3D-IC
European Union 2021 Cadence for 3D-IC in 2021
27 as 1 + 10 countries 4 major vendors
1 + 10 currencies 9 different tool types
24 official languages 12 data structures
200 local languages 30+? file types
A trip from Portugal to Moscow means crossing 1 border and 1 set of Customs
Guards and 1 currency exchange -- despite 6 local languages.
What Cadence has now (April 2021) is Clarity/Sigrity/Allegro (3 of the 9 tool
types required to complete our 3D-IC project) all tightly integrated. CDNS
owns all the data translation problems between these 3 fabric stages and will
manage all the fabric boundry conditions found along those 3 stages.
This means our engineers still have to hand guide all the tools and manage
all data translation problems for the remaining 6 3D-IC fabric stages.
---- ---- ---- ---- ---- ---- ----
I then gave my boss' bosses an example why these 3D-IC stages are murder.
IC switching <---> EM/SI/X-talk <---> thermal <---> fluid dynamics
In general, the hotter a chip gets, worse x-talk happens. Bad fluid dynamics
means a hotter package. More chip switching means more heat needs to be
drawn away. How a chip is placed impacts air flow. Different packages cool
differently. More x-talk means lower chip & board performance. Etc.
In short, the different 3D-IC fabric stages mess with each other a lot!
3D-IC design is like squeezing a balloon. We want to see how much we can
crush one stage of the fabric to have it not mess up some other fabric stage.
Right now we do this with 9 different tool types and 12 data structures.
We run tool "A". Feed those results into tool "B". Feed those results into
tool "C". Find a problem. Have to go back to tool "B". Then a 2nd problem
comes up -- that we have to feed to both tool "A" and tool "C". But then
we have to plod through tool "D", tool "E", all the way to tool "I" in this
same back-and-forth nightmare fashion to get our 3D-IC done!
Tool "A"
|
Tool "B"
|
Tool "C"
|
Tool "D"
|
Tool "E"
|
Tool "F"
|
Tool "G"
|
Tool "H"
|
Tool "I"
|
These are all separate runs with different solvers whose results we must
translate for the next stage! This introduces discontinuites and boundry
problems between each fabric stage. It's a nightmare.
Why we are suggesting a possible switch to Cadence is we'll have one vendor
who owns all these messy fabric stages -- plus own the data translation
issues between these 9 different fabric stages. That's assuming this new
Cadence flow passes an extensive evaluation by our engineers, of course.
---- ---- ---- ---- ---- ---- ----
CONCLUSION
Not much has happen in 3D-IC tool breakthroughs for the past 20 years. We
can confirm their Allegro/Sigrity/Clarity combo is integrated and works.
We look forward to seeing if their Voltus/Celsius combo works and how they
plan to integrate into one larger 3D-IC fabric flow.
Anirudh buying Numeca to fill in his CFD hole is good news, too. Their CFD
solvers are good at turbomachinery and I think automotive.
- [ Brian from Family Guy ]
---- ---- ---- ---- ---- ---- ----
Related Articles:
Anirudh's Clarity/AWR/EMX end run around ANSS/SNPS in 3D IC
6 CDNS Clarity vs. ANSS HFSS user benchmarks is Best of 2019 #4
And now a 7th hands-on CDNS Clarity vs. ANSS HFSS user benchmark
Anirudh on CDNS Clarity vs. Ansys HFSS; Green Hills, Black Duck
"It's results, NOT algorithms, dummy!"; Clarity vs. HFSS benchmark
56% of users doubt Anirudh's secret "new" Clarity matrix solver
Cooley's open letter to ANSS Ajei Gopal to join Troublemaker Panel
Ansys CEO Ajei Gopal cleverly acquires Helic as #8 "Best of 2018"
SCOOP! -- Anirudh goes total war on Ansys mothership at CDNlive'19!
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