( ESNUG 584 Item 2 ) -------------------------------------------- [06/15/18]
Subject: SCOOP -- Prakash to launch gate-level CDC linter and CDC EC tools
OOPS: And I laughed when I asked Prakash what his new "true" CDC linter tool
was named. "... it's the first tool in our new Verix family of products..."
A full 17 years ago, Real Intent had launched at DAC'00 its "new" Verix
"... claiming a breakthrough approach to logic verification with
its Intent-Driven Verification methodology, startup Real Intent
this week will unveil Verix, its first tool offering. ... it reads
Verilog RTL code, deciphers the designer's intent and automatically
checks for eight types of violations..."
- from Richard Goering, EE Times (05/08/2000)
Prakash is trying to pull a Back To The Future on us -- by trying to reuse
the name of his very, very, veeeeery first product from 17 years ago -- and
then rebranding it as his "new" "true" Verix CDC linter of 2017. D'oh!
- from Real Intent caught launching "new" linter under old name
From: [ John Cooley of DeepChip.com ]
Last year right before DAC'17 in Austin, I took great pleasure in catching
Prakash Narain of Real Intent trying to recycle his 18 year old "Verix"
product line name pretending it was "new" when he launched at DAC'17 his
true multi-mode CDC linter that he named "Verix CDC".
Remembering this, I called Prakash on Wednesday:
Cooley: "Hey, Prakash, so what are you announcing for this San
Francisco DAC? A 'new' PC operating system that you'll
try to call Real Intent Windows???"
Prakash: "I'm working 16 hour days now. My life is hell. Did you
just call to harass me? Don't you have better things to
do with your time?"
[ Prakash paused. ]
Prakash: "... we are launching two new tools you don't know about
at this DAC. One called PhyCDC which does CDC at the
gate netlist level ..."
I yawned. The datasheets for the Questa CDC and Spyglass CDC tools already
claim gate-level CDC -- and Real Intent already does gate-level CDC analysis
in the past with its Meridian tool. Are you trying to re-announce something
old as something new *again*, Prakash?
Prakash: "You won't let me finish, John! Let me finish! ... inside
our new PhyCDC there is also a new CDC-equivalence checker.
This is something totally new in EDA. Nobody else does
CDC-EC. I am very proud of this."
OK, since this is two new tools, to parse out what they were doing, I swung
back to his first tool, PhyCDC. Why do I even need a netlist CDC tool? Are
you just making up niches to sell tools in? Spyglass and Questa and even
your own Meridian have all done RTL CDC for years now.
Prakash: "Spyglass CDC and Questa CDC work on your source RTL. My
new PhyCDC does netlist level CDC because there's a whole
class of post-synthesis, post-scan/JTAG/BIST insertion,
post-power optimization/clock-gating level netlist type
bugs that you need to check CDC for.
These post-RTL stages of a design create new CDC paths,
new CDC control signals, and new CDC data-path signals
that can create messy clock glitches. Over the last
3 years, I know of 3 chip failures at some very big chip
design houses because of these post-RTL problems."
Cooley: "I've not done it myself, but I've been told you can use
both Spyglass and Questa at the gate/netlist level.
Doesn't this cancel out any need for your PhyCDC?"
Prakash: "Using Spyglass or Questa RTL analysis for gate-level CDC is
not practical since:
1.) your design and file sizes can be huge, and these
tools can't process them in a reasonable runtime;
2.) your RTL names get changed from all those post-RTL
stages making debug very difficult, and the netlist
doesn't directly match the RTL because of synthesis
optimizations for timing/power/test.
You can use an RTL tool like Spyglass CDC or Questa CDC
at the gate-level but the manual effort for setup,
analysis and debug can be double that of RTL CDC signoff."
INCREMENTAL IS FAST: Verix PhyCDC, according to Prakash, is "designed to
tackle all of these difficulties by making netlist CDC analysis incremental"
and hence "it's much, much faster."
(Basically he cheats by using info from his earlier Verix RTL CDC runs to
speed up his Verix netlist PhyCDC runs. He sneaks off his RTL database
over to his PhyCDC netlist tool to munch on.)
---- ---- ---- ---- ---- ---- ----
PRAKASH'S NEW CDC EC TOOL: When I then moved onto his new CDC-equivalence
checker where he had earlier said "Nobody else does CDC-EC. I am very proud
of this.", I got a bit confused what his big breakthrough claim was/is. The
best summary I got from his was:
1. PhyCDC maps your RTL constraints (SDC) to your gate-level netlist,
2. then it identifies the CDC crossings paths in your netlist,
3. then it runs CDC equivalence checking (CDC EC) to find whether any
of your netlist CDC paths have gone through transformations that
invalidate earlier RTL CDC sign-off.
"Our CDC-EC is waiver-free. It reuses your earlier RTL waivers correctly",
Prakash added.
WHAT IT'S NOT: From a *lot* back and forth with Prakash, all I can say on
his "new" (unnamed) CDC equivalence checker is what it's NOT.
- It's nothing like the normal Formal tools like JasperGold,
OneSpin, Questa Formal, VC Formal. It doesn't use assertions
nor anything like assertions.
- It's nothing like logical equivalence checkers like Conformal
nor Formality. It's not looking at functional equivalency between
an RTL version of a design and a netlist version of a design.
- It's not being sold separately. It's part of Verix PhyCDC.
- It's not static analysis tool like PrimeTime nor Genus.
- It DOES two function: some sort of formal timing analysis
to find CDC timing problems *plus* to find weird asynch CDC
crossings that cause glitches.
After that, Prakash said he'll have a later whitepaper explaining all this
because "it would take all day to explain this to you on the phone, John."
---- ---- ---- ---- ---- ---- ----
HARD NUMBERS & SECRET SAUCE: Anyway, Prakash claimed "on a 190 million gate
customer netlist, my new Verix PhyCDC tool analyzed 921,810 CDC crossing
end-points in 4 hours on a single CPU to identify 454 problem end-points
requiring further debug. The customer really liked this quick turnaround."
Our phone call concluded with Prakash claiming his Verix PhyCDC has a
"unique" CDC-glitch analysis for full chip netlist. His glitch analysis
manages the size complexity and design partitioning for parallel analysis
across multiple CPUs. Says it does static analysis both fast structural,
along with deep formal to partition the CDC analysis problem. "It's part
of our secret sauce."
- John Cooley
DeepChip.com Holliston, MA
---- ---- ---- ---- ---- ---- ----
Related Articles
Prakash leaks SimFix X-pessimism tool replying to Dan Joyce GLS
Real Intent trounces Synopsys Atrenta as the #6 "Best of" for 2017
Prakash and Anirudh spar on Real Intent Linting vs. Jasper Formal
Real Intent caught launching a "true" CDC linter under old name
Join
Index
Next->Item
|
|
