( ESNUG 573 Item 3 ) -------------------------------------------- [06/09/17]
Subject: And the variation part of Amit's 263 engineer SPICE survey...
Variation easily topped the list for the highest custom IC impact over the
next two years -- picked by the majority -- with SPICE simulation a close
second. This is because FinFETs, FD-SOI, and low power design are causing
their designs to behave unpredictably, causing mismatches between their
SPICE simulation and final silicon.
- 263 engineers surveyed on their Custom IC design types & nodes
From: [ Amit Gupta of Solido Design]
Hi, John,
And as I do every year, I asked these 263 engineers how variation impacts
their chip design.
The top 3 drivers for variation-aware tools continue to be to avoid respins
and to reduce overdesign (for better overall power/performance/area) and now
newly moving up to 43%, to reduce underdesign (for better yield).
All about margin: There is way less margin at the smaller (under 28nm) nodes
and low power -- it's the knife's edge for overdesigning vs. underdesigning.
More design being done at advanced process nodes, plus the difficulties of
getting high yield there (due to variation effects), is driving this.
Other drivers: avoiding project delays, lower voltage design, fewer SPICE
simulations, and fewer engineering resources all remained fairly stable.
---- ---- ---- ---- ---- ---- ----
VARIATION NOW DELAYS ~60% OF CHIP DESIGNS
More Chips In Danger: Chip design delays caused by variation has grown from
52% to 59% in the past year. This hurts, as time-to-market is critical.
All these project delays not only increase your engineering design costs,
they also reduce your final overall sales in the end market.
Combine this fact with our earlier 2015 survey, where the respondents had
warned that 55nm on down is where variation-aware design becomes important
and it becomes dangerous -- because this year (2017) this survey found in
ESNUG 573 #1 that now 50% of chips are now at or below 35nm!!!
Or said another way, now 64% of chip designs are in that sub-55nm variation
danger zone.
---- ---- ---- ---- ---- ---- ----
YOU CAN'T IGNORE VARIATION
Variation-aware design is now a must. With FinFET and FD-SOI devices, and
low power designs -- even with planar devices -- designers risk overdesign
(not getting the best from your transistor) and underdesign (taking a yield
hit), or worse a respin, on a multi-million dollar production run.
Variation-aware design is now a REQUIRED step in the signoff flow.
- Amit Gupta
Solido DA San Jose, CA
---- ---- ---- ---- ---- ---- ----
Related Articles:
263 engineers surveyed on their Custom IC design types & nodes
263 engineers on their present day SPICE use and SPICE leaders
And the variation part of Amit's 263 engineer SPICE survey...
Amit added 263 engineers on Library Characterization this year!
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