( ESNUG 573 Item 1 ) -------------------------------------------- [06/09/17]
Subject: 263 engineers surveyed on their Custom IC design types & nodes
This all about lock-in. This asked the question of "if you own the SPICE
environment, how much of the SPICE simulator market will you also own?"
This data says 41% of users will choose their SPICE simulator pretty much
with less regard to speed/performance/accuracy/capacity/cost, just because
it runs tightly with their commercial environment.
- Cadence is trying to use Virtuoso ADE and Cadence Altos/Liberate
to lock-in Spectre license sales.
- Synopsys is trying to use Custom Compiler and Magma SiliconSmart
to also do this -- but it's the SiliconSmart popularity that is
driving HSPICE/FineSim sales, the new Custom Compiler is too new
to impact this.
Conversely, the popularity of Mentor's BDA AFS could be used to lock-in the
Mentor BDA ACE environment -- thus displacing Cadence or Synopsys.
- 246 engineers surveyed on general SPICE use & SPICE requirements
From: [ Amit Gupta of Solido Design]
Hi, John,
Here's my third annual pre-DAC external survey sponsored by Solido.
We now have 3 years of data to do even better analytics on trends. Our
prior custom IC design surveys were: 2016 and 2015.
This year, 263 designers and engineering managers responded to our survey.
Below is what they reported about their general SPICE use and SPICE
requirements.
Where the questions are the same, I compare them to results from the prior
year(s).
---- ---- ---- ---- ---- ---- ----
SPICE USE & CUSTOM IC DESIGN BY TYPES
Analog/Mixed-Signal is still a key part of differentiating chips, so it is
not a surprise that AMS stayed strong at 64 percent.
Over the last two years, we've noticed an 8 percent increase in RF design
-- matched by a 9 percent decrease in both full custom digital and standard
cell design.
The result is that survey respondents say their teams are now designing
equally with standard cell and RF design types. This is from an increased
use of RF in mobile, IoT, and automotive chips.
The drop in Full Custom Digital and Standard Cell design is probably due to
more IP use. "Why design it, if you can buy it?"
---- ---- ---- ---- ---- ---- ----
SPICE USE & CUSTOM IC DESIGN BY PROCESS NODES
We asked again at which process node(s) they are designing. Below is the
shift we observed from 2016 to 2017.
Q: "At what nm process node(s) are you currently designing?"
35nm is the new 55nm: Last year, the majority were designing at 55nm and
below -- this year, the majority are designing at 35nm and below.
Roughly ~20% of custom IC design is still done at the older 90+nm nodes.
This is for IC's being designed for catalog parts, industrial controllers,
etc. -- that don't need the PPA of leading edge nodes.
Also, many companies stay on mature nodes just because they are cheaper.
Node jumpers: There were declines in 60/65/90nm and the 40/45/55nm designs,
and corresponding increases in 28/32/35nm and 7/10nm designs. This is
being driven by the recent uptick of designs in high growth segments like
networking/cloud, automotive, mobile/5G, and IoT SoCs.
To FinFET or not FinFET: Companies are deciding whether to move down to
the sub-16nm FinFET transistor nodes -- or to stay at the larger, cheaper
planar nodes of 28nm and above. The decision is driven by PPA vs cost.
More Node Flavors: Foundries like TSMC, Samsung, GlobalFoundries are also
creating derivatives of their process nodes (e.g. TSMC 40LP is TSMC's 40nm
low power) to appeal to more customers. GlobalFoundries is also investing
in a new 12nm FD-SOI node, a cheaper sub-16nm alternative to the
TSMC and Samsung 10/7nm FinFET nodes.
---- ---- ---- ---- ---- ---- ----
VARIATION & SIMULATION TO HAVE HIGHEST DESIGN IMPACT
To better understand design teams' priorities, we also asked:
Q: "Which *3* areas of Custom IC design do you expect to have
the most impact on your organization over the next 2 years?"
Variation easily topped the list for the highest custom IC impact over the
next two years -- picked by the majority -- with SPICE simulation a close
second. This is because FinFETs, FD-SOI, and low power design are causing
their designs to behave unpredictably, causing mismatches between their
SPICE simulation and final silicon.
- Amit Gupta
Solido DA San Jose, CA
---- ---- ---- ---- ---- ---- ----
Related Articles:
263 engineers surveyed on their Custom IC design types & nodes
263 engineers on their present day SPICE use and SPICE leaders
And the variation part of Amit's 263 engineer SPICE survey...
Amit added 263 engineers on Library Characterization this year!
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