( ESNUG 340 Item 5 ) --------------------------------------------- [1/19/00]
Subject: ( ESNUG 338 #8 339 #3 ) How We Search For Un-Initialized FF's
> The main point I was trying to make is that spending time crafting X's in
> the RTL is non-productive and error prone. In addition, as Cummings
> previously stated, it violates faithful semantics between the RTL and
> gate level simulation.
>
> - Harry Foster
> Hewlett-Packard Computer Technology Lab
From: Greg Brookshire <GBrookshire@raleighttech.com>
John,
Our approach to finding un-initialized flops on our last design was to use
several scripts to find flops without resets. Our methodology required that
all flops on the system clock be reset by a global reset signal that was
synchronized to the system clock. We drilled this into the heads of our
coders (mostly co-ops with Verilog experience) so we didn't have much of a
problem with flops that were not reset, but to be sure we used the following
two filters to find flops without a reset.
For our first non-reset-flop filter we used a script that reads a Verilog
file into DC then uses Perl to parse the register inference results. The
Perl script reports statistics such as the number of flops and latches with
and without resets. This was a quick way for our coders to make sure their
code was synthesizeable and to make sure they inferred the correct flops,
with reset, and no latches.
For a final filter we then used DC to generate two list of flops in the
design. The first was the list of all flops on the system clock. The
second was the list of all flops on the system reset. By comparing the two
lists in Perl, we found flops that were not reset. When we later ran gate
level sims we had very few problems with un-initialized flops.
- Greg Brookshire
Raleigh Technology Corp Cary, NC
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