( ESNUG 339 Item 3 ) --------------------------------------------- [1/13/00]
Subject: ( ESNUG 337 #3 338 #8 ) X's, Optimism, Resets, & Verilog Case
> Here are two coding examples that attempt to overcome Verilog optimism w/
> respect to propagation of X's through case statements in simulation. We
> were burned by not finding a reset problem until late in the schedule
> when our gate level simulation propagated the X correctly.
>
> These case statements are easier to read and use than Harry's examples in
> ESNUG 337 #3.
>
> reg [1:0] d, e;
> ...
> begin
> case (d)
> 2'b00: e = 2'b01;
> 2'b01: e = 2'b11;
> 2'b10: e = 2'b10;
> default:
> begin
> // synopsys translate_off
> if ((|d[1:0]) === 1'bx))
> e = 2'bxx;
> else
> // synopsys translate_on
> e = 2'b00;
> end
> endcase
>
> Our design team is currently using this methodology to find more
> intialization problems earlier.
>
> - Lauren Carlson
> StarBridge Technologies, Inc. Marlboro, MA
From: "Harry Foster" <foster@rsn.hp.com>
Hi John,
Concerning Lauren Carlson's reply to my letter, there's a problem with her
example as coded, which illustrates my original point on how difficult it
is to correctly craft X-state support into the RTL.
If d takes on either the value 2'b1x or 2'bx1, then the Reduction OR
operator (|d[1:0]) will result in a 1'b1 (not a 1'bx). Hence, the example
as coded will not propagate the X correctly. This example can be improved
by using the Reduction XOR operator (^d[1:0]), which will work correctly.
However, the problem still comes down to coverage "controllability vs.
observability" in the test suite. There's no guarantee that the
initialization error would be observable in later stages of logic for a
given stimulus. The main point I was trying to make is that spending time
crafting X's in the RTL is non-productive and error prone. In addition, as
Cummings previously stated, it violates faithful semantics between the RTL
and gate level simulation.
I believe the verification process is better served by:
(a) Eliminate X assignments in the RTL.
(b) Use faster RTL 2-state simulation with random 1 or 0 initialization
(as opposed to X-state initialization.)
(c) Use assertions to trap and halt simulation errors instead of
propagating the problem.
Hope this helps.
- Harry Foster
Hewlett-Packard Computer Technology Lab
---- ---- ---- ---- ---- ---- ----
From: "Glenn Poole" <gpoole@home.com>
John,
Lauren's example above is incorrect. If d is 2'b1x, (|d[1:0]) will give
a result of 1. You need to use the XOR operator "^" to make this work.
- Glenn Poole
Poole Design
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