( ESNUG 338 Item 8 ) --------------------------------------------- [12/3/99]

Subject: ( ESNUG 337 #3 )  X's, Optimism, Pessimism, Resets, & Verilog Case

> It is possible to code the RTL in a style which would intercept and
> process X-states more accurately, moderating both the pessimism and the
> optimism.  For example, our case statement could be modified to intercept
> X-states and propagate their affect on the result more accurately.
>
>                 reg [1:0] d, e;
>                 ...
>                 begin
>                    case (d)
>                      2'b00 : e = 2'b01;
>                      2'b0X : e = 2'bX1;
>                      2'b01 : e = 2'b11;
>                      2'bX0 : e = 2'bXX;
>                      2'bXX : e = 2'bXX;
>                      2'bX1 : e = 2'bXX;
>                      2'b10 : e = 2'b10;
>                      2'b1X : e = 2'bX0;
>                      2'b11 : e = 2'b00;
>                    endcase
>                  end
>
> This coding style quickly becomes unmanageable for all but the simplest
> examples and is prone to errors (incompleteness).  In addition, we are
> very quickly loosing the designer's clear functional intent to support an
> irritating consequence of RTL X-state simulation.
>
>     - Harry Foster
>       Hewlett-Packard Computer Technology Lab         Richardson, TX


From: Lauren Carlson <carlson@starbridgetech.com>

Hi, John,

Here are two coding examples that attempt to overcome Verilog optimism with
respect to propagation of X's through case statements in simulation.  We
were burned by not finding a reset problem until late in the schedule when
our gate level simulation propagated the X correctly.

These case statements are easier to read and use than Harry's examples in
.ESNUG 337 #3.

        reg [1:0] d, e;
        ...
        begin
         case (d)
           2'b00: e = 2'b01;
           2'b01: e = 2'b11;
           2'b10: e = 2'b10;
           default: 
             begin
	   // synopsys translate_off
               if ((|d[1:0]) === 1'bx))
                 e = 2'bxx;
               else
	   // synopsys translate_on
                 e = 2'b00;
             end
         endcase
    

For a fully specified case (no default statement) one could go as far as
coding it specifically to propagate the X's to find reset problems.

        reg [1:0] d, e;
        ...
            begin
              case (d)
                2'b00: e = 2'b01;
                2'b01: e = 2'b11;
                2'b10: e = 2'b10;
                2'b11: e = 2'b00;    
                // synopsys translate_off=09
              default: e = 2'bxx;
                // synopsys translate_on
              endcase
 

Our design team is currently using this methodology to find more
intialization problems earlier.

    - Lauren Carlson
      StarBridge Technologies, Inc.                Marlboro, MA



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