[ Editor's Note: You won't really understand this recount article
until you read http://www.deepchip.com/gadfly/gad121500.html first. ]
!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - /
_] [_ "The Physical Synthesis Tape-Out Census Recount"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
From: "Harry Foster" <foster@rsn.hp.com>
John,
I'd like to request a ballot recount. There's bound to be some dimpled
chads lurking in there somewhere...
- Harry Foster
Hewlett-Packard
No, this isn't a joke. It's been 5 days since I filed that tape-out census
and because it was such an exhausting project, I disappeared for the weekend
after I had published it. (Over the preceeding 7 days I was tracking ~150
tape-outs for Synopsys, Silicon Perspective, Cadence, Mentor, Magma,
Sapphire, and Monterey. It averaged out to ~200 e-mails and ~150 phone
calls during those 7 days.)
Now, on Monday afternoon I start getting the reader responses and discover
where I messed up in my census.
From: "Jon Stahl" <jstahl@avici.com>
Hi John,
I just read your "The Surprise Physical Synthesis Tape-Out Census" email
and must make three corrections:
#1 No Avici Chip Architect tape-out occurred
#2 Testing with the tool was done on three designs, two previously
completed with other tools, and one pre-tape out that I planned to
use Chip Architect to complete (the census states three tape-out's
were done).
#3 The designs the tool was tested on were 0.35um (1), and 0.25um (2).
The design I planned to complete with the tool was 0.25um (the census
states 0.18um for all three).
I ran into problems very late in the game with CA, and spent some time
working with Synopsys to try and resolve them, and finally gave up. I had
to use a combination of various other tools to get timing closed and the
design taped out. So my apologies to the community for those doing due
diligence on tools and only seeing my pre-tape-out good news report
without the later accompanying bad news. It took a while for the dust to
settle, and my job was to get the design out.
- Jon Stahl
Avici Systems N. Billerica, MA
OK, in my rush to get things done, I mistook Jon Stahl's ESNUG 338 letter as
talking about 3 Chip Architect tape-outs. No biggie. People make mistakes
and 99 percent of my census data came from users e-mailing me that they had
done tape-outs -- not me interpreting ESNUG posts -- so the overall data is
still good. Now
Synopsys "Chip Architect" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
10/99 100 K gates 100 Mhz Avici N. Billerica, MA 0.18 LSI
10/99 300 K insts 100 Avici N. Billerica, MA 0.18 LSI
10/99 750 K gates 100 Avici N. Billerica, MA 0.18 LSI
was to become
Synopsys "Chip Architect" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
* TBD TBD TBD TBD TBD TBD
* - no confirmed tape-outs of customers using only Chip Architect yet.
and Aart's new tape-out count wasn't going to be 50, but 47.
Then life got more complicated when I checked my voicemail and other e-mail.
First, I had a voicemail from a customer saying that I had violated my own
FAQ by not including those tape-outs reported on Friday. I checked and
found in my FAQ:
"Q: How will you report your findings?
A: On Wednesday of this week I'll give Richard Goering of EE Times the
preliminary list of known Synopsys physical synthesis tape-outs that
are known at that time. He says they'll be on http://www.EEdesign.com
when he gets them. On late Thursday or early Friday morning, I'll
have the final tally of Synopsys, Magma, Cadence PKS, Monterey, and
related tape-outs up on http://www.DeepChip.com and out on the ESNUG
mailing list."
In addition, another user e-mailed me saying the same thing. I thought
about it a bit and came to the conclusion that the spirit of this count was
to find tape-outs -- not to be sticklers to arbitrary rules. What's 24
hours going to change anyway?
So I dug through the e-mails and found I now had to add
Synopsys "Physical Compiler (PhysOpt)" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
08/00 80 K gates 25 Toppan Saitama, Japan 0.25
10/00 ~10 K insts 133 Mhz Broadcom Irvine, CA 0.18 TSMC
11/00 1 M gates 100 Toppan Saitama, Japan 0.18
11/00 400 K gates 100 Toppan Saitama, Japan 0.18
11/00 ~70 K insts 104 Mhz Moto Wireless Austin, TX 0.18
Synopsys "Chip Architect" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
??/00 450 K inst 125 Mhz Nexsi San Jose, CA 0.18 IBM
So now Aart would have 53 tape-outs -- exactly what he claimed. Oh, well.
And now Silicon Perspective would also get those 10 late Kawasaki tape-outs,
too.
Silicon Perspective "First Encounter" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
Q3/00 700 K gates 110 Mhz Kawasaki Japan 0.18
Q3/00 500 K gates 70 Kawasaki Japan 0.25
Q3/00 300 K gates 90 Kawasaki Japan 0.25
Q4/00 550 K gates 60 Kawasaki Japan 0.25
Q4/00 400 K gates 130 Kawasaki Japan 0.25
Q4/00 650 K gates 120 Kawasaki Japan 0.18
Q4/00 500 K gates 120 Kawasaki Japan 0.25
Q4/00 600 K gates 100 Kawasaki Japan 0.18
Q4/00 200 K gates 70 Kawasaki Japan 0.35
Q4/00 200 K gates 60 Kawasaki Japan 0.25
This made Silicon Perspective's tape-out count grow to an appropriate 43.
Then God decided to be even more of a practical joker when I found in that
Friday's e-mail a letter from the EDA head of ST Micro reporting:
Digital Storage Laguna Niguel, CA 3 tape-outs in 0.18 um
Micro Core Development Bristol, UK 1 tape-out in 0.25 um
Wireless Communications Grenoble, France 1 tape-out in 0.18 um
Consumer Broad Band Grenoble, France 3 tape-outs in 0.18 um
Graphics Products Div. Bristol, UK 1 tape-out in 0.18 um
Central R&D Crolles, France 2 tape-outs in 0.18 um
I've known a number of the EDA managers and designers at ST Micro for some
time now. I first met their head EDA guy a year ago at the 11/99 Synopsys
press event where Physical Compiler was first released. I had beers with
these ST guys at this year's DAC in LA. Over the seven days of my tape-out
count I was exchanging e-mails and phone calls with them because they easily
had 20+ PhysOpt tape-outs. This wasn't odd because Synopsys had given
ST Micro access to their physical synthesis 6 months before everyone else;
it makes sense that ST Micro would have a lot of tape-outs. They're actively
using 100 PhysOpt licenses. The problem was that on Thursday (my false
deadline), all I had gotten from ST was the ST Micro (Italy) data. Those 12
tape-outs were already included on my published tables. What I was getting
(above) was the ST Micro (France) data and the problem was that it *lacked*
the gate count & clock freq info I required.
Now, I was in a very bad position personally. Here's what I was facing:
If I Added These 11 ST Micro (France) Tape-outs:
- the EDA vendors losing the physical synthesis race (Cadence, Magma,
and Monterey) would cite this as more evidence that I was secretly
supporting Synopsys because I'm obviously an Evil Agent Provocateur
for Synopsys marketing.
- the pro-Cooley faction in Synopsys would say "See, I told you he's
OK" and the anti-Cooley faction in Synopsys would keep quiet for a
short while.
If I Excluded These 11 ST Micro (France) Tape-outs:
- the loser EDA vendors (Cadence, Magma, and Monterey) would have less
"evidence" that I was the stealth part of Synopsys marketing but they
would probably continue pushing the Cooley Is A Synopsys Corporate
Stooge story anyway to minimize their loses from this tape-out data.
- the anti-Cooley faction in Synopsys would howl "See! I told you that
Cooley is an asshole!" and the pro-Cooley faction in Synopsys would
have to work calming them down.
This was a classic Damned If You Do, Damned If You Don't situation for me.
So, like most Americans facing tough decisions, I deferred it to someone
else -- in this case, 5 someone elses -- an EDA Supreme Court of
Gary Smith, EDA Analyst, Dataquest
Richard Goering, EDA Editor, EE Times
Peggy Aycinena, Editor-in-Chief, ISD Magazine
Gale Morrison, Senior Editor, Electronic News
Gabe Moretti, EDA Editor, EDN Magazine
to decide this for me. I sent them each e-mails explaining my problem and
did follow-up phone calls. Gale's outgoing message said she was gone until
Jan. 2. Repeated attempts to reach Gary failed. I had to take Gary and
Gale off the court and add:
Erach Desai, EDA Analyst, Credit Suisse First Boston
Jay Vleeschhouwer, EDA Analyst, Merrill Lynch
in their places. No big problem here. All seven of these people know the
industry but weren't (mostly) in anyone's pocket. And Erach was even a bad
boy amongst his Wall St. peers for putting out estimates that countered
theirs. I gave each "justice" the facts via e-mail and I spoke with each
on the phone to answer their specific questions. I awaited their votes by
e-mail. Here's what I got:
From: Peggy Aycinena <paycinen@cmp.com>
This is technology, not politics. The facts are the facts, no matter when
they arrive. Include the statistics from all 'late' arrivals and re-issue
the results with explanation.
- Peggy Aycinena
Editor-in-Chief
ISD Magazine San Mateo, CA
---- ---- ---- ---- ---- ---- ----
From: "Gabe Moretti" <gabe@dimensional.com>
John,
You must amend your report to include these ST Micro (France) tape-outs.
- Gabe Moretti
EDA Editor
EDN Magazine Niwot, CA
---- ---- ---- ---- ---- ---- ----
From: "Jay Vleeschhouwer" <Jay_Vleeschhouwer@ml.com>
John,
Thanks for asking me to consider how you should proceed with the new data
that has come in for your survey. While as a rule I think it's best to be
consistent and rigorous about the gathering and analysis of this or any
other market data, I think that given the attention paid to this new
technology and the absence of a good or even any results compilation to
date, we should admit the reasonably complete new data you were provided
by ST Micro (France) in the good faith in which it seems to have been
offered.
Besides, I think we've had our share of recount halting this year.
- Jay Vleeschhouwer
Technical & Design Software Analyst
Merrill Lynch Technology Research Group New York, NY
---- ---- ---- ---- ---- ---- ----
From: "Richard Goering" <rgoering@cmp.com>
Yes, I would say add those 11 ST Micro tape-outs to your recount. It
sounds like they technically came in by the deadline. If information
is missing, maybe you can ask them to add it. As was the case in
Florida, every vote should count.
- Richard Goering
Group Editorial Director for EDA
EE Times Felton, CA
---- ---- ---- ---- ---- ---- ----
From: "Erach Desai" <erach.desai@csfb.com>
John,
No, do not count those 11 ST Micro (France) tape-outs in your recount.
Since I have recently taken a more cautious stance on the EDA sector for
2001 relative to Street expectations, I feel obliged to provide a somewhat
lengthy opinion (majority or dissenting?).
The FAQ posted on the DeepChip website is unambiguous: "I'll only count a
tape-out if I'm told by the physical synthesis user *himself* that he
taped out an X MHz, X kGate chip on X month on 0.XX micron process at
XXX fab". The ST-Micro (France) tape-outs email only states the process
technology without confirming any of the other details. The question
posed to the court is not about the integrity of the ST-Micro (France)
tape-outs, not about the voter's (design manager's) intent, and not about
the fairness of the process.
This jurist would point to several inadequacies in the process. First,
not all tape-outs are equal. Some used "physical synthesis" extensively,
others only on specific sub-modules, and others only experimentally.
Second, Cooley's definition of a tape-out is biased against the integrated
"physical design" solution providers (Avanti, Cadence, Magma, Monterey.)
But it's his survey, so it's his rules. Third, with over 30-42% of the
Synopsys PhysOpt tape-outs coming from ST-Micro (depending on whether one
counts the 11 dimpled votes), one would be led to conclude that ST-Micro
is the innovation capital of the chip industry(!!!) ... which gives a
whole new dimension to the brother Bush being governor of the pivotal
state analogy.
A few inescapable conclusions that can be analyzed from the data collected
by Cooley:
1) Silicon Perspective is clearly the sleeper surprise player
2) Synopsys' Physical Compiler appears to be eating Cadence's PKS' lunch
3) Concentrated customer tape-outs do not equal bookings and/or revenue
levels
Good luck, and God bless America and the EDA world.
- Erach Desai
VP of Technology Research
Credit Suisse First Boston Boston, MA
So, with a 4 to 1 vote of the EDA Supreme Court, I'm adding the 11 ST Micro
(France) tape-outs to the recount. Here's the amended, certified list of
confirmed tape-outs:
Synopsys "Physical Compiler (PhysOpt)" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
11/99 5+ M gates 180+ Mhz nVidia Santa Clara, CA 0.18
11/99 3+ M gates 180+ Matrox Montreal, Canada 0.18
12/99 135 K gates STMicro Grenoble, France
03/00 300 K gates ~150 STMicro 0.18
04/00 290 K insts 80 STMicro Agrate, Italy 0.25 STMicro
04/00 5+ M gates 200 nVidia Santa Clara, CA 0.18 TSMC
05/00 ~500 K gates 180 TI Wireless Dallas, TX 0.18
06/00 6.5 M gates 133/266 Unisys Minneapolis, MN 0.18 IBM
06/00 700 K gates 100 STMicro Castelletto, Ity 0.25 STMicro
07/00 290 K insts 80 STMicro Meylan, France 0.25 STMicro
07/00 1.5 M gates 100-200 Unisys Minneapolis, MN 0.18 IBM
07/00 300 K gates ~125 Conexant San Diego, CA 0.18
07/00 600 K gates 110 STMicro Castelletto, Ity 0.25 STMicro
08/00 80 K gates 25 Toppan Saitama, Japan 0.25
08/00 150 K gates 24 STMicro Castelletto, Ity 0.18 STMicro
09/00 300 K gates 120 Conexant San Diego, CA 0.18
09/00 7 K gates 200 Motorola Austin, TX 0.18 TSMC
09/00 3.5 M insts 250 nVidea Santa Clara, CA 0.18 TSMC
09/00 54 STMicro Castelletto, Ity 0.25 STMicro
10/00 160 K insts ~80 Toshiba Kawasaki, Japan 0.18 TC260
10/00 400 K insts 200 Broadcom Irvine, CA 0.18 TSMC
10/00 150 K gates 24 STMicro Castelletto, Ity 0.25 STMicro
10/00 470 K insts 450 Cray Chippewa Falls, WI IBM 0.12 Cu
10/00 ~10 K insts 133 Mhz Broadcom Irvine, CA 0.18 TSMC
11/00 830 K insts 100/133 Matrox Boca Raton, FL 0.18 NEC
11/00 1 M gates 100 Toppan Saitama, Japan 0.18
11/00 24 STMicro Castelletto, Ity 0.35 STMicro
11/00 ~25 K insts 200 TI DSP Dallas, TX 0.18
11/00 150 K gates 120 Conexant San Diego, CA 0.18
11/00 40 K gates 622 STMicro Carrolton, TX 0.25 STMicro
11/00 287 K insts 175 TI Wireless Dallas, TX 0.15 TI
11/00 600 K gates ~125 Conexant San Diego, CA 0.15
11/00 400 K gates 100 Toppan Saitama, Japan 0.18
11/00 73 K insts ~70 Toshiba Kawasaki, Japan 0.18 TC260
11/00 10 K gates 155 Hyperchip Montreal, Canada 0.18 IBM
11/00 79 K insts 100 LSI DSP Dallas, TX 0.18
11/00 ~70 K insts 104 Mhz Moto Wire Austin, TX 0.18
11/00 80 K insts 160 LSI DSP Dallas, TX 0.18
12/00 290 K insts 80 STMicro Meylan, France 0.25 STMicro
12/00 110 K insts 140 Mitel Semi Ottawa, Canada 0.18 TSMC
* 12/00 230 K gates 133 Agilent Corvallis, OR 0.18 HP
12/00 310 K insts 50-200 STMicro Grenoble, France 0.18 STMicro
12/00 4 M gates 155 Hyperchip Montreal, Canada 0.18 IBM
12/00 150 K gates 24 STMicro Castelletto, Ity 0.18 STMicro
12/00 1.8 M insts 200 nVidia Santa Clara, CA 0.15 TSMC
12/00 350 K gates 110 STMicro Castelletto, Ity 0.18 STMicro
12/00 5.0 M gates 266/300 Agilent Ft. Collins, CO 0.18
* - tape-out done using both Synopsys PhysOpt & Cadence PKS
plus the following 11 tape-outs from ST Micro (France):
Digital Storage Laguna Niguel, CA 3 tape-outs in 0.18 um
Micro Core Development Bristol, UK 1 tape-out in 0.25 um
Wireless Communications Grenoble, France 1 tape-out in 0.18 um
Consumer Broad Band Grenoble, France 3 tape-outs in 0.18 um
Graphics Products Div. Bristol, UK 1 tape-out in 0.18 um
Central R&D Crolles, France 2 tape-outs in 0.18 um
Synopsys "Chip Architect" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
* ??/00 450 K inst 125 Mhz Nexsi San Jose, CA 0.18 IBM
* - All dual PhysOpt/ChipArch tape-outs are listed once under PhysOpt
Synopsys/Everest "FlexRoute" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
* 07/99 1 M gates 200 Mhz Sandcraft Santa Clara, CA 0.18 LSI
* 09/99 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18
* 06/00 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18 LSI
* 07/00 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18
10/99 3 M gates 133 Mhz SGI Mountain View, CA 0.18
* - designs made with Sapphire "FormIT" & Everest/Synopsys FlexRoute
This gives Synopsys 59 PhysOpt, 1 Chip Architect, and 5 FlexRoute confirmed
customer tape-outs as of 12/15/00 making a total of 65 physical synthesis
tapeouts.
Silicon Perspective "First Encounter" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
06/98 1 M gates 110 Mhz Trident Santa Clara, CA 0.35 UMC
09/98 1.3 M gates 120 Trident Santa Clara, CA 0.25 TSMC
11/98 1 M gates 125 Trident Santa Clara, CA 0.25 Samsung
07/99 1 M gates 125 Trident Santa Clara, CA 0.21 UMC
10/99 1 M gates 120 Trident Santa Clara, CA 0.25 TSMC
08/00 400 K gates 30 Trident Santa Clara, CA 0.35 UMC
07/00 1.5 M insts 110-200 Philips Sunnyvale, CA 0.18 TSMC
10/00 300 K insts ?? Marvell Sunnyvale, CA ??
11/00 49 K insts 66 HiNT Fremont, CA 0.25 TSMC
12/00 3.2 M gate 160 Trident Santa Clara, CA 0.18 UMC
Q2/98 1 M gates 120 Trident Santa Clara, CA 0.25 TSMC
Q1/99 2 M gates 150 Trident Santa Clara, CA 0.20 UMC
Q3/99 2.5 M gates 180 Trident Santa Clara, CA 0.18 UMC
Q1/00 1.9 M gates 133 S3 Santa Clara, CA 0.22 TSMC
Q3/00 75 K insts 100 Marvell Sunnyvale, CA 0.18
Q3/00 65 K insts 100 Marvell Sunnyvale, CA 0.25
Q3/00 93 K insts 100 Marvell Sunnyvale, CA 0.25
Q3/00 71 K insts 100 Marvell Sunnyvale, CA 0.18
Q3/00 700 K gates 110 Kawasaki Japan 0.18
Q3/00 500 K gates 70 Kawasaki Japan 0.25
Q3/00 300 K gates 90 Kawasaki Japan 0.25
Q4/00 162 K insts 100 Marvell Sunnyvale, CA 0.18
Q4/00 2.1 M gates 145 S3 Santa Clara, CA 0.22 TSMC
Q4/00 550 K gates 60 Kawasaki Japan 0.25
Q4/00 400 K gates 130 Kawasaki Japan 0.25
Q4/00 650 K gates 120 Kawasaki Japan 0.18
Q4/00 500 K gates 120 Kawasaki Japan 0.25
Q4/00 600 K gates 100 Kawasaki Japan 0.18
Q4/00 200 K gates 70 Kawasaki Japan 0.35
Q4/00 200 K gates 60 Kawasaki Japan 0.25
?? 1.2 M gates 75 Acute Comm. Hsin-Chu, Taiwan 0.25 TSMC
?? 256 K insts 100 AMD Sunnyvale, CA 0.30 UMC
?? 500 K insts 133 AMD (CPD) Austin, TX 0.25 UMC
?? 650 K insts 66 AMD (CPD) Austin, TX 0.25 UMC
?? 650 K insts 66 AMD (CPD) Austin, TX 0.25 UMC
?? 100 K insts 166 High Bndwd San Jose, CA 0.35 UMC
?? 2.4 M gates 100+ Kawasaki San Jose, CA KLSI
?? 612 K insts 144 Sanyo Gifu, Japan 0.25 IBM
?? 431 K insts 114 Sanyo Gifu, Japan 0.18
?? 800 K inst ?? SiS Hsin-chu, Taiwan 0.18
?? 1.2 M insts ?? SiS Hsin-chu, Taiwan 0.18
?? 80 K insts ?? Teralogic Mountain View, CA 0.25 TSMC
?? 450 K insts ?? Teralogic Mountain View, CA 0.25 TSMC
This gives Silicon Perspective a total of 43 verified customer tape-outs.
None of the Cadence, Magma, Mentor, Sapphire, nor Monterey tape-out counts
changed from the orginal 12/15/00 census report.
Conclusions
-----------
Synopsys PhysOpt +
ChipArch + FlexRoute : ################################ 65 tape-outs
Silicon Perspective
"First Encounter" : ##################### 43 tape-outs
Cadence
PKS : ### 7 tape-outs
Mentor
TeraPlace : ### 7 tape-outs
Sapphire
FormIT : ### 6 tape-outs
Magma
"Blast Fusion" : # 3 tape-outs
Monterey
Dolphin : 0 tape-outs
I liked what "Justice" Erach Desai of Credit Suisse First Boston said in his
dissenting opinion:
"A few inescapable conclusions that can be analyzed from the data collected
by Cooley:
1) Silicon Perspective is clearly the sleeper surprise player
2) Synopsys' Physical Compiler appears to be eating Cadence's PKS' lunch
3) Concentrated customer tape-outs do not equal bookings and/or revenue
levels"
To Erach's observations I'll add that anyone can creatively cook their books
to reflect pretty much any desired amount of physical business they're
supposedly "closing". (I learned that one when Joe Costello, the CEO of
Cadence, years ago used to brag about how much money his Spectrum Consulting
division was making. Now years later in the Cadence Tality S-1 filing, it's
abundantly clear that Joe was losing money all along with his consulting
group!)
Concerning the newly crafted it's-not-a-tape-out-if-it's-not-full-P&R FUD
coming from the "losers" (Cadence, Magma, Monterey), I'll defer to:
"To claim 'tapeout' means that the tool was used in the design of
a chip - nothing more. This applies to tools both in the early
and late stages of a design flow. Whether GDSII is generated or
not is of no consequence."
- Michael Jackson, VP of Engineering, Avanti (EEdesign 12/15/00)
As I stated at the beginning of this survey, although it may be impossible
to follow the money in this contested market, tracking tape-outs will
clearly show who's really ahead, who's really behind, and who's publicly
lying because they're damn desperate in this market niche.
In a nutshell, Synopsys, Cadence, and Magma are all claiming that they've
made roughly $50 million in the physical synthesis market. But, when you
look at the real customer tape-outs with these tools you'll find Synopsys
has 65 vs. Cadence's 7 vs. Magma's 3 -- and Monterey has 0. From the
outside looking in, Synopsys appears to be winning with by a 10X to 20X
lead over Cadence and Magma -- and Monterey is in serious trouble.
"It is interesting to note that those customers who write to John
Cooley are in violation of their NDAs with EDA companies."
- Jacques Benkoski, Monterey CEO (EEdesign 12/15/00)
I hope you find this data useful and sorry for the need for a recount.
- John Cooley
DeepChip.com
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 11,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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