!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - /
_] [_ "The Surprise Physical Synthesis Tape-Out Census"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
"I don't want the cheese, I just want out of the trap."
- Spanish proverb
FOREWORD: I've personally verified each of the customer tape-outs listed in
this report either by direct e-mail or phone with at least one engineer in
the customer company mentioned. (I estimate I've done around 300 to 500
phone calls or e-mails over the past 7 days doing this count.) Intentially
excluded in this count are any unverified tape-outs even though the EDA
vendor may be able to provide one of their own press annoucements
supposedly "proving" the tape-out happened.
12/05/00 - Synopsys, Inc. holds a big press conference where its CEO, Aart
de Geus, announces he has 53 customer tape-outs for his physical
synthesis tools & closed $50 million of business in this niche.
12/07/00 - John Cooley, hoping to expose Aart's public exaggeration of 53
physical synthesis tape-outs, calls for a public counting of all
such tape-outs. Cooley sets a 7 day deadline so none of the EDA
vendors have time to rig the count. The call goes out on ESNUG.
12/08/00 - The "call for tape-outs" goes on EEtimes.com, EDAtoolsCafe.com,
ISDmag.com, ElectronicNews.com, and EEdesign.com.
12/12/00 - Cooley puts up the Rules for Counting up on DeepChip.com.
12/13/00 - With only 24 hours remaining, Cooley gloats to EE Times that he
has only found 26 tape-outs for Synopsys PhysOpt. It begins to
look like Aart has been caught in a public lie.
12/14/00 - On the 7 day deadline, an embarrassed Cooley has to announce
that he has found 50 Synopsys "physical synthesis" tape-outs.
Synopsys "Physical Compiler (PhysOpt)" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
11/99 5+ M gates 180+ Mhz nVidea Santa Clara, CA 0.18
11/99 3+ M gates 180+ Matrox Montreal, Canada 0.18
12/99 135 K gates STMicro Grenoble, France
03/00 300 K gates ~150 STMicro 0.18
04/00 290 K insts 80 STMicro Agrate, Italy 0.25 STMicro
04/00 5+ M gates 200 nVidea Santa Clara, CA 0.18 TSMC
05/00 ~500 K gates 180 TI Wireless Dallas, TX 0.18
06/00 6.5 M gates 133/266 Unisys Minneapolis, MN 0.18 IBM
06/00 700 K gates 100 STMicro Castelletto, Ity 0.25 STMicro
07/00 290 K insts 80 STMicro Meylan, France 0.25 STMicro
07/00 1.5 M gates 100-200 Unisys Minneapolis, MN 0.18 IBM
07/00 300 K gates ~125 Conexant San Diego, CA 0.18
07/00 600 K gates 110 STMicro Castelletto, Ity 0.25 STMicro
08/00 150 K gates 24 STMicro Castelletto, Ity 0.18 STMicro
09/00 300 K gates 120 Conexant San Diego, CA 0.18
09/00 7 K gates 200 Motorola Austin, TX 0.18 TSMC
09/00 3.5 M insts 250 nVidea Santa Clara, CA 0.18 TSMC
09/00 54 STMicro Castelletto, Ity 0.25 STMicro
10/00 160 K insts ~80 Toshiba Kawasaki, Japan 0.18 TC260
10/00 400 K insts 200 Broadcom Irvine, CA 0.18 TSMC
10/00 150 K gates 24 STMicro Castelletto, Ity 0.25 STMicro
10/00 470 K insts 450 Cray Chippewa Falls, WI IBM 0.12 Cu
11/00 830 K insts 100/133 Matrox Boca Raton, FL 0.18 NEC
11/00 24 STMicro Castelletto, Ity 0.35 STMicro
11/00 ~25 K insts 200 TI DSP Dallas, TX 0.18
11/00 150 K gates 120 Conexant San Diego, CA 0.18
11/00 40 K gates 622 STMicro Carrolton, TX 0.25 STMicro
11/00 287 K insts 175 TI Wireless Dallas, TX 0.15 TI
11/00 600 K gates ~125 Conexant San Diego, CA 0.15
11/00 73 K insts ~70 Toshiba Kawasaki, Japan 0.18 TC260
11/00 10 K gates 155 Hyperchip Montreal, Canada 0.18 IBM
11/00 79 K insts 100 LSI DSP Dallas, TX 0.18
11/00 80 K insts 160 LSI DSP Dallas, TX 0.18
12/00 290 K insts 80 STMicro Meylan, France 0.25 STMicro
12/00 110 K insts 140 Mitel Semi Ottawa, Canada 0.18 TSMC
* 12/00 230 K gates 133 Agilent Corvallis, OR 0.18 HP
12/00 310 K insts 50-200 STMicro Grenoble, France 0.18 STMicro
12/00 4 M gates 155 Hyperchip Montreal, Canada 0.18 IBM
12/00 150 K gates 24 STMicro Castelletto, Ity 0.18 STMicro
12/00 1.8 M insts 200 nVidea Santa Clara, CA 0.15 TSMC
12/00 350 K gates 110 STMicro Castelletto, Ity 0.18 STMicro
12/00 5.0 M gates 266/300 Agilent Ft. Collins, CO 0.18
* - tape-out done using both Synopsys PhysOpt & Cadence PKS
Synopsys "Chip Architect" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
10/99 100 K gates 100 Mhz Avici N. Billerica, MA 0.18 LSI
10/99 300 K insts 100 Avici N. Billerica, MA 0.18 LSI
10/99 750 K gates 100 Avici N. Billerica, MA 0.18 LSI
Synopsys/Everest "FlexRoute" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
* 07/99 1 M gates 200 Mhz Sandcraft Santa Clara, CA 0.18 LSI
* 09/99 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18
* 06/00 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18 LSI
* 07/00 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18
10/99 3 M gates 133 Mhz SGI Mountain View, CA 0.18
* - designs made with Sapphire "FormIT" & Everest/Synopsys FlexRoute
COUNTING NOTES: This gives Synopsys 42 verified Physical Compiler, 3 Chip
Architect, and 5 (Everest) FlexRoute tape-outs. Although many of the
PhysOpt tape-outs also involved Chip Architect, each tape-out was counted
only once. Not counted was one FlexRoute/ChipArch 450 K inst, 125 Mhz,
0.18 IBM tape-out by Nexsi of San Jose, CA because Nexsi replied after the
12/14/00 deadline. Also not counted were the following PhysOpt tape-outs:
10/00 ~10 K insts 133 Mhz Broadcom Irvine, CA 0.18 TSMC
11/00 ~70 K insts 104 Mhz Moto Wireless Austin, TX 0.18
because they, too, came in past the Thursday deadline.
Although Marketing VP Tom Ferry of Synopsys went on record in EE Times
on-line (12/13/00) saying I hadn't yet counted the SGI tape-out, my SGI
contacts told me that yes their design was close, but it's not a tape-out,
so you won't find SGI list in the verified PhysOpt tape-outs above.
COMMENTARY: Within the first few hours after I announced on ESNUG that I
was doing this tape-out count, Synopsys Marketing contacted me to tell me
how their count of 53 was conducted. While I thought:
Physical Synthesis Tape-Outs = Physical Compiler (PhysOpt) Tape-Outs
they informed me that they used the formula:
Physical Synthesis Tape-Outs = Physical Compiler (PhysOpt) Tape-Outs +
Chip Architect Tape-Outs +
(Everest) FlexRoute Tape-Outs
Which very much surprised me at first. After a little mumbling, I agreed
to that standard but said that each tape-out counts only once - a combo
PhysOpt/ChipArch tape-out is *one* tape-out -- not *two*. They agreed.
So, for the record, I found 50 tape-outs using *their* way of counting and
I found 42 using *my* way of counting.
Overall, after conducting this tape-out census, I feel that Aart had played
me like a used guitar. Or perhaps, more correctly, his Marketing weasils
and field staff probably ran this under some code name like "Operation
Spank Cooley". Some very trustworthy people I know at STMicro went on
public record claiming 20 tape-outs for Synopsys -- yet in 7 days I could
only find 15 of them. Also you won't find Toppan listed in the tape-outs
even though Aart put their logo up on his slides as one of his tape-outs.
Toppan just never contacted me. If there really was only 53 tape-outs,
there is *no way* I could have found 50 of them within 7 days of a surprise
count. The Synopsys field may have seriously hustled to get their physical
customers to contact me within that deadline, but getting a 90+ percent
response rate in that timeframe isn't statistically realistic.
What this all tells me is that Synopsys probably really has 60-something
(to possibly low 70 something) PhysOpt/ChipArch/FlexRoute tape-outs and
that Aart gave himself a safety margin when he claimed those 53.
Aart played me like a used guitar.
[ Editor's Note: The tape-outs for Synopsys were recounted. Please see
http://www.deepchip.com/gadfly/gad122100.html for the final count. ]
CADENCE "PKS"
-------------
Cadence "PKS" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
04/00 50 K gates 130 Mhz EmpowerTEL San Jose, CA ??
06/00 50 K gates 100 Agilent Corvallis, OR 0.18 HP
06/00 166 K gates 166 Agilent Corvallis, OR 0.25 HP
11/00 200 K gates 160 Geocast Beaverton, OR 0.18 TSMC
11/00 50 K gates 100 Agilent Corvallis, OR 0.18 HP
11/00 1.4 M gates ~125 Intel Chandler, AZ 0.25 Intel
* 12/00 230 K gates 133 Agilent Corvallis, OR 0.18 HP
* - tape-out done using both Synopsys PhysOpt & Cadence PKS
COUNTING NOTES: This gives Cadence PKS a total of 7 verified customer
tape-outs. I received an e-mail from one engineer in Motorola that spoke
of a 31 Mhz 167 K gate, 0.35 mixed-signal chip tape-out, but I excluded it
from the count because it turned out that all the PKS work was done by a
Cadence consulting engineer. This survey is a count of *customer*
tape-outs, not EDA vendor "taxicab mode" tape-outs. ("Taxicab mode" is
where the EDA vendor drives the tool instead of the customer.)
I counted one tape-out twice in this entire survey because the customer had
seriously used both Synopsys PhysOpt and Cadence PKS on his design. "Our
dual PhysOpt/PKS tape-out was done because we ran into some run-time
issues with PKS on that core. It was taking 6 days to compile and we
couldn't get any debug/improvement cycles in," reported Jay McDougal of
Agilent. "The PhysOpt run took about 1 day but had about 10% larger area.
So, I used Ambit to get an initial netlist with the area savings and
PhysOpt to get a placement. I then returned to PKS after our internal scan
insertion tool and clock tree generation to do the final timing tweaks.
This allowed me to use the SE compatible global router in PKS, do
incremental optimization based on that global route, and get less than 2%
difference in pre- and post- final route timing in SE. With a PhysOpt
placement, we see 5-10% difference in pre- and post- route timing."
COMMENTARY: Although Cadence marketing put out a press release on 9/13/00
implying a PKS tape-out by Ericsson Microwave, no one from Ericsson ever
stepped forward claiming such a PKS tape-out. (I e-mailed and phoned
Cadence Marketing about this, but they never returned any of my repeated
messages.)
I was very impressed to see that 1.4 M gate, 125 Mhz Intel PKS tape-out.
That's a nice feather for Cadence to have in its PKS cap. Why Cadence
marketing didn't bother to do a press release on this one, I know not.
On the flip side, I was very surprised to not find a single PKS tape-out
from Philips Semiconductor -- one of Cadence's biggest customers. Also,
even though Cadence CEO Ray Bingham kept using the phrase "proliferation"
when he spoke of his company's physical synth tools in his last quarterly
report, having only 7 customer tape-outs for PKS doesn't seem to indicate
"proliferation" is the correct word to use here.
Maybe it's just Ray's enthusiasm coming out here.
MAGMA "BLAST FUSION"
--------------------
Magma "Blast Fusion" Customer Tape-Outs
Date Size Clock Company Location Fab/um
-------------------------------------------------------------------------
11/00 2.5 M insts 200+ Mhz 3Dlabs Egham, Surrey, UK 0.18 IBM 7SF
12/00 740 K insts 125 IMG Tech Kings Langley, UK 0.18 TSMC
12/00 800 K gates 200 NEC IC Kawasaki, Japan 0.13 NEC
COUNTING NOTES: This gives Magma a total of 3 verified customer tape-outs.
I received an e-mail from a trusted user source that a few (2? 3?) more
Magma tape-outs would be coming soon, but I didn't count these due to lack
of details and my source wanted me to keep his news quiet.
COMMENTARY: Rajeev Madhavan, the CEO of Magma (and who I think of as "the
Don King of EDA") has been bragging to the Wall St. EDA analysts that he
has "9 or 10 tape-outs" and he's going to close $50 million in business by
March 2000. Heeeeelllo! MyFly! Aart spanked me with 50 tape-outs and
*he's* only claiming $57 million in physical bookings! Rajeev has only
3 tape-outs and he's dishing out that he has $50 million in business?!
But it makes sense with Rajeev's burn rate. He has something like 220 R&D
engineers on staff. This means he's conservatively burning through at
least $2 million each month in investor dollars just paying their salaries.
Add workstations, facilities, office space, sales travel, etc. and that
could easily jump to $3 or 4 million each month Rajeev has to pay.
Rajeev has to take over the world by storm. Or go down in flames trying.
MONTEREY "DOLPHIN"
------------------
Monterey "Dolphin" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
* TBD TBD TBD TBD TBD TBD
* - Monterey has no confirmed customer tape-outs yet.
COUNTING NOTES: Counting 0 is pretty easy. Here, I'll do a recount. 0.
COMMENTARY: The CEO of Monterey, Jacques Benkoski, claims he has two
customer tape-outs. I found zero. Because he's so behind in the game, he
likes to put out FUD about what is and isn't a tape-out. (In his mind,
only P&R tools can do tape-outs. There is no such thing as a Design
Compiler tape-out as far as he's concerned.) He also likes to pretend his
tools are part of the mainstream design flow.
Physical Compiler "doesn't tapeout designs," he said. "What they are
doing is passing it to someone who is actually using a place and
routing tool to complete the design. That is truly taping it out."
Benkoski said that many of Monterey's customers feed Physical Compiler
netlists into Monterey's Dolphin Physical Design System, which they
use to tapeout designs.
- EE Times, 12/07/00
How Jacques goes from two customers and no tape-outs to "many of Monterey's
customers", I don't know.
I'm happy that Monterey just recently got $25 million in mezzanine funding.
They need it desperately.
The Old Flow "Sandwich" Tools
-----------------------------
When I first did this call for tape-outs I received a few angry letters
from Avanti and Avanti customers asking why I wasn't including Avanti
Saturn in my tape-out call. My answer to them is that Avanti Saturn,
Cadence PBopt, and Synopsys "Floorplan Manager" are all old flow sandwich
tools as far as I'm concerned. They "sandwich" between RTL synthesis and
P&R. They start with gates and end with gates or possibly placed gates.
They've been around for years and I'm sure Saturn, PBopt, & Floorplan Mgr.
can easily claim hundreds, if not thousands, of customer tape-outs.
There's no new information in tracking these old flow tape-outs.
In contrast PhysOpt/PKS/Magma/Monterey aren't sandwich tools. Their goal
is to (at least eventually) go from Verilog/VHDL RTL all the way down to
GDS II -- hence it's very interesting to track their tape-outs.
There are 3 exceptions, though, to tracking "sandwich" flow tape-outs and
that deals with how the newbie "sandwich" tools (Silicon Perspective,
Mentor's TeraPlace, and Sapphire's "FormIT") are doing.
SILICON PERSPECTIVE "FIRST ENCOUNTER"
-------------------------------------
Silicon Perspective "First Encounter" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
06/98 1 M gates 110 Mhz Trident Santa Clara, CA 0.35 UMC
09/98 1.3 M gates 120 Trident Santa Clara, CA 0.25 TSMC
11/98 1 M gates 125 Trident Santa Clara, CA 0.25 Samsung
07/99 1 M gates 125 Trident Santa Clara, CA 0.21 UMC
10/99 1 M gates 120 Trident Santa Clara, CA 0.25 TSMC
08/00 400 K gates 30 Trident Santa Clara, CA 0.35 UMC
07/00 1.5 M insts 110-200 Philips Sunnyvale, CA 0.18 TSMC
10/00 300 K insts ?? Marvell Sunnyvale, CA ??
11/00 49 K insts 66 HiNT Fremont, CA 0.25 TSMC
12/00 3.2 M gate 160 Trident Santa Clara, CA 0.18 UMC
Q2/98 1 M gates 120 Trident Santa Clara, CA 0.25 TSMC
Q1/99 2 M gates 150 Trident Santa Clara, CA 0.20 UMC
Q3/99 2.5 M gates 180 Trident Santa Clara, CA 0.18 UMC
Q1/00 1.9 M gates 133 S3 Santa Clara, CA 0.22 TSMC
Q3/00 75 K insts 100 Marvell Sunnyvale, CA 0.18
Q3/00 65 K insts 100 Marvell Sunnyvale, CA 0.25
Q3/00 93 K insts 100 Marvell Sunnyvale, CA 0.25
Q3/00 71 K insts 100 Marvell Sunnyvale, CA 0.18
Q4/00 162 K insts 100 Marvell Sunnyvale, CA 0.18
Q4/00 2.1 M gates 145 S3 Santa Clara, CA 0.22 TSMC
?? 1.2 M gates 75 Acute Comm. Hsin-Chu, Taiwan 0.25 TSMC
?? 256 K insts 100 AMD Sunnyvale, CA 0.30 UMC
?? 500 K insts 133 AMD (CPD) Austin, TX 0.25 UMC
?? 650 K insts 66 AMD (CPD) Austin, TX 0.25 UMC
?? 650 K insts 66 AMD (CPD) Austin, TX 0.25 UMC
?? 100 K insts 166 High Bndwd San Jose, CA 0.35 UMC
?? 2.4 M gates 100+ Kawasaki San Jose, CA KLSI
?? 612 K insts 144 Sanyo Gifu, Japan 0.25 IBM
?? 431 K insts 114 Sanyo Gifu, Japan 0.18
?? 800 K inst ?? SiS Hsin-chu, Taiwan 0.18
?? 1.2 M insts ?? SiS Hsin-chu, Taiwan 0.18
?? 80 K insts ?? Teralogic Mountain View, CA 0.25 TSMC
?? 450 K insts ?? Teralogic Mountain View, CA 0.25 TSMC
COUNTING NOTES: This gives Silicon Perspective a total of 33 verified
customer tape-outs. I received an e-mail from the Kawasaki LSI CAD manager
in Japan claiming that he had done 10 Silicon Perspective tape-outs for
customers in Japan, but since he didn't include the details of each chip,
I didn't those 10 as part of this tape-out count. After the deadline, the
very same manager sent me the data:
Q3/00 700 K gates 110 Mhz Kawasaki Japan 0.18
Q3/00 500 K gates 70 Kawasaki Japan 0.25
Q3/00 300 K gates 90 Kawasaki Japan 0.25
Q4/00 550 K gates 60 Kawasaki Japan 0.25
Q4/00 400 K gates 130 Kawasaki Japan 0.25
Q4/00 650 K gates 120 Kawasaki Japan 0.18
Q4/00 500 K gates 120 Kawasaki Japan 0.25
Q4/00 600 K gates 100 Kawasaki Japan 0.18
Q4/00 200 K gates 70 Kawasaki Japan 0.35
Q4/00 200 K gates 60 Kawasaki Japan 0.25
So I hate to be the bad guy, but I did state that at the beginning that I'd
only count those tape-outs that came in by the Thursday, 12/14/00 deadline.
COMMENTARY: Rules aside, if Silicon Perspectives went around bragging they
had 43 tape-outs in this survey, I wouldn't go out of my way to say they
were lying nor exaggerating.
[ Editor's Note: The tape-outs for Synopsys were recounted. Please see
http://www.deepchip.com/gadfly/gad122100.html for the final count. ]
MENTOR "TERAPLACE"
------------------
Mentor "TeraPlace" Customer Tape-Outs
Date Size Clock Company Location Fab/um
-------------------------------------------------------------------------
09/99 2 M gates 200 Mhz Cyrix Richardson, TX 0.18 National
12/99 41 K insts 600 Centar Austin, TX 0.18 TSMC
02/00 3 M gates 600 Cyrix Richardson, TX 0.18
05/00 50 K insts 733 Centar Austin, TX 0.15 TSMC
09/00 52 K insts 867 Centar Austin, TX 0.15 TSMC
09/00 8 K insts 120 Micronix Newport Beach, CA 0.35 AMI
12/00 300 K insts 100 Vitesse Morrisville, NC 0.25 NEC
COUNTING NOTES: Nothing unsual happened here. I found 7 customer verified
tape-outs for Mentor's TeraPlace tool.
COMMENTARY: Looks like they're in the game, but only in a small way. From
the outside looking in, the little Silicon Perspective start-up is kicking
big old Mentor's butt in this category.
SAPPHIRE "FORMIT"
-----------------
Sapphire "FormIT" Customer Tape-Outs
Date Size Clock Company Location Fab/um
------------------------------------------------------------------------
* 07/99 1 M gates 200 Mhz Sandcraft Santa Clara, CA 0.18 LSI
* 09/99 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18
* 06/00 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18 LSI
* 07/00 1 M gates 300 Mhz Sandcraft Santa Clara, CA 0.18
12/00 500 K gates 133 Mhz SiAccess San Jose, CA 0.18 TSMC
12/00 450 K gates 133 Mhz SiAccess San Jose, CA 0.18 TSMC
* - designs made with Sapphire "FormIT" & Everest/Synopsys FlexRoute
COUNTING NOTES: I found 6 customer verified tape-outs for Sapphire
"FormIT". Four of the 6 tape-outs are shared with Everest/Synopsys
FlexRoute because the customer used both tools.
COMMENTARY: During this whole tape-out count, I tried my best to stay in
touch with each of the EDA companies involved. I'd send them e-mails
telling them the customer counts I found for their tools, talked to their
marketing people, etc. I did this with Magma, Cadence, Synopsys, Monterey,
Silicon Perspectives, and Mentor. The only people I couldn't reach was
Sapphire. I'd call them and even their main phone number bumped me to the
receptionist's voicemail! (Odd!)
Then I found out that Sequence had just bought Sapphire. No wonder no one
was answering the phone at Sapphire -- they were all out Christmas shopping
with the boatload of cash they got from Sequence.
- John Cooley
DeepChip.com Holliston, MA
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 11,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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