!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
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_] [_ "The Physical Synthesis Tape-Out Census FAQ"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
For my own personal sanity, here's a FAQ for how I'm doing the survey of
known physical synthesis tape-outs. I've been getting a lot of e-mails on
this and I don't have the time to directly answer each question. Also, I
think it's just a good idea for people to understand how this count is being
done.
Q: What triggered this count of physical synthesis tape-outs?
A: At a press conference last Tuesday, Aart de Geus, the CEO of Synopsys
made the public claim that he had 53 customer tape-outs with his physical
synthesis tools yet wouldn't give a detailed list of who these customers
are. Rajeev Madhavan, the CEO of Magma, has been telling the financial
community he has 9 to 10 tape-outs. Ray Bingham, the CEO of Cadence,
also makes many allusions to PKS "proliferation" and implied tape-outs
when he talks to Wall Street and the press. I'm seeking to verify or
disprove these EDA vendor claims. Tape-outs are the real life use of an
EDA tool to make actual production chips.
Q: With this survey going out to the 11,000 readers on ESNUG, won't it miss
the Magma and Cadence users?
A: ESNUG readership in March 2000 broke out to approximately 81 percent
Design Compiler users, 23 percent Avanti Apollo users, and 22 percent
Cadence Silicon Ensemble users. Also this tape-out survey was published
this week on http://www.DeepChip.com and on the following websites:
http://www.EEdesign.com http://www.EEtimes.com http://www.isdmag.com
http://www.electronicnews.com http://www.EDAtoolsCafe.com
I think the vast majority of Cadence, Magma, and Synopsys customers know
of this tape-out count, so no one will be left out.
Q: How are you counting tape-outs?
A: First, I'll only count a tape-out if I'm told by the physical synthesis
user *himself* that he taped out an X Mhz, X kgate chip on X month on
0.XX um process at XXX fab. Chips that I'm told about by Synopsys, Magma
and Cadence won't count until they're confirmed by the customers
themselves. Also, each design counts only once. If IBM fab tells me
they have 3 customer PhysOpt chips in the pipe and SGI, Cray, & Hyperchip
say they've each done one PhysOpt chip on IBM 0.18 -- I count 3 tape-outs
here, not 6 tape-outs. A single chip is one design. For example, if you
have 4 blocks on one chip that ran through Magma, it's still one tape-out
not 4 tape-outs. ECO's aren't new tape-outs; ECO's are engineers working
to correct the original tape-out. But fundamentally different versions
of a design (like the low power versus the high performance versions) are
legitimate unique tape-outs. Process migrations (taking a design from
0.35 um down to 0.18 um) are tape-outs. A "pending" tape-out is not a
tape-out; it's a tape-out that might be coming some time in the future.
(An awful lot of chip designs can go for months on end being "95 percent
complete".)
Q: What's a tape-out? What's not a tape-out?
A: A tape-out is when the designer gets timing closure with the intent of
actually fabricating the final design. The chip doesn't have to actually
have been made because many times designs are yanked from production at
the last minute for business reasons. I'm looking for at least a final
clean DRC/LVS before I agree it's a tape-out. "Technology evals" don't
count unless these designs actually go to fab. Why? Because customers
doing "techology evals" are just playing with the tool; they aren't
betting on the actual success of the tool and will easily hand wave past
any minor issues they encounter. Yet in real life designs, many times
these seemingly "minor" problems they ignored in eval can explode into a
major problem on a real chip. (See ESNUG 362 #1 for an example of this.)
Also, another non-tape-out is if the EDA vendor runs their tool for the
customer (i.e. "taxicab mode") instead of the user running the physical
synthesis tools themselves. Taxicab mode happens a lot in evals. It's
interesting, but it's not a customer tape-out as far as I'm concerned.
Q: What about customers who don't want to be known? Won't this effect the
count?
A: Yes, but it'll most likely effect all tape-out counts equally. Let's say
it turns out that 20 percent of Synopsys customers wish to keep it very
secret that they used Synopsys physical synthesis. It's my conjecture
then that 20 percent of Magma customers and 20 percent of Cadence PKS
customers will behave the same way -- skewing all tape-out counts down
equally. It's not as if most Cadence users live on Venus, most Synopsys
customers live on Mars and most Magma customers live on Pluto. Physical
synthesis users are from one fairly small world of chip designers.
Q: Do you expect to find all 53 Synopsys customer tape-outs?
A: No, but if I find less than 25, you know someone's lying.
Q: Do expect to find all 10 Magma tape-outs?
A: No, but if I find less than 5, you know someone else is lying, too.
Q: Why are you doing this on such short notice of seven days?
A: Having a very short amount of time to get these customers tape-outs in
reduces the risk that Synopsys/Magma/Cadence could sweet talk some
customers to send in Not Quite So True customer tape-out "successes".
A short notice keeps everyone mostly honest because they simply don't
have enough time to rig up many fake customer tape-outs.
Q: Are the EDA vendors themselves involved with this count?
A: Yes, I've contacted all of them and given them the current status of
known tape-outs I have for them plus the rumored tape-outs I have for
them. Again, I don't count tape-outs unless the CUSTOMERS confirm that
they did the tape-out themselves. Taxicab tape-outs don't count.
Q: How will you report your findings?
A: On Wednesday of this week I'll give Richard Goering of EE Times the
preliminary list of known Synopsys physical synthesis tape-outs that
are known at that time. He says they'll be on http://www.EEdesign.com
when he gets them. On late Thursday or early Friday morning, I'll have
the final tally of Synopsys, Magma, Cadence PKS, Monterey, and related
tape-outs up on http://www.DeepChip.com and out on the ESNUG mailing
list.
And for those EDA users sending me your tape-out info, THANK YOU for helping
me cut through the EDA Marketing bullshit!
- John Cooley
DeepChip.com
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 11,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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