"Monkeys with wiffle bats beating on keyboards build better software
than EDA companies."
- [ anon message #1477 on the Yahoo! SMMT board ]
( ESNUG 330 Subjects ) ------------------------------------------- [9/99]
Item 1: ( ESNUG 329 #1 ) How The Ambit 80% Price Cut Effects Buy Choices
Item 2: Cheap IC Layout Viewers/Editors for GDSII Files On Windows NT
Item 3: ( ESNUG 329 #11 ) Tools To Convert Transistors Into Schematics
Item 4: Call-For-Papers For The Year 2000 SNUG Europe Conference In Paris
Item 5: ( ESNUG 326 #7 329 #7 ) Getting *Signed* Comparitors w/ DC 99.05
Item 6: ( ESNUG 329 #21 ) One Customer Reviews The Revamped DW PCI Core
Item 7: ( ESNUG 328 #6 ) Those Complicated DC Wireload Issues Continue
Item 8: ( ESNUG 329 #17 ) Cadence 'Pearl' & DC Just *Won't* Play Nice
Item 9: ( ESNUG 329 #20 ) Timing Diagram Editors Other Than Chronology's
Item 10: ( ESNUG 328 #1 ) The Final Word On The "Flex-LM Cracked" Story
The complete, searchable ESNUG Archive Site is at <http://www.DeepChip.com>
( ESNUG 330 Item 1 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 329 #1 ) How The Ambit 80% Price Cut Effects Buy Choices
> You've no doubt heard the news that Cadence has slashed the price of Ambit
> BuildGates to $25k. My question is: with Synopsys effectively raising the
> price of Design Compiler, and many testimonials that BuildGates is as good
> or better than DC, why stay with DC? Is there anything that DC can do
> that BuildGates can't?
>
> - Brian Walkington while on contract at Hewlett-Packard
From: Paul Borsetti <pborsetti@enikia.com>
John,
We are a small company just starting an ASIC design group. Most of us have
lots of experience in using Synopsys (I have used it since the early 90's).
We had Cadence in a couple of days ago and I must say that they caught our
ear with Ambit. It is hard for us to ignore the price -- but I am really
scared about leaving Synopsys. Can you give us some advice please? An EDA
mistake for this company could result in a disaster -- and I am scared.
- Paul Borsetti
Lead ASIC Design Engineer
Enikia Corporation Piscataway, NJ
---- ---- ---- ---- ---- ---- ----
From: [ message #993 by 'Z. Marcisz' on the Yahoo! SNPS board ]
I've been an Ambit salesperson from the early days and am no longer with
Cadence. Here's my 2 cents on the Ambit product and what the latest Cadence
annoucement means:
1) Ambit had a clear lead in both design size capacity, runtime and
area/timing results. With DC 99XX, SNPS has closed this gap and both
tools are about on par with each other. Ambit holds an edge with it's
higher capacity and built-in static timing engine. At $25K it compares
very well to a $125K+ solution from SNPS.
2) We (almost) never lost a deal to SNPS when competing for business at
new startups. When designers benchmarked the two tools, we
traditionally won. Stratum One, Maverick Networks, Monterey Design,
Amber Networks, etc. all picked Ambit over DC. Again, this $25K price
point will make these deals a slam dunk in the future.
3) We had a tougher time with established SNPS accounts. The main reason
was switching costs. It's hard to displace thousands of lines of
scripting and the expertise with DC. The new price point will do one
of two things in these accounts: 1) give the CAD Mgrs a huge hammer for
getting the best discount out of SNPS or 2) if SNPS doesn't want to
drop their shorts, the users will switch to Ambit. They'll get great
technology, support and much better price. Either way, CDN will win.
4) PKS is out there and VERY real. A number of my accounts were beta
sites and the results look very compelling for high speed designs
and/or sub .18u technologies.
SNPS is about 6-8 months behind with it's counter punch -- PhysOp. We're
still not sure where they going to get the P&R technology for this product.
Given that 30+% of SNPS revenues come from DC, I think this aggressive move
by CDN will impact SNPS' DC revenues and create a great upgrade path for CDN
users to PKS.
- [ message #993 by 'Z. Marcisz' on the Yahoo! SNPS board ]
( ESNUG 330 Item 2 ) --------------------------------------------- [9/99]
Subject: Cheap IC Layout Viewers/Editors for GDSII Files On Windows NT
> Do you know of a free or low cost layout viewer that would enable me to
> view IC layouts (GDSII data type) on an NT operating system? Where can I
> get it? Of course, it would be nice if I could also edit the layout, but
> simply viewing a layout and being able to measure distances would be a
> good start.
>
> - Paul Alan Spitalny
> Cascade Linear
From: Jim_T@analog-innovations.com ( Jim Thompson )
You can get GDSVU from <http://www.artwork.com> for around $500, which is
what I use for checking layouts. It's a viewer only, no editing. I think
ICEditor is available for a few thou' and does just about everything.
- Jim Thompson
Analog Innovations, Inc. Phoenix, AZ
---- ---- ---- ---- ---- ---- ----
From: Toby Schaffer <jtschaff@eos.ncsu.edu>
The canonical answer to the free layout viewer/editor question is Magic, but
I don't think there's an NT version. However, you can download an eval copy
of VMware <http://www.vmware.com/products/forwindowsnt.html> which should
let you run Linux/X Window binaries under NT.
- Toby Schaffer
North Carolina State University
---- ---- ---- ---- ---- ---- ----
From: pontius@btv.ibm.com (Dale Pontius)
A few years back I fiddled with a layout editor called "LASI" that runs
under DOS. I lost track of it, but at the ISSCC this year I ran across a
book co-authored by the author of LASI, and the book uses the program, so
apparently it's still around.
A quick stop to google, look for "lasi" and "boyce", and it's still around.
It's even mentioned in the comp.lsi.cad faq. LASI has it's own format, but
it has a GDSII import facility. It also has rather an interesting editing
paradigm -- it worked on groups of vertices, last time I tried it.
- Dale Pontius
IBM Burlington, VT
---- ---- ---- ---- ---- ---- ----
From: Serban-Mihai Popescu <serbanp@ix.netcom.com>
If you're familiar with Magic, I think there is somewhere on the net a
Windows version for it. I don't have at hand the pointer, but it shouldn't
be so hard to find it.
- Serban-Mihai Popescu
( ESNUG 330 Item 3 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 329 #11 ) Tools To Convert Transistors Into Schematics
> Has anyone ever heard of a tool that can convert a transistor-level SPICE
> netlist into a schematic? We thought about making a dummy library in
> Library Compiler and then converting the netlist into verilog then reading
> it in to DC, but there has to be a better way. Any ideas?
>
> - Andy Frazer
> Integrated Device Technology Santa Clara, CA
From: [ Life In The Fast Lane ]
John, keep me anonymous.
There are two tools that I know of -- Cadence's Affirma_TLA (Transistor
Logic Abstractor), and Tuxedo-LTX from Verplex.
- [ Life In The Fast Lane ]
---- ---- ---- ---- ---- ---- ----
From: Benoit.Durand@st.com
John,
When I was AE at COMPASS, we had a tool called 'Laybool' that was able to
convert SPICE netlist to Verilog or vhdl. I think that Avanti still sells
this tool. It's new name is Lynx.
- Benoit Durand
ST Microelectronics
---- ---- ---- ---- ---- ---- ----
From: David Chapman <dchapman@aimnet.com>
John,
If this user wants extract the functionality of the cell and generate a
truth table, there are two ways to look at the problem:
1) lots of library characterization tool vendors perform this step
automatically as part of the delay measurement process
2) it is very difficult because of issues with dynamic logic,
pass-gate logic, and feedback cells (i.e. flip-flops)
These are not contradictory; the tools tend to fall down when given "messy"
cells. He may need to hire some outside help to do this tranlation by
hand or, of course, the library characterization vendors would be only
too happy to help you -- for a price.
- David Chapman
Chapman Consulting Santa Clara, CA
( ESNUG 330 Item 4 ) --------------------------------------------- [9/99]
From: Ronald Niederhagen <SNUGeurope@synopsys.com>
Subject: Call-For-Papers For The Year 2000 SNUG Europe Conference In Paris
John,
Could you send out a reminder to ESNUG that the Call For Papers is open for
SNUG'00 Europe? We are asking Synopsys users to participate by submitting
an abstract that will share their experiences and success stories with other
European users. We would like to receive these abstracts by Friday, October
29th, 1999. ( See <http://www.snug-universal.org> )
We are looking forward to an excellent EuroSNUG'00 next year in Paris! The
Design Automation and Test, Europe (DATE2000) conference and exhibition will
be held 28th-30th March; EuroSNUG'00 will be on Thursday 30th and Friday
31th March, 2000.
- Ronald Niederhagen,
SNUG'00 Europe Technical Chair
Synopsys European Headquarters Munich, Germany
( ESNUG 330 Item 5 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 326 #7 329 #7 ) Getting *Signed* Comparitors w/ DC 99.05
> An old collegue in the Netherlands, Rob van der Valk, gave me a hint on
> how to do the signed comparisons after he saw my letter in ESNUG. The
> trick is to invert the MSB's of the operands and do an unsigned
> comparison on that. So instead of:
>
> op_a[n:0] > op_b[n:0]
> do:
> {~op_a[n],op_a[n-1:0]} > {~op_b[n],op_b[n-1:0]}
>
> That's easier and smaller in logic than the functions I wrote.
>
> - Menno Spijker
> Mitel Semiconductor Kanata, Canada
From: Charutosh Dixit <charu@lsil.com>
John,
The solution given for above for signed comparators looks flawed to me. The
correct solution is: If we have two signed numbers to be compared, we swap
the MSBs of the two numbers and then perform the regular magnitude
comparison. The scheme works as follows:
a. When the two numbers have the same sign, MSB swapping does not have any
effect and the regular magnitude comparison is done
b. When the two numbers have opposite sign, like for example A=0011 and
B=1001, then the positive number (A) is the bigger number. By swapping
the MSB we get A=1011 and B=0001, and thus the positive number is made
bigger in magnitude (1011 > 0001), for the magnitude comparison that
follows this process.
Hope this helps your ESNUG readers.
- Charu Dixit
LSI Logic Milpitas, CA
( ESNUG 330 Item 6 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 329 #21 ) One Customer Reviews The Revamped DW PCI Core
> Has anyone successfully use the DWPCI MacroCell from Synopsys? Was it
> compliant with the relevant specifications? What were the implementation
> issues? How did you handle the I/O timing (PLL, etc.)? Thanks for any
> information you can supply.
>
> - Dave Peeters
> Entridia
From: Jim McDonald <jim@3ware.com>
Hi, John,
I'm not sure what the correct form this should take; here are the points we
used to choose the DW PCI core:
1) Performance: The DW PCI core is able to initiate fast back-to-back
transactions and memory write and invalidate commands. Other core
designs insert or require extra latency clocks or turn-around (recovery
time) clocks. These limitations do not seem to exist in the DW PCI
core. Some of the cores that we looked at were designed years ago and
didn't seem to optimize performance.
2) Ease of integration: The DW PCI core comes with an extensive simulation
environment that allows regression testing of PCI compatibility. Also,
since the DW PCI core comes from Synopsys, it seems to optimally use DC
to generate scripts that correctly enforce PCI timing requirements.
This feature gave us confidence that we could meet PCI specs with
readily available silicon processes.
3) Flexible: The same core design is usable for 32/64 bit and 33 MHz or 66
MHz. Also, many parameters are configurable at synthesis time, without
re-writing verilog code.
4) Documentation: The documentation is comprehensive (huge) and seems
complete. This docmentation includes PCI & back-end waveforms instead
of just text descriptions, helping to visualize the transactions.
We have used some other PCI core designs that were more limited and less
complete. For example, one core we have experience with does not perform
any of the initiator retry functions automatically; so back-end logic must
be created and verified to meet the PCI specification (i.e. we had to
become PCI experts to make this core work properly.)
Our design is not in silicon yet, but we have done some simulation and
back-end design. We're very optimistic about making our design goals.
- Jim McDonald
3Ware Palo Alto, CA
( ESNUG 330 Item 7 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 328 #6 ) Those Complicated DC Wireload Issues Continue
> I did a real quick test setting the top level of a design to a certain
> wireload, with all the subdesigns having no wireload. The results were
> the same as setting all designs to that same wireload. The timing for
> having no wireload whatsoever set was different, so this supports that
> designs with no wireload do indeed inherit them from parent hierarchy.
>
> - [ A Synopsys CAE ]
From: Robert Wiegand <rwiegand@ensoniq.com>
Hi John,
I found another interesting wireload "behavior" that I didn't expect
involving enclosed mode and switching between operating conditions. Let's
start with a hierarchical design compiled bottom up, with the wireload
specified for each design based on design size, using enclosed mode. Each
design is compiled, dont_touch'ed, and saved without the -hierarchy switch
(compile generated hierarchy such as designware and mux-ops are ungrouped
after the compile) ensuring that higher level designs will link in the
previously compiled lower level designs without trying to recompile them.
As expected, the wireloads set on the lower level designs will "stick" (as
if they were design attributes) when they are linked in by higher level
designs. A core level timing report will show all the subdesigns and their
respective wireloads as expected.
The unexpected behavior occurs after changing operation conditions. I do
the lower level compiles at max conditions, but at the core level I do a
min/max fixup step, and check the results at min, typ, max and minmax
conditions. Changing conditions on the fly (without reloading the design)
includes the following steps:
1) unload old libraries and reload new libraries if they are different
2) update the link_library and target_library variables
3) perform any library initialization steps such as dont_use'ing specific
cells, etc
4) set the wireload on the current design
5) set the operating conditions on the current design
6) redefine the clocks on the current design (insertion delays are
different)
The core level timing report no longer shows the subdesign wireloads! The
above listing of steps is abreviated, and I haven't isolated exactly which
command makes the subdesign wireload behavior change. The timing results
are consistant with using an enclosed wireload at the core and not setting
the subdesign wireloads i.e., the core wireload is used for the entire
design. Changing to one of the subdesigns and doing a report_design gives
different results depending on whether or not there is a default wireload
attribute on the library. With a library default wireload, the report
shows the wireload as manually selected by user, but the wireload is the
default wireload, not the desired one. Without a library default wireload,
the report shows no wireload specified.
In either case, it is still the core wireload that is used throughout the
design. I tried this on several libraries, including one where all
condtions are in the same library, and another with seperate min, typ and
max libraries. The results were the same.
In order to get around this, and return to the desired and expected
behavior, I modified my scripts for changing operating conditions to set
the wireload on each and every design in the hierarchy. Something like
this:
which project_name + "_wireload.scr"
if (dc_shell_status) {
echo "Using hierarchical wireloads"
foreach (des, find(design)) {
current_design des
include project_name + "_wireload.scr"
} else {
echo "Using default wireload"
current_wireload = wireload_load
foreach (des, find(design)) {
current_design des
set_wire_load -library wireload_library -mode wireload_mode
current_wireload
}
}
current_design core
The script referred to by project_name + "_wireload.scr" is a brute force
search and destroy script to match up the current_design design name with
an associated wireload. This worked great until I tried to route the scan
chains at the core level, which changes the design names! The variable
insert_test_design_naming_style can be used to control how the design is
renamed, but the %s and %d fields are required. I set it to %s_scan_%d.
Since I couldn't find any quick and easy way to prevent the renaming from
occuring, I had to resort to more brute force. The wireload script looks
something like this:
/* get design_name as a string */
root_design {}
design_name = ""
foreach (root_design, find(design, current_design)) {}
design_name = root_design
/* assign wireload to design_name */
if (design_name = = top_block){
current_wireload = [top wireload]
} else if (design_name == core_block \
|| design_name == core_block + "_scan_1")
{ current_wireload = [core wireload] }
else if (design_name == "block1" || design_name == "block1_scan")
{ current_wireload = [block1 wireload]}
else if (design_name == "blockn" || design_name == "blockn_scan")
{ current_wireload = [blockn wireload] }
else {
echo "Design not found in wireload script, using default wireload"
current_wireload = wireload_load
}
set_wire_load -library wireload_library -mode wireload_mode
current_wireload
My timing reports now show all the correct and expected subdesign
wireloads, and the timing results are consistant with the expected wireload
behavior.
- Bob Wiegand
Creative Labs Malvern, PA
( ESNUG 330 Item 8 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 329 #17 ) Cadence 'Pearl' & DC Just *Won't* Play Nice
> I would like to ask a question. We, Chip Express are an ASIC vendor. We
> are now in the process of developing a layout flow that is using Timing
> Driven Q-place placement software from Cadence. Being timing-driven, the
> software reads constraint files produced by, you guessed it -- Synopsys.
>
> The tool that reads and converts the constraint file is: Pearl (Cadence
> static timing analysis tool). We are receiving Synopsys constraint files
> from various Synopsys versions. Almost each time we use Pearl there are
> statements that are not recognised by the tool, and causes it to produce
> erroneous output.
> The only thing we can do is manually change the constraint file, and try
> again. As I said, we get different "types" of constraint files, depending
> on the Synopsys version used. Does anyone know of a formal / informal way
> to overcome this problem ?
>
> - Eran Rotem
> Chip Express (Israel) Ltd. Haifa, Israel
From: Frank Emnett <frank@aiec.com>
Eran,
Have you tried the write_script command in Synopsys? It might help
eliminate some of the variance in constraint types. We are trying it as
an interface to Cadence tools (SE-DSM), where it gets converted to GCF.
- Frank Emnett
Automotive Integrated Electronics Corp. Phoenix, AZ
---- ---- ---- ---- ---- ---- ----
From: London Jin <londonj@eng.adaptec.com>
Hi John,
I share Eran's pain. Using Synopsys' constraints and applying them to
Cadence does not work well because Synopsys does not tell Cadence what
changes down the road, and Cadence does not keep pace with every Synopsys
version upgrade. As a result, the TDL flow is full of issues, and does not
produce promising results.
Issue #1. Before 1998.02, in "set_false_path -through {A B}", A, B are
considered as AND relation in Synopsys. This is what Cadence
has supported. However, Synopsys changed from the AND relation
to the OR relation in 1998.02 and Cadence remains unchanged as
of today. To make it backward compatible, Synopsys has a
variable you can set: set timing_through_compatibility "true"
If you are not aware of it, your timing exceptions are incorrect
in Cadence.
Issue #2. Cadence does not support multiple -through as of today.
Both issues above introduce errors in timing constraints. I am not excited
about TDL. Do you have any successful cases?
- London Jin
Adaptec Milpitas, CA
---- ---- ---- ---- ---- ---- ----
From: Nir Sever <nir@gigapixel.com>
Hi John,
The problem Eran is facing is what I consider today to be my biggest problem
in setting up Timing Driven design flows, using different tool vendors.
I've been working with some EDA companies developing timing driven back-end
tools (floorplanners and P&R) and it seems like everyone is having its own
constraints format. Even worse, everyone supports different types of
constraints. Since Synopsys is the source for the constraints, you need to
translate from Synopsys to everyone else's format, and try to restrict the
design to use just the constraints your tool vendor can support.
For example, in Synopsys you can define multi-cycle path with -through
attribute. This can be translated to GCF (allthough not with the Cadence
supplied translator), but Pearl doesn't support this so basically you can't
use this constraint to drive Qplace. My conclusion:
1. Write your own translator(s) (I did...)
2. Restrict your designers to constraints that are translatable (I
know it's easier for me than it is to you).
3. When you have a certain structure that requires more complicated
constraints (I have an AGP/PCI combo block with very complicated
constraints), take it out of the "big chunk" and use the SDF Path
Constraints for it.
Best Regards,
- Nir Sever
GigaPixel Corp. Santa Clara, CA
( ESNUG 330 Item 9 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 329 #20 ) Timing Diagram Editors Other Than Chronology's
> Are you aware of any good timing diagram tools other than Chronology's?
> I just want to draw nice timing diagrams for documentation purposes.
>
> - Bruce Nepple
> Imagenation
From: Philip Brown <phil@sei.com>
We use the Synapticad tool (Timing diagrammer or Waveformer). My engineers
love it. And it is cheap. The NT version has a much better GUI than the X
version, but otherwise it is very very easy to use, and produces great
diagrams. It exports to Frame, Word and various image formats. Highly
recommended.
- Phil Brown
SEI
---- ---- ---- ---- ---- ---- ----
From: Ajoy Aswadhati <ajoy@lucidsolutions.com>
Hi John,
I have used Timing Diagrammer from Synapticad a couple of years back. It
will do exactly what Bruce wants. He can download an eval copy from
<http://www.syncad.com>
The name of the tool is waveformer pro.
- Ajoy Aswadhati
Lucid Solutions
---- ---- ---- ---- ---- ---- ----
From: Frank Emnett <frank@aiec.com>
John,
We've been evaluating Datasheet Pro from Synapticad. Their NT version has
many of the same capabilities in terms of defining timing relationships,
plus allows OLE embedding of your timing diagrams in Microsoft Word, etc.,
documents. This makes maintaining large numbers of timing diagrams as
part of a single spec much less of a hassle.
They also support Solaris and HP-UX (haven't looked at either of these).
There are many analysis features also, which is really overkill for our
needs, which seem similar to yours. If you're looking for something cheaper
and simpler, I hope you have better luck than I did in my search, which
turned up empty. Seems like some small software shop who came up with a
simple timing diagram editor (for documentation only, no analysis) which
was a few hundred bucks could sell a reasonable number of them.
- Frank Emnett
Automotive Integrated Electronics Corp. Phoenix, AZ
---- ---- ---- ---- ---- ---- ----
From: Jay Dowling <jay@acut.com>
waveformer pro by synapitcad is a nice waveform editor that has a lot of
bonus stuff, like automatic test bench output and a verilog simulator
- Jay Dowling
CiMatrix Nashua, NH
( ESNUG 330 Item 10 ) -------------------------------------------- [9/99]
Subject: ( ESNUG 328 #1 ) The Final Word On The "Flex-LM Cracked" Story
> Editor's Note: On Wednesday, Sept. 8, the http offering the Flex-LM
> cracking tool completely removed the Flex-LM cracking tool and any
> mention of it. I've done multiple web searches for the specific name
> of this tool and found it nowhere on the net. This Flex-LM cracker had
> been freely available on that site for 4 weeks (since August 6th.) What
> caused it to go & whether it's permanently gone, I don't know. - John
From: Chad Fasca <cfasca@cahners.com>
John,
What may have caused the Flex-LM cracking software to suddenly drop from the
Internet was that Globetrotter alerted the U.S. Commerce Department that
day about the hacker site.
Here's an interesting footnote. Globetrotter says the loophole exploited by
this hack was addressed in 1998. New FlexLM software releases carry a lag
time between initial release and widespread use in the marketplace, the firm
says. Meanwhile, one of your readers said the hack compromised software up
to the most recent release (6.1f). Globetrotter says that the earlier
versions that it tested were not compromised.
There appears to be some discrepancy here.
- Chad Fasca, Editor
Electronic News Today New York, New York
BTW, Aug. 6 (the date the hack was posted) happens to be the same day as the
bombing of Hiroshima (Aug. 6, 1944). Coincidence? Agenda? X-File?
---- ---- ---- ---- ---- ---- ----
From: Alain Raynaud <alain_raynaud@mentorg.com>
John,
The news that FlexLM was compromised is bad news for most EDA companies.
But not for those of us here at Meta Systems. We were smart enough to
deliver all of our software with a dongle. Without this crucial piece of
hardware, our software is totally useless. Oh, and I almost forgot, our
dongle is about 6 cubic meters in size,and weighs about 1 ton. For some
reason, our customers keep referring to it as an "emulator", though we never
can figure out why.
Maybe we should have stick with the concept of "dongle" a long time ago
instead of "emulator". We sure could have saved some lawyers fees. I
guess it's too late now. :-)
- Alain Raynaud
Meta Systems / Mentor Graphics Cedex, France
---- ---- ---- ---- ---- ---- ----
From: David Chapman <dchapman@aimnet.com>
Concerning my FlexLM under Windows 98 question in ESNUG 328; Globetrotter
tells me that it relies on some sort of hardware ID (parallel port dongle
in the worst case, or Ethernet number if a network card is present). I
haven't asked them directly about this hole for Windows 98 -- my contacts
with Globetrotter preceded your alert. They do have an offer on their Web
page which allows a single free FlexLM license for Windows 98, which I will
at least try out, but I am several weeks away from needing it. When I get
to that point I will press them to confirm that the security problem has
been fixed for all platforms, including the low-end ones (at least I don't
have the problem of legacy software like the other vendors.)
Thanks for publishing my request.
- David Chapman
Chapman Consulting Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
> John - what were you thinking?
>
> I don't see the public benefit. I don't see the benefit for EDA vendors.
> I certainly don't see the benefit for you, unless you like the deluge of
> email. And most of all, I don't see any benefit for your users. I don't
> know who, but I'd be willing to bet that some EDA vendor is now going to
> lock down security in a way that is going to severely inconvenience you
> and your readers.
>
> If you honestly believe that publishing a hacker story benefits the
> public, you should publish it. If you believe that doing so on balance
> harms the public or encourage others to harm the public -- you should
> refrain from publishing as a matter of personal integrity -- as I believe
> you would. But please, please, think of the "law of unintended
> consequences" when you publish something like this.
>
> - Matt Christiano, CEO
> GLOBEtrotter Software, Inc. San Jose, CA
From: [ An EDA Vendor ]
John,
That email from the Globtotter CEO is absolutely hilarious. I think you
should nominate him for the pointy hair executive of the year award. If I
were the Silos guys I would be looking to sue globetrotter for damages,
at least for covering the cost of printing new CD's! The interesting
question would be how many EDA vendors were aware of this crack. It does
not appear that many of them had been notified by Globetrotter. Anon pls.
- [ An EDA Vendor ]
---- ---- ---- ---- ---- ---- ----
From: Mike Dini <mdini@dinigroup.com>
John,
Matt Christiano's scathing rebuke of your behavior in the Globetrotter mess
is the peak of hypocritical behavior of software (and related) companies.
We all have gotten use to paying exorbitant prices for testing EDA products
that don't really work, and now we are apparently expected to keep our mouth
shut when a product doesn't work at all. His email message to you in short
says "You shouldn't have reported that our product doesn't work because it
might hurt us". Well isn't that too bad. Sure seems like that once the genie
was out of the bottle then they fixed the problem in a hurry. Also, it seems
as if they weren't up front with all the users of their product about the
security compromise. Could you provide a list of Globetrotter's other products
so that I can avoid them in the future?
- Mike Dini, CEO
The Dini Group
---- ---- ---- ---- ---- ---- ----
From: [ One Of The Paying EDA Customers ]
John,
After your article the other day, I found some detailed instructions on the
web on how to crack FlexLM from a friend at an EDA vendor. It's at
[ URL Deleted ]. It appears to be complete directions for using a piece of
flexLM cracking software. Is this the same software you encountered?
I downloaded the information just in case it disappears and I wish sometime
in the future to check it out. I am not a hacker nor do I think hackers
should be allowed to steal intellectual property. Wonder if the people
doing this hack have use for the software for themselves or just to say
they were able to crack the code?
No, I am not an EDA vendor, but have experienced on a number of occasions
some dreaded message indicating that the system :
- cannot find the LM manager
- cannot find the LM manger server
- The LM manager server is down
- The LM manager server does not recognize something about my use of
the tool
- All copies of the software are checked out and not available
Novice users of software are the main source of the last message. They
somehow manage to leave process windows active that have checked out a
license, but are doing nothing with the license. On one occasion a user
managed to use 18 copies of a simulation license and 9 copies of a
synthesis license. Many other users were blocked and waited for the
problem to be corrected.
On more than one occasion a full day, evening, night, or weekend of work has
been lost due to inaccessible tools where a valid license was purchased.
Oh, to be able to instantly continue work instead of waiting for the system
admin to fix the problem!
These admin problems occur inspite of having redundant license servers, etc.
I didn't write this, OK?
- [ One Of The Paying EDA Customers ]
---- ---- ---- ---- ---- ---- ----
From: Tom Quan <tomq@mondes.com>
Hi John,
I read in Electronic News that you are forming a group to combat security
hacking of EDA software called "StealthNET". Do you have details about the
group? Monterey Design Systems is interested to join.
- Tom Quan
Monterey Design Systems Sunnyvale, CA
[ Editor's Note: Yes, Tom, I'm creating a small, controlled mailing list
of about 20 to 30 security/licensing people from the EDA Vendors with the
idea of exchanging bugs, workarounds, and plugging security holes in EDA
software. It's called StealthNET. (I'm doing it as a goodwill thing in
the industry. Plus, I'm one of the few people who can do this. That is,
I'm a truely neutral party here because of the wide free access I have to
EDA software. Teaching me how to steal EDA tools is like teaching me how
to steal sand. Not much to worry about there.) The only people that
will be on StealthNET will be EDA Vendors that I've physically confirmed
as legit, who have detailed technical knowledge of security issues, and
who are personally more motivated to keep EDA secure than they are to
tell their friends the latest ways of how to crack Flex-LM. - John ]
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