Editor's Note: My heart goes out to the ESNUG readers in Taiwan whose
family and friends are going through the awful Hell of that horrible
earthquake. I hope those of you I've known over the years via e-mail
are healthy and OK. Take care and God bless.
- John Cooley
the ESNUG guy
( ESNUG 329 Subjects ) ------------------------------------------- [9/99]
Item 1: ( ESNUG 327 #2 ) Customers Excited About The Ambit 80% Price Cut
Item 2: ( ESNUG 324 #2 ) Eleven Troubles w/ Simplex 'Thunder & Lightning'
Item 3: ( ESNUG 327 #3 328 #4 ) Metastability 'Z' In Some Xilinx FPGAs
Item 4: ( ESNUG 325 #5 ) Beware Of Verilog Uselib! Linking Takes HOURS!
Item 5: ( ESNUG 325 #1 ) Avanti "Mars Rail" Was Unstable; Has It Changed?
Item 6: ( ESNUG 327 #5 ) How To Get More Than 2 Gig of Memory in DC_Shell
Item 7: ( ESNUG 326 #7 ) Tricking DC 99.05 To Get *Signed* Comparitors
Item 8: ( ESNUG 315 #8 ) Screwy Some/All "*" In PrimeTime Timing Reports
Item 9: ( ESNUG 327 #8 328 #10 ) Fundamental Hole With PGP IP Encryption
Item 10: ( ESNUG 321 #3 ) Token-based VeriLint? No $47K Purchase From Us!
Item 11: Can Anyone Convert Transistor-Level Netlists Into Schematics?
Item 12: ( ESNUG 326 #14 ) Vim Syntax Files For Verilog, Hspice, & Tcl
Item 13: ( ESNUG 324 #4 ) Where Can I Get A Memory Compiler For My Chip?
Item 14: Anyone Have Some PrimeTime Single Or Dual Port RAM STAMP Models ?
Item 15: ( ESNUG 321 #4 ) Extra 'Equivalency Checking' Hoops Not Worth It
Item 16: Seven DC Approaches To Eliminating Timing Violations In Designs
Item 17: Cadence 'Pearl' And Synopsys DC Just *Won't* Play Nice Together
Item 18: HW/SW Co-Design; Comparing Synopsys Eaglei vs. Mentor's Seamless
Item 19: DW Port Name Headaches Recompiling A DC 98.08 Design In DC 99.05
Item 20: What Timing Diagram Editors Are There Other Than Chronology's ?
Item 21: What Do Users Think Of The Revamped Synopsys DesignWare PCI Part?
The complete, searchable ESNUG Archive Site is at <http://www.DeepChip.com>
( ESNUG 329 Item 1 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 327 #2 ) Customers Excited About The Ambit 80% Price Cut
> Synopsys is going to a "new price structure", which is a thinly disguised
> price increase. It may look like you can same money with their "5 year
> deal" which locks you into their tools for 5 years, but read the fine
> print, you don't. Some tools went up as much as 40% ...
>
> I'm being forced to drop some tools, some of which actually had some
> promise, off of maintenance and just go with the core tools to stay within
> my maintenance budget (which is fixed). Is there as much "snarling and
> gnashing of teeth" about this out there as there is here?
>
> - [ Kenny From South Park ]
From: "Ed Beers" <sreeb@doctordesign.com>
John,
I'm surprised that you had no comment in ESNUG on Cadence's Ambit recent
80 percent cost reduction. At $25K, it looks very compelling. Certainly,
convincing my management that they should fork over 10X for the Synopsys
version would be a tricky task if I needed to do it today.
- Ed Beers, Project Manager
Doctor Design Inc. San Diego, CA
---- ---- ---- ---- ---- ---- ----
From: Brian Walkington <bwalk@sdd.hp.com>
John,
You've no doubt heard the news that Cadence has slashed the price of Ambit
BuildGates to $25k. My question is: with Synopsys effectively raising the
price of Design Compiler, and many testimonials that BuildGates is as good
or better than DC, why stay with DC? Is there anything that DC can do that
BuildGates can't?
- Brian Walkington while on contract at Hewlett-Packard
---- ---- ---- ---- ---- ---- ----
From: apm@technologist.com ( Paul Marriott )
Dear John,
I'm an ASIC design and verification consultant currently working for Nortel
in Ottawa and Miranda Technologies in Montreal. I recently saw your remarks
about Cadence 80 percent price cut on Ambit tools in EE Times and wanted to
disagree with what you said. Quote:
"A lot of customers are angry about Synopsys raising prices 20 to
40 percent. Cadence cutting prices by 80 percent is a very clever
tactical maneuver to grab market share." ... "They didn't get
$100,000 for copies of Ambit, I know that. They were practically
giving them away to get customers to use them."
Well, as for Ambit not getting $100,000 per copy, that's not quite true,
since Miranda Technologies in Montreal <http://www.miranda.com> was a
customer who did pay somewhere in that ballpark (though with a discount).
At the time (November of '98), the price worked out at around 20-25 percent
cheaper than a comparably configured Synopsys license. Ambit certainly
wasn't giving seats away, that's for sure!
How we came to purchase those Ambit seats was very colorful.
I was working on a joint project with 3 companies (Miranda included) and a
university in Montreal. We developed a really neat SIMD architecture for
video DSP and we used Synopsys to synthesize it (using an educational
license -- all legal and correct since this was under a Quebec government
program called Project Synergy which was designed to fund pre-commercial
research). At the end of the project, we wanted to build a commercial
version of the architecture we had developed. We planned on spinning out a
company and buying a proper commercial Synopsys license for the synthesis
of this new chip. We approached Synopsys for a quote for a "reasonable"
configuration of tools and DesignWare parts for this.
It was three months before Synopsys would even return calls. Then they
started going to people who'd left the project, revealing confidential
information to them and trying to get them to say that we'd been using an
illegal license all along and making vague threats about a university in
Montreal going to be prosecuted for such a violation.
All of this was very underhanded.
I was extremely annoyed that they had revealed some confidential details of
our RFQ to a former employee of the project. Finally, when they did give us
a quote, they said that the license could only be used **for one specific
project** and they would take legal action if we used it for anything else.
I thought this was pretty dubious, to say the least. I think they were
paranoid that we would try and use educational seats for the work ( which
really makes no sense since if really had wanted to do that because we
wouldn't have been trying to spend upwards of $100k with them in the first
place then!) Needless to say, I was less than impressed with their sales
tactics. It seemed that they really weren't interested in doing business
with a small company. (Big hint for Synopsys sales people: all companies
start out small).
Around that time, I decided to take a look at the Ambit tools to see if
they were good enough to compete. They were more than happy to give me
evaluation licenses, sent up FAEs and generally behaved like decent people.
Our spin-off never happened (for various other reasons, though the Synopsys
stuff didn't help), and I ended up going to work full time for Miranda,
starting up an ASIC group. Miranda then followed my advice and bought an
Ambit seat (at full price minus a discount that I negotiated). At that
time, Ambit had just been purchased by Cadence, but they honoured the price
I'd negotiated prior to the take over.
Working for a small company, it was frustratingly difficult to get any
quote at all from Synopsys, whereas Ambit were more than happy to take my
business. I've been impressed with the technical support since and the QOR
I'm getting is very close to what I was getting with Synopsys for similar
designs previously.
It's also quite refreshing to be able to speak to the Ambit person who
actually wrote the code when there was a problem or two to solve.
With this recent 80 percent Ambit price cut, I was worried that I would be
stuck with overpriced licenses, but my Ambit sales representative has given
me a great deal (which I can't reveal here) to make up the difference and
allow me to use the distributed synthesis capability of the new Envisia
version of Ambit. I was also worried that the Cadence take over would mean
less support for small accounts like Miranda's, but so far this hasn't been
the case at all.
One final point, since Ambit fully supports VHDL-93 constructs, it is _much_
easier to integrate RTL code with existing VHDL-93 coded testbenches rather
than having to jump through some of the hoops I've had to in the past
because of Synopsys being stuck in the dark-ages with VHDL-87.
I'd quite like to see more Ambit-related discussion on ESNUG -- perhaps the
"S" should really be Synthesis rather than Synopsys?
- Dr. Paul Marriott
Marriott Design Services Montreal, Canada
( ESNUG 329 Item 2 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 324 #2 ) Eleven Troubles w/ Simplex 'Thunder & Lightning'
> I saw there were couple of references to Simplex's Power analysis tools
> 'Thunder & Lightning' in your DAC'99 Trip Report. I have been working
> with them for around an year now and I couldn't resist from commenting.
>
> * It has too many command/scripts/tools to do the required analysis
> For e.g., If I were to do static IR analysis, I will have to go
> through a run of at least 12 steps (which includes generation/running
> of various scripts and tools)
>
> * It uses many mystical or hard-to-understand the scripts/command files.
> Generally, I just copy the old command file (which has a lot of Pascal
> type statements). I just modify the new GDS design cells and couple of
> file names without really having any understanding of the effect of
> other statement in the command file. (In fact, that's what the Simplex
> staff recommends.)
>
> ...
>
> You will need lot of hand-holding from Simplex's support to work with
> their 'Thunder & Lightning' power tools.
>
> - Anil Kumar
> Vitesse Semiconductor Corp. Camarillo, CA
From: [ Us, Too! ]
John,
I agree with all of Anil's statements, especially concerning the user
interface. I've heard they've improved it recently, but not much. The
core algorithm of Simplex might be swell and dandy, but I'd personally
prefer a slightly less accurate tool that had a friendlier, less *complex*
user interface. There's no reason that the first-time user should be
concerned with implementation details like the number of "stripe" files,
all the various intermediate file formats, or the many command-line options
on their "unsupported" (but very necessary) perl scripts. I had to spend a
considerable amount of time creating my own do-everything script to simply
input GDS and output a parasitic netlist. Another flaw: it doesn't handle
intentional resistor devices very well. I need to jump through hoops to
remove resistors from the layout and LVS netlist, which can lead to missing
capacitances on nodes that only have resistor connections.
The worst part is that Simplex uses our company name in its advertising,
claiming how much we love it. Keep me anonymous please.
- [ Us, Too! ]
( ESNUG 329 Item 3 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 327 #3 328 #4 ) Metastability 'Z' In Some Xilinx FPGAs
> Metastability 'Z' is no more of an issue in an FPGA than it is anywhere
> else. For Xilinx FPGAs, Greg's comment about lookup tables is incorrect.
> I don't know the situation for other vendors.
>
> The way it works is as follows:
>
> Let's assume that we have a 4 input LUT, implementing a 2 input and gate.
> Of the 4 inputs (address lines to the lut), two are grounded (i.e. never
> change) and the other two select 1 of four locations. The locations
> depend on which two address lines are used. Of the 4 locations that are
> interesting, three are set to '0', and 1 is set to '1'. Unlike RAMs or
> other memory structures with word lines, bit lines, sense amps,
> pre-charge, and other entertainment, the LUTs are implemented as latches,
> 16 of them. They then connect through a tree of pass transistors to the
> output.
>
> Regardless of which single input is changing, only 2 of the pass
> transistors in the tree are involved in the change over from one value to
> the next. Since the outputs of all the 16 latches have propagated through
> the tree as far as they can, when you change over from one location to
> another (with only 1 address line changing), and both have the same value,
> the transition does not cause a glitch in the output.
>
> If you care, you can see this structure on page 4 of:
>
> http://patent.womplex.ibm.com/cgi-bin/viewpat.cmd/US04870302__
>
> Clearly, if both inputs are changing, a glitch could occur, but then the
> same is true of a real AND gate.
>
> Although my example is for a 2 input gate, the same is true for 3 or 4
> input structures that are mapped to a LUT. The basic rule is that if
> only one input is changing, and both the before and after values are the
> same, no glitch can occur.
>
> While somewhat more difficult to describe, it can be shown that for
> structures like a 3 or 4 input AND gate, with one input held low, you can
> have multiple of the remaining inputs changing simultaneously, and not
> get glitches in these situations either.
>
> - Philip Freidin
From: Greg Dean <Greg.Dean@nsc.com>
Hi, John,
The Xilinx circuit Philip refers to uses a tree of NMOS pass transistors
forming a 16 to 1 multiplexor to do the selection for the lookup table.
Indeed this configuration is able to safely implement an AND or NOR (one
input can select between two lows without glitching). However, when
switching between two highs (as in a OR or NAND gate), the output may
glitch low, especially if the input is near threshold for an extended
period of time, such as when the input comes from a metastable latch.
Consider the following section of the circuit. With the A input in the
center of the inverter's threshold (assume VDD/2), the output, A# is also
at VDD/2. This puts OUT at VDD/2 - Vth, which is below the threshold of
the buffer, and so OUT_buf is low.
A -------+---|>o----+ A#
| |
_|_ | OUT
VDD ----------------)------+-------|>--- OUT_buf
| |
_|_ |
VDD -----------------------+
There are other (off) transistors not shown connected to OUT which
contribute some leakage current to this node to pull it down.
In normal usage, this should not be a problem, as stored charge on OUT
should hold its voltage while the A input quickly switches through this
region of operation.
- Greg Dean
National Semiconductor South Portland, ME
( ESNUG 329 Item 4 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 325 #5 ) Beware Of Verilog Uselib! Linking Takes HOURS!
> The first problem I had was that Verilog-XL would try to build the
> support ASIC out of vendor A's library components instead of vendor B's
> library. I was able to solve this problem using the `uselib directive ...
>
> - Greg Arena
> Dialogic Corporation Parsippany, NJ
From: "Paul.Zimmer" <paul.zimmer@cerent.com>
Beware of uselib. We were using it for a while, then discovered that
it made the linking take HOURS during gate simulations (as opposed to
minutes for good-ol' -y). My guess is that uselib was causing us to
troll through the whole search path every time XL had to link a module.
- Paul Zimmer
Cerent Corp.
( ESNUG 329 Item 5 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 325 #1 ) Avanti "Mars Rail" Was Unstable; Has It Changed?
> In the Avanti P&R system you can add numerous options. These include
> HPO (high performance option), power analysis (Mars Rail), physical opto
> (Saturn), cross-talk (Mars Xtalk), and timing driven. They utilize the
> flexlm licensing so each of these options have a unique set of tokens
> associated with each of them.
>
> - [ The Man In The Iron Mask ]
From: [ A Little Bird ]
Hi John,
Concerning Mars Rail (i.e. the power/reliability tool from Avanti), I heard
from our CAD support team that they evaluated it sometime back and the tool
was not very stable. Don't know the details. Maybe your readers know more
now? Anon please.
- [ A Little Bird ]
( ESNUG 329 Item 6 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 327 #5 ) How To Get More Than 2 Gig of Memory in DC_Shell
> Does anybody know ALL the requirements to get dcshell to not crash when it
> wants to allocate more than 2 Gigabytes of memory? Running on Solaris 2.7
> with 'datasize' unlimited. Does the LD_LIBRARY_PATH environment variable
> have to contain /usr/lib/sparcv9?
>
> - Don Monroe
> Tenor Networks Acton, MA
From: Don Monroe <don_monroe@tenornetworks.com>
John,
I know you're a big fan of follow-up, so here's my follow-up on this.
After some exchanges of e-mails and some research, the Synopsys AE finally
came up with the "magic" to get a dc_shell job to use more than 2 Gigs of
memory. For a C-shell environment you have to set the following limits:
limit memorysize 14000M
limit datasize 14000M
limit stacksize 512M
Leaving then set to 'unlimited' doesn't work. The actual value you set is
obviously swap space dependent. This worked on Solaris 2.6/2.7 Suns.
- Don Monroe
Tenor Networks Acton, MA
( ESNUG 329 Item 7 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 326 #7 ) Tricking DC 99.05 To Get *Signed* Comparitors
> I'm having trouble synthesizing signed arithmatic from Verilog. I thought
> converting everything to integers would do the trick since integers are
> defined in Verilog as 32-bit signed values. However Design Compiler 99.05
> creates unsigned comparators when I compare two integers. Of course, I
> can instantiate a signed DesignWare comparator, but I hate to do that
> since that makes the Verilog code tool dependent. The thing is that the
> Synopsys VCS simulator handles integers correctly as signed. When I check
> the HDL Compiler for Verilog Reference Manual, it says on page 4-6; "All
> comparisons assume unsigned quantities", apparently regardless if it
> compares integers or regs. How do I force DC to synthesize a *signed*
> comparator without instantiating or writing my own comparison functions?
>
> - Menno Spijker
> Mitel Semiconductor Kanata, Canada
From: Menno Spijker <menno_spijker@mitel.com>
Hi John,
An old collegue in the Netherlands, Rob van der Valk, gave me a hint on
how to do the signed comparisons after he saw my letter in ESNUG. The
trick is to invert the MSB's of the operands and do an unsigned
comparison on that.
So instead of:
op_a[n:0] > op_b[n:0]
do:
{~op_a[n],op_a[n-1:0]} > {~op_b[n],op_b[n-1:0]}
That's easier and smaller in logic than the functions I wrote.
- Menno Spijker
Mitel Semiconductor Kanata, Canada
( ESNUG 329 Item 8 ) --------------------------------------------- [9/99]
From: "Paul Zimmer" <paul.zimmer@cerent.com>
Subject: ( ESNUG 315 #8 ) Screwy Some/All "*" In PrimeTime Timing Reports
John,
I just got bit AGAIN by this problem, so I want to blow off some steam by
complaining about it publicly AGAIN. Both DesignTime and PrimeTime use a
"*" in the timing report to indicate:
"some or all of the timing is backannotated"
The problem is, there's a HUGE difference between SOME of the timing being
backannotated and ALL the timing being backannotated.
After I read in the SDF, I expect ALL the timing to be backannotated, and I
want to *know* if something isn't. Why can't Synopsys use "*" for the
current "some or all", but use something like "+" for ALL.
The particular problem that tripped me up might interest ESNUG readers
as well. In the Verilog world, there exists a net that connects the
top level module ports (your pins) to the pad input/output/io pins.
I guess this corresponds physically to the bond wire.
Anyway, the timing on this net should be zero. Unfortunately, most vendor
SDF files don't annotate this net, so DT/PT will estimate the delay using
wireload models. If you do a report using report_timing without any special
switches, this delay will hide quietly inside the number reported for the
pad timing, and you'll never know. Since SOME of this number is from the
SDF (the timing through the pad), you'll see a nice, healthy-looking "*"
next to the number in the report, and you may spend ages trying to fix the
timing on a path that's actually OK.
If, however, you use the "-input_pins" switch, the two pieces will be
separated and you'll see the estimated timing of this net without the
"*" next to it.
Some ways around this problem:
1) Force the wireload model to be low or non-existent.
2) Do a "set_annotated_delay 0.0 -net..." across this net. This is what
I was doing, but it wasn't working correctly because there was a level
of hierarchy in the way.
3) Do "set_resistance 0.0" on this net, and maybe a set_load 0.0 as well.
4) Hack the SDF file (Perl to the rescue!) to put these paths in.
5) Beat on your vendor to fix their tools to put this number in the SDF.
6) Use some magic DesignTime/PrimeTime switch that I don't know about???
These workarounds are fine for the specific problem of hidden net delays on
input pins, but only Synopsys can fix the fundamental problem of unannotated
timing hiding behind annotated timing!
"Some or all" indeed!
- Paul Zimmer
Cerent (uh, I now mean "Cisco")
( ESNUG 329 Item 9 ) --------------------------------------------- [9/99]
Subject: ( ESNUG 327 #8 328 #10 ) Fundamental Hole With PGP IP Encryption
> PGP uses "Public Key Encryption" rather than the traditional "Private
> Key" mechanism. Rather than having a single key for the document, the
> PGP uses two keys: 1 public and 1 secret. Data may be encrypted with
> either key, and decryption requires the opposite key.
>
> - David Black
> Qualis Design Austin, TX
From: [ Play It Again, Sam ]
John,
There's an important issue related to IP encryption which hasn't been
addressed. We have determined that since users cannot be trusted, the key
has to be embedded into the tool. We are also saying that not all tool
vendors can be trusted with the key... The reality is that a tool vendor
doesn't even need a key to steal the IP! Remember, the tool always needs
to read the decrypted source. And no one can prevent a tool vendor from
making the tool write out a decrypted IP. The vendor could, for example,
trigger the 'write' based on some secret command line option!
This problem can't be solved by using an encryption scheme, but nevertheless
needs to be dealt with before IP encryption can used effectively.
Assuming this problem doesn't exist, and the tool vendor cannot be trusted
with key, an alternative encryption scheme would be to split the key between
the tool vendor and the user. (i.e one portion of the key is embedded in
the tool, and the other portion is with the user.) This way neither of them
can steal the IP on their own.
- [ Play It Again, Sam ]
P.S. John, if you decide to publish this, please keep me anonymous.
( ESNUG 329 Item 10 ) -------------------------------------------- [9/99]
Subject: ( ESNUG 321 #3 ) Token-based VeriLint? No $47K Purchase From Us!
> "EDA Mall introduces a new concept, Session-Based Licensing. With
> either a Credit Card (Available Now!) or a Purchase Order Account,
> you can purchase the number of Verilint or VHDLlint licenses you need,
> when you need them." ( http://www.interhdl.com )
>
> - from http://www.edamall.com , the new Avant! website selling
> Verilint at $10 per use, announced at DAC.
From: [ Lint Free For Me! ]
John, keep me anon.
The VHDL-Lint issue is one I had to review for my company. According
to my calculations, we can run the tool many times using the token-based
system for the same cost as the Avanti maintenance. So, I have told our
Avanti salesdroid that we are not going to upgrade. Now, I am upset by
being sent a form to fill in to decline their 'offer'. Strangely,
sending a reply email to decline their offer is low on my priorities.
We have an internal tool which makes many design rule and coding checks
on our RTL code, so we can use this and just use VHDL-Lint for final
checks. Any advice on whether and how we could make money selling our
own tool (we are not an EDA company, so creative suggestions are required).
On the flip side, I am amused by seeing Avant! buying a formal equivalency
checking company, Chrysalis. Didn't they have their own EC tool when they
bought Compass?
- [ Lint Free For Me! ]
( ESNUG 329 Item 11 ) -------------------------------------------- [9/99]
From: Andrew Frazer <Andy.Frazer@idt.com>
Subject: Can Anyone Convert Transistor-Level Netlists Into Schematics?
John,
Has anyone ever heard of a tool that can convert a transistor-level SPICE
netlist into a schematic? We thought about making a dummy library in Library
Compiler and then converting the netlist into verilog then reading it in to
DC, but there has to be a better way. Any ideas would be appreciated.
- Andy Frazer
Integrated Device Technology Santa Clara, CA
( ESNUG 329 Item 12 ) -------------------------------------------- [9/99]
Subject: ( ESNUG 326 #14 ) Vim Syntax Files For Verilog, Hspice, & Tcl
> I am looking for vim syntax files for dc_shell (script and log) and
> others EDA tools syntax files.
>
> - Benoit Durand
> STMicroelectronics
From: Jeff Solomon <jsolomon@stanford.edu>
John,
I don't have a Vim syntax file for .synopsys stuff. But I do have special
Vim syntax files for Verilog, Hspice and Tcl. You may be interested in the
tcl file because Synopsys uses tcl now.
I've put together a little webpage about my vim config:
<http://www-flash.stanford.edu/~jsolomon/vim/>
Good luck.
- Jeff Solomon
Stanford
( ESNUG 329 Item 13 ) -------------------------------------------- [9/99]
Subject: ( ESNUG 324 #4 ) Where Can I Get A Memory Compiler For My Chip?
> Talk to your local ASIC vendor like LSI or IBM as a start. Memory
> compilers are typicaly a vendor supplied tool unless you are doing COT
> or Full Custom design in which case your vendor will probably suggest
> which memory compiler(s) to use and where to get them.
>
> - Tom Dejanovic
> Cisco Systems
From: Richard Knight <knightrd@concentric.net>
John,
We sell a number of custom design related products:
MAX, SUE, MCC, DPC
- Layout, Schematics, MegaCell & DataPath Compilers
MaskCompose
- Automated Frames, Jobdeck, Completed Mask/Fab Paperwork
- Mix & Match Reticles
- Clustering, Wafer Map, etc...
QuickView (Hierarchical Speed)
- View: GDS, MEBES, Jobdeck, SEM, Hitachi
- XOR ant number/combination of formats
Chameleon
- OPC, MRC, DRC, LVS, Fracturing, Parasitics
Our website <http://www.shearwater.com> gives the details.
- Richard Knight, Exec. VP
Shearwater Group Vashon Island, WA
( ESNUG 329 Item 14 ) -------------------------------------------- [9/99]
From: Jonathan Park <jpark@viper.chipx.com>
Subject: Anyone Have Some PrimeTime Single Or Dual Port RAM STAMP Models ?
John,
I am looking for examples of Stamp models ( for PrimeTime ) for Synchronous
Single port and Dual port RAMs. Can anyone help in getting this models ???
- Jonathan Park
Chip Express Gaithersburg, MD
( ESNUG 329 Item 15 ) -------------------------------------------- [9/99]
Subject: ( ESNUG 321 #4 ) Extra 'Equivalency Checking' Hoops Not Worth It
> On the flip-side -- there are capacity problems -- but not as bad as you
> suggest. Equivalence checkers work hierarchically, so large designs
> aren't a problem if they have matching hierarchy. The main problems are:
>
> - RTL to gates if there is not matching hierarchy. But flow can solve
> this. Use an RTL to hierarchical-gates proof, then a hierarchical to
> flat gates proof,
>
> - RAM's remain hard. We still use simulation to do this, but we will
> probably start to use symbolic simulation pretty soon.
>
> - large arithmetic blocks are also hard. Most equivalence checkers
> run out of steam on RTL-gates at around 17 or 18 bits.
>
> - re-timed designs and duplicated logic (e.g. duplicating state for
> physical considerations) can cause problems.
>
> and of course there may be others that I don't see.
>
> In conclusion, equivalence checkers are pretty mature now and are being
> used by a lot of companies on a lot of designs. Currently ST has about
> 10 on-going designs that use Formality as part of their flow with only
> a few problems.
>
> - Mike Bartley
> STMicroelectronics Bristol, UK
From: Don Mills <mills@lcdm-eng.com>
But, Mike, these items "On the flip-side" I consider much more constraining
then you make them out to be. Maintaining hierarchy between RTL and GATE
is often much harder to do then just following a flow. I have often been
constrained to make hierarchy changes just to accommodate EDA and Foundry
tool requirements. The hoops I have to jump through are for Foundries
are tough enough without added additional tools with additional hoops.
Additionally, my designs have been RAM and arithmetic based. From my
perspective and yours, formal tools have many constraints that need to be
met to be used and are not applicable in some cases -- like the ones I have
been associated with.
- Don Mills
LCMD Engineering South Jordan, UT
( ESNUG 329 Item 16 ) -------------------------------------------- [9/99]
Subject: Seven DC Approaches To Eliminating Timing Violations In Designs
> Synopsy dc is not able to meet the timing constraints on a design. After
> analysis, we found that synopsys selects the slowest architecture for the
> design ware (multiplier and adder) rather than the fastest. The design is
> really simple. About 40,000 gates, a single clock feeding all registers.
>
> No problems: check_timing and check_design commands report nothing.
>
> Synopsys version is 99.05. I know that we can select manually the
> architecture for the design ware (set_implementation) but it is tedious.
> Do you have an idea to solve that problem.
>
> - Jean-Marc Allard
From: Predrag Markovic <dmpeca@eunet.yu>
Hello Allard,
Well, you have a lot of options. Their values depend strongly of the type of
design. Generally, I would try the following (not in the given order).
1) Try to exclude (set_dont_use) slow cells from ASIC foundry library.
The foundry usually compile a zillions of cells for DC that you not
need. This number of cells creates enormous design (mapping) spaces
for DC that can not be solved (NP bounded). Look at your timing
report and find the cells with unreasonable high delay for the given
technology. set_dont_use and repeat compilation.
2) Try incremental compiling i.e. compiling in "two rows", second
with this switch.
3) At some level of hierarchy apply boundary_optimization. That could
be extremely effective, particularly if you have applied bottom up
approach compiling your design. If you have some "unreasonable"
buffers in you design introducing delay that will be very effective.
Where in within the chip hierarchy to apply boundary_optimization
is difficult to say. Sooner is better than latter.
4) Try to identify the critical path and apply 2) and 3).
5) Analyze the fan out of the nets. set_max_fanout to smaller number
can help also.
6) If you have used operator inferencing (and BOA) in you HDL code rather
than DW component instantiation than change HDL code to use DesignWare
component instantiation. This can give better DC results in some cases
and give you much better control during the synthesis.
7) Keep the number of gates in current_design for compile command to up
to a few thousand.
Other options could be tedious as you said. Hmm... maybe set_implementation
is not so tedious as it looks like.
- Predrag Markovic
DMPECA Belgrade, Serbia
( ESNUG 329 Item 17 ) --------------------------------------------- [9/99]
From: Eran Rotem <eran@chipx.co.il>
Subject: Cadence 'Pearl' And Synopsys DC Just *Won't* Play Nice Together
Hello John,
First I would like to thank you for your column, it is helpful, colourful
and very interesting.
I would like to ask a question. We, Chip Express are an ASIC vendor. We
are now in the process of developing a layout flow that is using Timing
Driven Q-place placement software from Cadence. Being timing-driven, the
software reads constraint files produced by, you guessed it -- Synopsys.
The tool that reads and converts the constraint file is: Pearl (Cadence
static timing analysis tool). We are receiving Synopsys constraint files
from various Synopsys versions. Almost each time we use Pearl there are
statements that are not recognised by the tool, and causes it to produce
erroneous output.
The only thing we can do is manually change the constraint file, and try
again. As I said , we get different "types" of constraint files, depending
on the Synopsys version used. Does anyone know of a formal / informal way
to overcome this problem ?
- Eran Rotem
Chip Express (Israel) Ltd. Haifa, Israel
( ESNUG 329 Item 18 ) -------------------------------------------- [9/99]
Subject: HW/SW Co-Design; Comparing Synopsys Eaglei vs. Mentor's Seamless
> Transwitch is interested in opinions on Seamless (Mentorgraphics) and
> Eaglei (Synopsys). Comments / Comparisons urgently needed.
>
> - Somnath Mukherji
> Transwitch
From: crad@ihgp2.ih.lucent.com ( Conrad Herse )
I've been using Seamless for sometime now (never used Eaglei, though I've
seen a foil presentation on it). Like any complex tool Seamless does have
an occasional "anomaly", but overall I've found it to perform pretty much
as advertised. The learning curve is not too painful, it does support some
special things I've needed (like memory ECC), and performance has been
acceptable. I've also been happy with the support I've been getting from
Mentor. I see no immediate need to switch to a new tool at this time.
I've also seen growing interest in the capability as it starts to prove its
value.
Of course it ain't cheap, but what's the value of hitting your market
window ....
- Conrad Herse
Lucent
---- ---- ---- ---- ---- ---- ----
From: John Cooley <jcooley@world.std.com>
Got this from the SNUG'99 Trip Report of March this year:
"We saw a real need for HW/SW co-design. We had the Mentor Seamless
and Synopsys Eaglei guys come in to pitch their tools. As a test,
we set up two teams in house using both tools. Each team consisted
of two HW engineers and one SW engineer. For a few weeks, they used
either Eaglei or Seamless to develope a PowerPC based testbench. We
then had each team switch to using the other tool. In the end, the
two tools were very close but our conclusion was to choose Mentor
Seamless because it was more mature, it allowed granular and dynamic
optimization control of memories, they had working Denali memory
models (Synopsys MemPro was yet unworkable), and it ran on HPUX
(Eaglei only runs on Suns and we're a HP house.) Price was a
non-issue because they were so close."
- Hugh Blair of Honeywell Space Systems
Hope this helps.
- John Cooley
the ESNUG guy
( ESNUG 329 Item 19 ) -------------------------------------------- [9/99]
From: johne@vcd.hp.com (John Eaton)
Subject: DW Port Name Headaches Recompiling A DC 98.08 Design In DC 99.05
I am recompiling a design I did with DC 98.08 using DC 99.05 and am
encountering a strange bug. Certain designware modules that used to have a
port name or .A now get the name ./A_BAR [6]. Is there a workaround that
easier than pulling up the gates files and hand editing it?
- John Eaton
Hewlett-Packard Vancouver, Canada
( ESNUG 329 Item 20 ) -------------------------------------------- [9/99]
From: "Bruce Nepple" <brucen@imagenation.com>
Subject: What Timing Diagram Editors Are There Other Than Chronology's ?
John,
Are you aware of any good timing diagram tools other than Chronology's? I
just want to draw nice timing diagrams for documentation purposes.
- Bruce Nepple
Imagenation
( ESNUG 329 Item 21 ) -------------------------------------------- [9/99]
From: David Peeters <peeters@entridia.com>
Subject: What Do Users Think Of The Revamped Synopsys DesignWare PCI Part?
Has anyone successfully use the DWPCI MacroCell from Synopsys? Was it
compliant with the relevant specifications? What were the implementation
issues? How did you handle the I/O timing (PLL, etc.)? Thanks for any
information you can supply.
- Dave Peeters
Entridia
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