> From: Ron Goodstein <rongood@world.std.com>
>
> John,
>
> When is your big summer bash at the Poor Farm this year? The summer is
> running out and you haven't announced when it is yet, John.
>
> - Ron Goodstein
> First Shot Logic Simulation Waltham, MA
Editor's Note: For those who don't know, I write ESNUG on an old 386
33 Mhz computer on a sheep farm that's about 45 minutes west of Boston.
And every year, my landlord on the farm has held an ever growing annual
'SheepStock' party in the back pasture. Last year we had six bands
play, about 200 people camping in tents, and (from the police report)
over 1,000 people attended the party throughout the day. The problem is
that it has grown too big. Twelve underage kids were arrested last year
for trying to smuggle in beer and it made the local newspapers. Even
the FM radio stations had staff members commenting on various 'colorful'
personal stories they experienced while "on the farm" -- no riots nor
big fires, but there was a haunting similarity to how the media covered
the recent "Woodstock'99" now and how our "SheepStock'98" was covered
then. So, seeing this party as a blight on their sleepy, whitebread
suburb of Boston, the Holliston Police Department decided this year to
deny the permit for "SheepStock'99" to be held. Sorry, Ron.
- John Cooley
the ESNUG guy
( ESNUG 325 Subjects ) -------------------------------------------- [8/99]
Item 1: ( ESNUG 324 #1 ) Avanti Timing-Driven P&R Clashes w/ Synopsys Use
Item 2: Cadence Offering A Free Beta DFII SKILL Tabulator (Lint) Program
Item 3: A Grad Student's Request For Some Sample Hierarchical GDSII files
Item 4: Ver. 99.7 of the NSCU Cadence Design Kit Is Now Available For Users
Item 5: SDF Annotate Verilog-XL Issues w/ Mixing Two ASICs From Two Vendors
Item 6: Differences w/ ViewLogic FPGA Express vs. Synopsys FPGA Compiler II
Item 7: ( ESNUG 319 #6 ) Modelsim & VSS VITAL SDF Lib DC 99.05 Conflicts
Item 8: ( ESNUG 321 #10 322 #5 ) A Module Compiler Trick Synopsys AE's Hide
Item 9: ( ESNUG 324 #14 ) Some Useful Dc_shell & Makefile Vim Syntax Files
Item 10: ( ESNUG 324 #6 ) Measuring Toggle Of A Signal In A VCS Simulation
Item 11: How To Convert Synopsys DC .lib Files To Cadence/Ambit ALF Files
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 325 Item 1 ) ---------------------------------------------- [8/99]
Subject: ( ESNUG 324 #1 ) Avanti Timing-Driven P&R Clashes With Synopsys Use
> Recently there were some disgruntled Avanti customers complaining about
> Avanti licensing procedures in ESNUG. I just thought I'd add to this
> discussion by letting everyone know this creative licensing isn't just
> reserved for their HDL RTL tools.
>
> In the Avanti P&R system you can add numerous options. These include
> HPO (high performance option), power analysis (Mars Rail), physical opto
> (Saturn), cross-talk (Mars Xtalk), and timing driven. They utilize the
> flexlm licensing so each of these options have a unique set of tokens
> associated with each of them.
>
> - [ The Man In The Iron Mask ]
From: "Manish Shrivastava" <manish@ieee.org>
Hi John,
Recently I heard a term called Power driven layout and I literally laughed
at the people who told me that. But after reading this ESNUG I think I
should have not done that. It looks like Avanti does support some kind
of Power analysis built into the tool. But does this mean that Avanti
can support some kind Electromigration / IR drop driven layout?
Does this also mean extra effort on Libraries to be characterized?
Currently, we just use the Timing Driven feature of Avanti P&R and it
turned out to be a nightmare because our frontend designers love the path
segmentation feature of Synopsys and they create a false path from any
point to any point by just creating a hierarchy there. Then when you go to
the Avanti backend tool you have to dig out each net, or cell Input/Output
and tell it to disable timing through it. OK, it is similar to doing it
in the front end, but then you have hierarchy in front end, and a flattened
verilog netlist at the backend.
I hope the Avanti Static Timing Analysis tool can start supporting something
more then just the CLK pins / input ports and D pin of FF / output ports for
its start and end points.
Oh, I would like to share a trick with everyone, may be people know about it
already. To break a path through the bidirectional ports in your design,
you can now happily use the -through option in Synopsys. What you need for
Avanti is just to find the instance name of the tristate driver and the
input side buffer and use the command tdfSetDisableTiming ( output of
tristate buffer, input of the input side buffer ) and you have a false path
set for breaking the false loop. But beware, not related to above but to
bidi port, never declare a port as bidi unless you are driving and
recieving data -- else Avanti just removes a bidi port with connection to
one direction only from your slack graph.
- Manish Shrivastava
( ESNUG 325 Item 2 ) ---------------------------------------------- [8/99]
From: john@cadence.com (John Gianni)
Subject: Cadence Offering A Free Beta DFII SKILL Tabulator (Lint) Program
John,
There's a lint-like DFII SKILL Tabulator (beta verson) available for Cadence
customers to obtain by:
/usr/ucb/mail -s "send skillTab.il" swap@cadence.com < /dev/null
Once you obtain that beta SKILL Tabulator, start DFII (any release):
icfb &
Load & run the beta SKILL Tabulator:
load("skillTab.il")
sseTabulateSKILL()
And, please send me the results:
mail -s "skillTab.out" john@cadence.com < skillTab.out
You'll be amazed that we can then tell you:
- Every function you are using (yours or ours) and how many times
- Which ones are mis-spelled or otherwise undefined dependencies
- Which ones are changed or deleted in all recent DFII releases
(even future releases)
- What the changes (usually positive) are & how to recover
- How long it might take to recover
And, with the actual SKILL code:
- Super SKILL Lint scores for every file, graded from best to worst
etc.
I urge your Cadence ESNUG readers to check out this beta test software and
let us know what they think.
- John Gianni
Cadence Design System, Inc.
( ESNUG 325 Item 3 ) ---------------------------------------------- [8/99]
From: Jayesh Laddha <laddhjj@eng.auburn.edu>
Subject: A Grad Student's Request For Some Sample Hierarchical GDSII files
I would greatly appreciate if someone can send me some GDSII files which
contain data in a hierarchical manner. That is, it should contain say some
circuit elements which are replicated some number of times in the X and Y
directions. Presently, I have GDSII files which are in the flat format and
am interested in trying to deal with GDSII files which contain data in the
hierarchical format.
- Jayesh Laddha
Auburn University
( ESNUG 325 Item 4 ) ---------------------------------------------- [8/99]
From: Toby Schaffer <jtschaff@eos.ncsu.edu>
Subject: Ver. 99.7 of the NSCU Cadence Design Kit Is Now Available For Users
John,
We are pleased to announce the availability of version 0.99.7 of the North
Carolina State University Cadence Design Kit (NSCU CDK). This patch has
lots o'stuff; the major additions and changes are:
- overhaul of Diva capacitor extraction to use multiLevelParasitic();
size of extraction rules files is reduced by factor of four
- compliance with SCMOS User's Manual 7.3
- parasitic capacitances for TSMC 0.3um
- wirebond pads and updated transistor models for Supertex (formerly
Orbit) 2.0um
- high-resistance implant layer for AMI C5N
There are other changes, fixes, and updates as well. A complete changelog
is at http://www.ece.ncsu.edu/cadence/CDKpatches.html .
What is the NCSU CDK?
---------------------
The kit focuses on providing a flow for full-custom IC design through MOSIS,
including schematic entry, Verilog digital simulation, analog circuit
simulation, layout DRC checking and device extraction, and mask generation.
It supports 4.4 and is not backward compatible with 4.3.x. All SKILL code
is available as source in a fairly-well organized fashion.
The CDK homepage is http://www.ece.ncsu.edu/cadence/CDK.html .
The tools used are Virtuoso, Composer, Analog Artist, DLE and Diva.
In particular, the kit features:
+ support for all MOSIS SCMOS processes/layers, including process-dependent
layers
+ Diva verification: DRC (all rules from SCMOS User's Manual 7.3),
extraction (MOSFETs, high-voltage MOSFETs, cwell/m1-poly/polycap/inter
-metal/parasitic capacitors, vertical NPN BJTs, diodes, poly/poly2
resistors), and LVS
+ layermaps for MOSIS CIF/GDSII import/export
+ Composer with interface to
* HSPICE/Spectre through Analog Artist, with MOSIS-provided
transistor models in place
* Verilog with technology-independent parts
+ technology-independent libaries for analog (eg, RLC, transistors) and
digital (eg, gates) parts. These parts have SKILL code hooked in to
enforce sizing and grid rules (eg, minimum width/length, half-lambda
grid), automatic transistor model selection depending on technology,
and drain/source area/perimeter estimation.
+ technology libraries (ie, one library for every MOSIS SCMOS process)
with parameterized layout cells setup for both manual use and layout
synthesis via DLE
+ MOSIS wirebond pads (Supertex 2.0um; HP 0.4um, 0.6um; AMI 1.2um)
+ various user-friendly GUI enhancements
* simplified library creation and technology file attachment for
MOSIS technologies
* enhanced label creation (Virtuoso)
* click on any object to print info about it in the CIW
* ability to align layout objects (Virtuoso)
* ability to insert likeness of JPEG images into layout (Virtuoso),
(useful for signing, or putting drawings or photos on, chips)
+ documentation of all customizations in either HTML or OpenBook format
A few things the kit does NOT expressly provide support for:
- it doesn't do P&R
- it doesn't provide a standard cell layout library
- it doesn't do digital timing analysis
- it doesn't do parasitic resistance extraction
At present, the CDK needs to be installed $CDS_DIR/local, so the installer
will probably require sysadmin-type permissions, although this will
hopefully change in the near future.
- Toby Schaffer
North Carolina State University
( ESNUG 325 Item 5 ) ---------------------------------------------- [8/99]
Subject: SDF Annotate Verilog-XL Issues w/ Mixing Two ASICs From Two Vendors
> I am working on a project in which I am designing a support ASIC
> for another, separate ASIC based on an ARM7 core.
> I decided to link these two ASIC's together in one Verilog test
> bench to see if they'll work together the way I think they should. The
> two ASIC's are being fabricated by two different vendors (I'll just
> refer to them here as Vendor A and Vendor B) which naturally means that
> they have two different sets of library files to use. However, there
> are a number of cells in these two libraries that just happen to have
> the same names (e.g. the names of the 2-input NAND gate cell and the 3-
> input OR gate cell are identical in both libraries).
> The first problem I had was that Verilog-XL would try to build the
> support ASIC out of vendor A's library components instead of vendor B's
> library. I was able to solve this problem using the `uselib directive.
> Verilog-XL now looks at the correct library for each device when
> compiling the files. The current problem is with the SDF annotation. I
> can get the ASIC with the ARM core to annotate without a problem. But
> when I try to annotate the support ASIC, I get the following error
> messages reading SDF file and back-annotating timing data...
>
> /proj5/osa/vendor/postimp/pre_asa.sdf
> L773: SDFA Error: Type of INSTANCE (...).u10
> (or3$inst3_8$3) does not match CELLTYPE or3
>
> /proj5/osa/vendor/postimp/pre_asa.sdf
> L1027: SDFA Error: Type of INSTANCE (...).u204
> (nd2$inst3_8$3) does not match CELLTYPE nd2
>
> ...(and so on for a total of 123 SDF annotator errors on a couple of
> different cells)
>
> It appears to me that it's trying to annotate the support ASIC's
> data using the library of the ASIC with the ARM core. I don't get these
> error messages when I annotate the ARM core. I used the $sdf_annotate
> task to invoke the annotator in my test bench before doing any
> simulations, and I did tell it specifically which instance should be
> annotated from which file.
>
> Anybody have any ideas? I can run simulations without the
> annotation on the support ASIC, but I'd really like to make this as
> accurate of a simulation as I possibly can.
>
> - Greg Arena
> Dialogic Corporation Parsippany, NJ
From: "Ashutosh Varma" <ashu@axiscorp.com>
I think maybe because of `uselib, the cell defnames have been changed by
Verilog-XL to make them unique. And your original SDF file doesn't expect
this change.
I do not see an easy way out of this, except writing a script to manually
make the module names different for both libraries (prefix with something)
and the corresponding SDF files. With that, you can avoid having to use
`uselib.
- Ashutosh Varma
Axis Systems Sunnyvale, CA
---- ---- ---- ---- ---- ---- ----
From: paulge@pwrtool.cse.tek.com (Paul Gerlach)
This is true. I haven't used `uselib for a couple years, but I think I
remember this. I have the following line in a -f file, give it a try:
+sdf_nocheck_celltype //sdf doesn't work with uselib without this
Concerning Greg's "INSTANCE (...).u10 (or3$inst3_8$3) does not match
CELLTYPE or3" problem: when in doubt, turn it off!
- Paul M Gerlach
Tektronix, Inc. Beaverton, OR
( ESNUG 325 Item 6 ) ---------------------------------------------- [8/99]
Subject: Differences w/ ViewLogic FPGA Express vs. Synopsys FPGA Compiler II
> What is differences the Synopsys FPGA Express 3.2 and FPGA Compiler 3.2 ?
> Which is the best to Xilinx FPGA VHDL synthesize and optimize?
>
> - Tibor Szolnoki
From: Jim Kipps <jkipps@viewlogic.com>
ViewLogic FPGA Express 3.2 is identical to FPGA Compiler II (3.2) w/ regard
to language coverage and optimization algorithms. FPGA Compiler II is
differentiated from FPGA Express in three ways: DC compatibility features,
distribution channel, and price.
With regard to DC compability features, FPGA Compiler II can read and write
DC scripts and it can synthesize instantiated DesignWare components. While
FPGA Express uses the same language front-end and is subset compatible with
DC, it does not synthesize instantiated DesignWare components.
With regard to distribution channel, FPGA Express is not sold directly by
Synopsys. Rather, it is sold by Viewlogic and VeriBest as part of an
FPGA-in-Systems design solution. FPGA Express can also be obtained in a
vendor restricted form from Xilinx, Lattice, and Lucent.
Viewlogic is the only channel that markets FPGA Express for both the windows
and UNIX platform.
With regard to price, FPGA Express can be purchased at several price points
depending on which options you need. FPGA Compiler II comes with all
options included, which makes its price higher than FPGA Express. However,
if you are purchasing DC from Synopsys you might get a break on the price of
FPGA Compiler II.
As for which is best for Xilinx, FPGA Express 3.2 and FPGA Compiler II (3.2)
deliver the exact same results (san the use of DesignWare). In all fairness,
I should say that the two main competitors of FPGA Express/FPGA Compiler II
( Synplicity and Exemplar ) also give good results for Xilinx. I will also
admit to not doing so well for the Virtex family in the FGPA Express 3.1
release, but the 3.2 release has made tremendous improvements in its support
of Virtex and I recommend it.
All three tools (FPGA Express, Synplify, and Leonardo) can be evaluated at no
charge.
- James R. Kipps, FPGA Marketing Manager
ViewLogic Marlboro, MA
---- ---- ---- ---- ---- ---- ----
From: ems@riverside-machines.com
> While FPGA Express uses the same language front-end and is subset
> compatible with DC...
This wasn't true in Express 3.1 and DC 1998.05, as we discussed a few
weeks ago -- are you saying that they do both now use the same analyser?
- Evan
Riverside Machines Ltd.
( ESNUG 325 Item 7 ) ---------------------------------------------- [8/99]
Subject: ( ESNUG 319 #6 ) Modelsim & VSS VITAL SDF Lib Conflicts W/ DC 99.05
>> I'm trying to do a post-synthesis simulation with Modelsim EE 5.2, using
>> the VITAL lib of my ASIC vendor. I keep getting errors that some instances
>> do not have one or two generics (e.g.: tpd_c_q_posedge). (I do not have
>> errors of missing instances...) I don't think there is any error on the
>> top instance I apply the SDF file, nor similar things... However, I don't
>> know if I produce wrongly the SDF/VHDL files from Synopsys DC 99.05 (I use
>> the SDF v2.1 format). Is there any chance that the vendor ASIC VITAL
>> models are not 100% VITAL compatible, as said in the Modelsim user manual?
>
> The story has two sides. For an ASIC library used inside DC, a Synopsys
> model needs to be described (.lib) which is compiled into a binary format
> (.db) by Library Compiler (lc) of Synopsys. Usually the ASIC vendor is
> already providing the .db format, so you as customer do not need to have
> the lc license and do not need to compile it yourself. ... I guess, you
> will find either no definition or something like
>
> tpd_c_q
>
> The missing edge specifyer is enough to let the SDF backannotator failing.
>
> - Alex Schreiber
From: "jok" <jok@erols.com>
So, does this require some hand edits to make a vital library compliant
which was generated from the ASCII file used to create a synthesis library?
We are considering using the Library Compiler to make a VITAL library. Now,
what are the caveats to make the library 'compliant' ? i.e. The missing
edge specifier in your example would seem to be a short-fall of the tool
which created the VITAL library... but is it? How can a vendor be sure
that the library does not cause grief like the grief spoken about in this
thread?
- Jim
---- ---- ---- ---- ---- ---- ----
From: Eric Venditti <evenditt@tif.ti.com>
Hi,
In fact the latest Synopsys DC version has been enhanced for edge relative
timing and now most of the vital library are not compatible with the new
SDF generated by DC. In order to solve this problem end to get a DC 98.08
like SDF you can set in your .synopsys_dc.setup a variable call
sdfout_no_edge = "true";
After that it should work as with the previous version
- Eric Venditti
Texas Instruments
( ESNUG 325 Item 8 ) ---------------------------------------------- [8/99]
Subject: ( ESNUG 321 #10 322 #5 ) A Module Compiler Trick Synopsys AE's Hide
> Keep me anon, but the Synopsys AE's are always trying to keep people from
> using a very powerful feature of Module Compiler -- it used to be in the
> documentation, but they even took it out of there!
>
> For carry save arrays, there is a way to access the carry and sum terms
> prior to the final add. This is great if you want to control pipelining
> yourself, instead of hoping that MC finds the right place for your regs.
> The example below does a simple multiply, but registers the values prior
> to the the final add.
>
> module TEST (Z, X, Y);
> input [w-1:0] X, Y;
> output [2*w-1:0] Z;
> wire [2*w-1:0] PRODS, PRODC;
>
> directive local (carrysave="convert", pipeline="off");
> wire [w*2-1:0] PROD = X*Y;
> csconvert(PRODS, PRODC, PROD);
> PRODS_reg = sreg(PRODS);
> PRODC_reg = sreg(PRODC);
> Z = ACC0+ACC1; //Adding the two terms together, or to another
> //signal brings um back together.
> endmodule
>
> You can use this to create superfast accumulators or if the Multiplier
> feeds other adders you can often save a carry propagate add.
>
> To be fair to the Synopsys AE's, this approach has 2 drawbacks:
>
> 1. Hard to verify
> 2. if you try to do any logic on these outputs seperately, you can
> really screw yourself (like trying to check if they are zero...)
>
> At my last company we used this feature to get great results!
>
> - [ Casper, The Friendly Ghost ]
From: [ A Synopsys Module Compiler CAE ]
Hello John,
I would like to respond to ESNUG 322, Item 5: "A Module Compiler Trick
That Synopsys AE's Hide".
Casper is right, the carrysave is a very powerful technique. It takes
only a couple of lines of code to implement but can result in a
significant reduction in area and/or delay depending on the design
architecture. The problem is, as Casper mentioned, one can fall in a lot
of trouble if this very powerful feature is not used correctly.
Now that MC is widely deployed and there are well trained users of MC
everywhere, we'll start documenting this feature along with a use
methodology, starting with release 2000.02.
- [ A Synopsys Module Compiler CAE ]
( ESNUG 325 Item 9 ) ---------------------------------------------- [8/99]
Subject: ( ESNUG 324 #14 ) Some Useful Dc_shell & Makefile Vim Syntax Files
> I am looking for vim syntax files for dc_shell (script and log) and
> others EDA tools syntax files.
>
> - Benoit Durand
> STMicroelectronics
From: Gzim Derti <gderti@intrinsix.com>
Hi John,
I started playing with VIM not long ago and wanted to pretty up what I was
seeing in my Synopsys scripts, so I started to generate a rudimentary .vim
syntax file for Synopsys tools.
I basically bastardized the syntax file for another language and added in
the comment definitions from C-language (seems to work for me).
Remember to also add an entry in the /usr/local/share/vim/syntax/syntax.vim
language definition file so that vim knows that the new synopsys.vim
file exists. Here's what my entry looks like...
" Synopsys
au BufNewFile,BufRead *.syn,*.scr,*.pt,*synopsys* so $VIM/syntax/synopsys.vim
NOTE: that the 'au' line above is a single line!!!!
I've added most of the commands that I've run into so far. More can and
probably will be added in the future as they present themselves. I also was
running into issues when trying to define "syn match" rather than "syn
keyword" using regular expressions so I just defaulted to using keywords
for everything.
One final note, I've been using vim -g -fg white -bg black to make things
stand out better. I find that it's also a little easier on my eyes after
staring at the tube all day... but YMMV!!
- Gzim Derti
Intrinsix Corp. Rochester, NY
filename="synopsys.vim"
" Vim syntax file
" Language: Synopsys
" Maintainer: <vacancy>
" Credits: Stephan Hegel <ea273@fen.baynet.de>
" Czo (Olivier Sirol) <sirol@cao-vlsi.ibp.fr>
" $Id: synop.vim,v 1.4 1998/28 19:37:33 steve Exp $
" Remove any old syntax stuff hanging around
syn clear
" case is not significant
syn case ignore
" Synopsys keywords
syn keyword synopStatement dc_shell
syn keyword synopStatement analyze elaborate
syn keyword synopStatement include echo read write compile
syn keyword synopStatement alias
syn keyword synopStatement all_connected
syn keyword synopStatement change_names
syn keyword synopStatement characterize write_script
syn keyword synopStatement check_design
syn keyword synopStatement current_design current_instance
syn keyword synopStatement create_design create_cell create_port create_net
syn keyword synopStatement connect_net
syn keyword synopStatement create_clock
syn keyword synopStatement designer
syn keyword synopStatement company
syn keyword synopStatement disconnect_net
syn keyword synopStatement echo_include_commands
syn keyword synopStatement filter find
syn keyword synopStatement get_unix_variable
syn keyword synopStatement get_attribute
syn keyword synopStatement link uniquify quit
syn keyword synopStatement remove_license remove_design remove_variable remove_port
syn keyword synopStatement remove_input_delay
syn keyword synopStatement remove_attribute
syn keyword synopStatement report_timing
syn keyword synopStatement report_reference
syn keyword synopStatement report_transitive_fanout
syn keyword synopStatement report_net report_cell report_constraint report_clock report_port
syn keyword synopStatement reset_design
syn keyword synopStatement set_operating_conditions
syn keyword synopStatement set_max_capacitance set_max_fanout set_max_area
syn keyword synopStatement set_attribute
syn keyword synopStatement set_input_delay set_output_delay
syn keyword synopStatement set_critical_range set_output_delay
syn keyword synopStatement set_fix_multiple_port_nets
syn keyword synopStatement set_wire_load
syn keyword synopStatement set_scan_configuration set_signal_type check_test
syn keyword synopStatement set_disable_timing
syn keyword synopStatement set_dont_touch_network set_dont_touch
syn keyword synopStatement set_dont_use set_drive set_fix_hold set_load
syn keyword synopStatement set_max_delay set_min_delay
syn keyword synopStatement set_false_path
syn keyword synopStatement syn_flatten
syn keyword synopStatement synthetic_library
syn keyword synopStatement ungroup
syn keyword synopStatement update_timing
syn keyword synopStatement verilogOut_no_tri
syn keyword synopStatement verilogout_equation
syn keyword synopStatement hdlout_internal_busses
syn keyword synopStatement bus_inference_style
syn keyword synopStatement define_name_rules
syn keyword synopStatement default_name_rules
syn keyword synopStatement hdlin_latch_synch_set_reset
syn keyword synopStatement hdlin_use_cin
syn keyword synopStatement write_name_nets_same_as_ports
syn keyword synopStatement if else endif for foreach end switch case breaksw default endsw break
syn keyword synopStatement while set unset sleep
syn keyword synopStatement touch grep awk rm mv date print sh cat cp chmod mkdir ps wc
syn keyword synopBoolean true false
" floating numbers
syn match synopNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
syn match synopNumber "-\=\<\d\+\.\d\+\>"
syn match synopNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
syn match synopNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
" integer numbers
syn match synopNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>"
syn match synopNumber "-\=\<\d\+\>"
syn match synopNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
syn match synopNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
syn match synopCharacter "\'[&><=:+\-*\/().,;\'$#|~!%@?\^\[\]{}\\a-z0-9 ]\'"
syn match synopComment "/\*.*$"
syn match synopComment "\*/.*$"
syn match synopComment "\".*\""
syn match synopSpecial "[{}().,;/]"
syn match synopOperator "\!="
syn match synopOperator "=="
syn match synopOperator "{}"
syn match synopOperator "="
syn match synopOperator "+"
syn match synopOperator ">"
syn match synopOperator ">>"
syn match synopOperator "<<"
syn match synopOperator "|"
syn match synopOperator "\$"
syn match synopOperator "\$<"
syn match synopOperator "-\w\s"
syn match synopAttribute "\s-\w\+\>"
if exists("c_comment_strings")
" A comment can contain cString, cCharacter and cNumber.
" But a "*/" inside a cString in a cComment DOES end the comment! So we
" need to use a special type of cString: cCommentString, which also ends on
" "*/", and sees a "*" at the start of the line as comment again.
" Unfortunately this doesn't very well work for // type of comments :-(
syntax match cCommentSkip contained "^\s*\*\($\|\s\+\)"
syntax region cCommentString contained start=+"+ skip=+\\\\\|\\"+ end=+"+ end=+\*/+me=s-1 contains=cSpecial,cCommentSkip
syntax region cComment2String contained start=+"+ skip=+\\\\\|\\"+ end=+"+ end="$" contains=cSpecial
syntax region cComment start="^/\*" end="\*/" contains=cTodo,cCommentString,cCharacter,cNumber,cFloat,cSpaceError
syntax match cComment "//.*" contains=cTodo,cComment2String,cCharacter,cNumber,cSpaceError
else
syn region cComment start="^/\*" end="\*/" contains=cTodo,cSpaceError
syn match cComment "//.*" contains=cTodo,cSpaceError
endif
syntax match cCommentError "\*/"
if !exists("did_synops_syntax_inits")
let did_synops_syntax_inits = 1
" The default methods for highlighting. Can be overridden later
hi link synopStatement Statement
hi link synopBoolean String
hi link synopComment Comment
hi link synopNumber String
hi link synopCharacter String
hi link synopSpecial Special
hi link synopOperator Type
hi link synopAttribute Type
hi link cCommentError cError
hi link cCommentString cString
hi link cComment2String cString
hi link cCommentSkip cComment
hi link cString String
hi link cComment Comment
endif
let b:current_syntax = "synop"
" vim: ts=8
---- ---- ---- ---- ---- ---- ----
From: Claudio Fleiner <claudio@fleiner.com>
Enclosed below is a Vim file to use for editing/creating makefiles.
- Claudio Fleiner
" Vim syntax file
" Language: Makefile
" Maintainer: Claudio Fleiner <claudio@fleiner.com>
" URL: http://www.fleiner.com/vim/syntax/make.vim
" Last change: 1999 June 16
" Remove any old syntax stuff hanging around
syn clear
" This file makes use of the highlighting "Function", which is not defined
" in the normal syntax.vim file yet.
" some directives
syn match makePreCondit "^\s*\(ifeq\>\|else\>\|endif\>\|define\>\|endef\>\|ifneq\>\|ifdef\>\|ifndef\>\)"
syn match makeInclude "^\s*include"
syn match makeStatement "^\s*vpath"
syn match makeOverride "^\s*override"
hi link makeOverride makeStatement
" Microsoft Makefile specials
syn case ignore
syn match makeInclude "^!\s*include"
syn match makePreCondit "!\s*\(cmdswitches\>\|error\>\|message\>\|include\>\|if\>\|ifdef\>\|ifndef\>\|else\>\|elseif\>\|else if\>\|else\s*ifdef\>\|else\s*ifndef\>\|endif\>\|undef\>\)"
syn case match
" make targets
syn match makeSpecTarget "^\.SUFFIXES"
syn match makeSpecTarget "^\.PHONY"
syn match makeSpecTarget "^\.DEFAULT"
syn match makeSpecTarget "^\.PRECIOUS"
syn match makeSpecTarget "^\.IGNORE"
syn match makeSpecTarget "^\.SILENT"
syn match makeSpecTarget "^\.EXPORT_ALL_VARIABLES"
syn match makeSpecTarget "^\.KEEP_STATE"
syn match makeImplicit "^\.\w\+\.\w\+\s*:[^=]"me=e-2
syn match makeImplicit "^\.\w\+\.\w\+\s*:$"me=e-1
syn match makeTarget "^\w[A-Za-z0-9_./\t -]*:[^=]"me=e-2
syn match makeTarget "^\w[A-Za-z0-9_./\t -]*:$"me=e-1
" Statements / Functions (GNU make)
syn match makeStatement contained "(subst"ms=s+1
syn match makeStatement contained "(addprefix"ms=s+1
syn match makeStatement contained "(addsuffix"ms=s+1
syn match makeStatement contained "(basename"ms=s+1
syn match makeStatement contained "(dir"ms=s+1
syn match makeStatement contained "(filter"ms=s+1
syn match makeStatement contained "(filter-out"ms=s+1
syn match makeStatement contained "(findstring"ms=s+1
syn match makeStatement contained "(firstword"ms=s+1
syn match makeStatement contained "(foreach"ms=s+1
syn match makeStatement contained "(join"ms=s+1
syn match makeStatement contained "(notdir"ms=s+1
syn match makeStatement contained "(origin"ms=s+1
syn match makeStatement contained "(patsubst"ms=s+1
syn match makeStatement contained "(shell"ms=s+1
syn match makeStatement contained "(sort"ms=s+1
syn match makeStatement contained "(strip"ms=s+1
syn match makeStatement contained "(suffix"ms=s+1
syn match makeStatement contained "(wildcard"ms=s+1
syn match makeStatement contained "(word"ms=s+1
syn match makeStatement contained "(words"ms=s+1
" some special characters
syn match makeSpecial "^\s*[@-]\+"
syn match makeNextLine "\\$"
" identifiers
syn match makeIdent "\$([^)]*)" contains=makeStatement
syn match makeIdent "\$\$\w*"
syn match makeIdent "\$[^({]"
syn match makeIdent "\${[^}]*}"
syn match makeIdent "^\s*\a\w*\s*[:+?!]="me=e-2
syn match makeIdent "^\s*\a\w*\s*="me=e-1
syn match makeIdent "%"
" Errors
syn match makeError "^ \+\t"
syn match makeError "^ \{8\}[^ ]"me=e-1
syn region makeIgnore start="\\$" end="^." end="^$" contains=ALLBUT,makeError
" Comment
syn match makeComment "#.*$"
" match escaped quotes and any other escaped character
" except for $, as a backslash in front of a $ does
" not make it a standard character, but instead it will
" still act as the beginning of a variable
" The escaped char is not highlightet currently
syn match makeEscapedChar "\\[^$]"
syn region makeDString start=+"+ skip=+\\"+ end=+"+ contains=makeIdent
syn region makeSString start=+'+ skip=+\\'+ end=+'+ contains=makeIdent
syn region makeBString start=+`+ skip=+\\`+ end=+`+ contains=makeIdent,makeSString,makeDString,makeNextLine
if !exists("did_makefile_syntax_inits")
let did_makefile_syntax_inits = 1
hi link makeNextLine makeSpecial
hi link makeSpecTarget Statement
hi link makeImplicit Function
hi link makeTarget Function
hi link makeInclude Include
hi link makePreCondit PreCondit
hi link makeStatement Statement
hi link makeIdent Identifier
hi link makeSpecial Special
hi link makeComment Comment
hi link makeDString String
hi link makeSString String
hi link makeBString Function
hi link makeError Error
endif
let b:current_syntax = "make"
" vim: ts=8
( ESNUG 325 Item 10 ) --------------------------------------------- [8/99]
Subject: ( ESNUG 324 #6 ) Measuring Toggle Of A Signal In A VCS Simulation
> Does any one know how to count the toggle rate of a signal during a VCS
> simulation ?
>
> - Eran Schar'am
> Zoran Microelectronics Haifa, Israel
From: David Kelf <davek@co-design.com>
Hi John,
Couldn't help notice this post in ESNUG on getting toggle info out of VCS.
Cadence supplies the source code for a toggle test PLI application free on
their Verilog-XL and NC-Verilog installation CDs. The original purpose of
this to was to provide PLI examples such that people could get a head start
with PLI. However, the toggle test routines proved invaluable as a basis
for power estimation applications and stuff like that.
Assuming Zoran has a copy of Verilog-XL they may want to check out the
example directories. These routines use standard PLI so they should work
fine with most of the regular Verilog simulators.
- Dave Kelf
Co-Design Automation, Inc.
( ESNUG 325 Item 11 ) --------------------------------------------- [8/99]
Subject: How To Convert Synopsys DC .lib Files To Cadence/Ambit ALF Files
> I'm switching over from Synopsys Design Compiler to Ambit BuildGates. I
> have some uncompiled ASCII .lib files from Synopsys. I don't know where
> to start looking to figure out how to convert these to Ambit ALF library
> files. I'm not even sure what program is used to do it.
>
> - David Rogoff
From: Jeroen Vermeeren <Jeroen.Vermeeren@nym.sc.philips.com>
Hi David,
The trick is not to create ALF files but TLF files. Ambit can read CTLF
files as well as ALF files. Use "syn2tlf" for conversion of synopsys .lib
to TLF. Use "tlfc" for conversion from tlf to ctlf (to compile the tlf).
- Jeroen Vermeeren
Philips Semiconductors
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