Editor's Note: Last week, I was Mr. Super Stud. I had five (yup, that's
five, as in 1-2-3-4-5 !) past ex-girlfriends call me! Of course, it was
great to catch up on old times, etc. One lives in upstate New York, just
got downsized from her job, and was thinking of moving back to Boston. (I
hadn't seen her in 4 years... and she seemed disappointed when I told her
about how great my current relationship was going.) Another was now a
new single mom. I hadn't seen her in 2 years. (Whew!) Another just got
back from her home in Sweden and just broke up with her Boston boyfriend.
Another was seeing a married man. And the last one had just placed her
first personal ad in a Boston newspaper.
I figured it was just my incredible machismo crossing the space-time
continuum luring these past lovers back to me. That was, until I had
lunch with a non-romantic female friend and I told her about my 'animal
magnetism'... Her painful words: "John! You uber-goober! Men have
such inflated egos! You goober! These women are calling you because
they're between viable boyfriends. Valentine's Day is blasting at them
from every which way subliminally and not-so-subliminally telling
them there's something *wrong* with them if they're not in a coo-ing,
kissy-kissy romantic relationship. They're calling you because you're
an unmarried male -- and nothing more than that!! You uber-goober!"
A little deflated, I told a good male friend about my five 'callers' and
my female friend's explaination. He said: "She might be right, but at
least you made each ex-girlfriend's list of guys to call. That's
something to be proud of." And when I bragged to my current girlfriend
about my five ex's calling, she replied: "<Yawn> And I had two past
boyfriends call me, too. It's a Valentine's thing. No big thing. So,
do you want to go to Sue's or Matt's party this weekend?" <Ouch!>
- John Cooley
the ESNUG guy
( ESNUG 311 Item 1 ) ---------------------------------------------- [2/99]
Subject: ( ESNUG 310 #1 ) Three Other Ways To Crack FLEX-lm Licensing
> The first way to bypass FLEX-lm is to simply keep resetting your system
> clock to a day when your license keys were still legitimate. This does get
> to be a hassle because companies like Cadence and ViewLogic use start
> and end dates in their licensing forcing you to be resetting the system
> clock quite often. Also, Cadence is rumored to do some nasty things if
> it finds files newer than your current date in your system.
>
> The second way is to 'steal' EDA licenses from other companies over the
> Internet. All you need is a copy of the FLEX-lm license key from your
> target company to get the server name and the port number FLEX-lm uses on
> it. For example, if you used to work at Texas Instruments and you're now
> at a small start-up that needs more Synopsys licenses than the one you
> legally have, grep your copy of that TI license key for 'SERVER'. It'll
> spit out something like 'SERVER achilles 55431234 995'. This says that
> 'achilles' uses port 995 for FLEX-lm keys. Ping ti.com to get their dotted
> quad (192.94.94.33) and add '192.94.94.33 achilles' in your /etc/hosts to
> make their machine local to you. After that, 'setenv LM_LICENSE_FILE
> 995@achilles.ti.com' on your machine. You now have those TI Synopsys
> licenses for your machine.
>
> This works because the net admin and EDA admin people don't interact much.
> The net admin guy could easily stop me by blocking external access at the
> firewall to those specific ports that FLEX-lm uses.
>
> My third, and favorite hardware hacker way to bypass FLEX-lm, is by using
> my PROM burner to copy my workstation's boot PROM. That way, all 16 of my
> workstations have the same machine ID, they each run their own copy of
> Synopsys/Cadence/whatever, yet I only pay for one copy. They're hell to
> network together, though. Makes them not too useful for large chip dsgns.
>
> - [ Gozer, the Gozerian ]
From: [ Not Me, I Didn't say This! ]
Hi John,
Can you post this anonymous
In the last posting about licenses it was mentioned that you could try to
change the nodeid of the system.
For everything there is a faq on the internet so also for this 'Frequently
Asked Questions about Sun NVRAM/hostid'
ftp://ftp.mindlink.net/pub/crypto/sun-stuff/sun-nvram-hostid.faq.html
ftp://ftp.netcom.com/pub/henderso/sun-nvram-hostid.faq.html
http://www.squirrel.com/squirrel/sun-nvram-hostid.faq.html
Plain text versions of this document are available from the following:
ftp://ftp.mindlink.net/pub/crypto/sun-stuff/sun-nvram-hostid.faq
ftp://ftp.netcom.com/pub/henderso/sun-nvram-hostid.faq
http://www.squirrel.com/squirrel/sun-nvram-hostid.faq
and it refers to the software method for changing the hostid
'change-sun-hostid'
Here is the relevant extract from the faq:
This FAQ is also distributed as part of a larger package for spoofing
the hostid on Sun workstations called change-sun-hostid. In particular,
parts of change-sun-hostid can be used to modify the apparent hostid for
some or all processes on a UNIX system without messing with the NVRAM.
This package even provides a way to make a host seem to have multiple
hostids (different processes see different hostids). If you are interested
in changing your hostid to deal with software licence issues, you should
probably try the scripts/programs in this package first, as most of them
don't make permanent changes to a chip on your motherboard. Changing
the NVRAM should be a last resort. You can retrieve this package from:
ftp://ftp.mindlink.net/pub/crypto/sun-stuff/change-sun-hostid.tar.gz
http://www.squirrel.com/squirrel/sun-stuff/change-sun-hostid.tar.gz
As you can see it is sun only.
It is a nice solution for the license server reliability problem. What
happens if your license server goes up in smoke?
1. you can transfer your licenses to a new server. This will takes days
and need a lot of administration. Meanwhile you are without any license.
2. you use a three servers in a redundant configuration. If one machine
goes down or needs updating your back to solution 1, but without the
time pressure.
3. you pay for a 4 hour intervention on your sun and hope that they
are able to get the nodeid back.
4. Use this system and boot another sun with the same node id as license
server.
- [ Not Me, I Didn't say This! ]
---- ---- ---- ---- ---- ---- ----
From: "Alex Kumets" <kumets@hotmail.com>
John,
It's easy to avoid problem with 'resetting your system clock' solution.
Just use `find -atime +1` and `touch` commands together.
- Alex Kumets
ASIC Consulting
---- ---- ---- ---- ---- ---- ----
From: [ Zul, The EDA Marketing Demi-God ]
(anonymity please)
What, now you're a hacker's reflector? If I want to steal software, I
could just go to my local Starbucks and find some tattooed, pierced,
haiku-writing, goatee-wearing slacker-boy and have him do it for an "all
the coffee you can drink" card.
It is a well-proven law that any licensing/encryption/lock can be broken.
It is also a law that one cannot aid and abet in a crime. Passing out this
kind of information is questionable at best.
- [ Zul, The EDA Marketing Demi-God ]
---- ---- ---- ---- ---- ---- ----
From: [ A Cadence Reader ]
John, I had to reply to this one...
What's up with this dude? I assume most of my customers can figure out
how to bypass the system and use licenses without paying for them, but they
just don't do it. It's illegal, and I know from a personal customer
experience that it is VERY embarassing when you get caught. I guess because
it's software he/she thinks it doesn't count???
I wouldn't be bragging if I was "Gozer". I'm not impressed!
Please don't print my name in case it's one of my customers. I
sure hope not.....
- [ A Cadence Reader ]
---- ---- ---- ---- ---- ---- ----
From: [ No, Flames, Please ]
John -
Yawn... Anyone who dreams up ways to weasel their way around license
management like this is just being stupid. Doing this kind of thing is
not rocket science, and will probably work for a while, but it will catch
up with you eventually. No, I don't speak from experience, but your
readers should be warned that anyone running a company like this is probably
in trouble all around.
Please don't use my real name, I'm not particularly interested in being
flamed for this.
- [ No, Flames, Please ]
---- ---- ---- ---- ---- ---- ----
From: danlutes@crystal.cirrus.com (Daniel Lutes)
John,
I hate to sound like an EDA company lackey, but please cease and desist.
We're all engineers, whether software or hardware. Publishing articles
like these to facilitate theft of one engineer's work by another doesn't
seem to me like a legitimate productivity enhancer.
On the other hand, since the senior execs at the EDA companies now all
seem to read your ESNUG newsletter, perhaps publishing these security holes
at the beginning of your column is the best way to get them patched.
With that in mind, feel free to publish, withold, or edit as you see fit.
- Dan Lutes
Cirrus
( ESNUG 311 Item 2 ) ---------------------------------------------- [2/99]
Subject: (ESNUG 308 #7 310 #11) Wait! Our Experience With LSF Was Great!
> I was forced to use a Perl script (written by a fellow graduate student) to
> check the number of jobs I was running and submit jobs as old jobs
> completed. It was not convenient at all.
>
> I also found that some of my jobs would continue running for more than a
> full day. When I killed these jobs they would often report results as if
> they had finished normally. I don't know how long they would have remained
> in limbo if I had not killed them manually.
>
> All in all, I was rather disappointed with LSF. Maybe I expect too much
> functionality without a great deal of work. And, as I said, I cannot
> guarantee that the system was installed and maintained properly.
>
> - David C. Hoffmeister
> University of Maryland
From: Tanya Pobuda <tpobuda@platform.com>
John,
Just a quick note to let you know that Platform's account manager has just
been in contact with the Naval Research Lab. There's a strong feeling there
that this is a misconfiguration or maintainence issue, and our rep and her
support team are working to solve it.
We've got a second call in to pinpoint the problem. I will forward a note to
let you know how it turns out.
Thanks for the tip.
- Tanya Pobuda
Platform Computing Corp.
---- ---- ---- ---- ---- ---- ----
From: Billy Vitro <bvitro@cisco.com>
John,
The LSF software was almost certainly configured completely wrong. The
main feature of LSF is to load share by sending jobs to CPUs that are not
currently being used. It will even monitor machines which are loaded by
jobs run outside the LSF system, providing the jobs were started prior to
LSF submitting the batch job to the host.
This user may have been experiencing something that we see ourselves;
nothing in LSF prevents users from running jobs on hosts outside of LSF
and stealing CPU cycles after the batch job has been started. We got around
that by restricting logins on server farm machines, which keeps people from
bogging them down with non-batch jobs, and allows the LSF software to do
it's job and use the resources most efficiently.
- Billy Vitro
Cisco Systems
---- ---- ---- ---- ---- ---- ----
From: Tom Loftus <tloftus@hns.com>
John,
I have to respond to David Hoffmeister's comments regarding LSF. It sounds
to me like it was not configured properly to match his needs as he suggested
in his e-mail.
I have had very positive results with LSF and praise it very highly,
particularly for ASIC regression testing. However, it is an extremely
configurable tool and requires close cooperation between the administrators
of the tool and the users.
Our biggest problem has been coming up with a "use model" which can be
captured in the LSF config files and implemented on the machines with the
desired results. This is complicated by the fact that we allow both batch
and interactive use of the servers. With that said, here are some specific
responses from a user of LSF versions 3.1 and 3.2.
> Often my jobs were submitted to hosts that had more than one job per
> cpu already while other hosts had multiple idle cpus.
The number of jobs per CPU is a configurable option. When he says "jobs"
I would be curious to see if these were LSF submitted jobs, or jobs running
outside the LSF system. LSF software can't control jobs not submitted
through LSF.
> On top of that, if I submitted too many jobs at once, even with resource
> requirements, it allowed all of them to run and swamped the system.
We have limits on the number of jobs per user setup in a set of queues so
that a user can submit to the queue with the desired amount of parallelism.
Our biggest limit is licenses. We can't let the LSF software chew up all
the Verilog licenses or other users can't work.
> Maybe I expect too much functionality without a great deal of work. And,
> as I said, I cannot guarantee that the system was installed and maintained
> properly.
I am both the administrator and the user of the LSF software and so am
possibly somewhat unique in my ability to tweak it to our needs. But my
experience has shown that if you can describe a set of rules, or use model,
to fit your situation, you can reliably implement it in LSF.
Also, there will always be some cases where a person could make better
decisions than the software following it's simple rules. However, I
maintain that the benefits far outweigh the occasional inefficiencies.
One last comment, I wish they integrated better with flexLM license servers
because I would like better flexibility to suspend jobs and steal licenses
and then resume but I can't do that now.
- Tom Loftus
Hughes Network Systems
( ESNUG 311 Item 3 ) ---------------------------------------------- [2/99]
Subject: ( ESNUG 310 #12 ) Convert Verilog To State Machines & Flow Charts
> Does anybody aware of any tool out in the market which can take Verilog
> code as a input and gives FLOW CHART or STATE MACHINES as a result ? I'm
> trying to do a extention of a existing chip where I need to understand
> the implementaion but not much documentaion is available for me.
>
> I know there is a tool which generates code from state machine or flow
> chart (Design Book of Escalade), but I need the other way.
>
> - Gopi Sirineni
> Integrated Device Technology, Inc. San Jose, CA
From: cashley@us.ibm.com ( Carl Ashley )
John,
Summit Design ( www.summit-design.com ) has a tool(s) which take in text
Verilog and produce either block diagrams (standard feature) or flow charts
and state machine diagrams ( additional license ). I have more experience
with the VHDL version of their product. I think generating FSM diagrams is
a bit of "snake oil", but the Summit Text2Graphics feature has recognized
several state machines that I have submitted to it. The Summit tool has
a feature which can be selected to go through the entire design tree (aka
hierarchy) and generate the highest level graphical representation it can
(e.g. FSM, Flowchart, block diagram).
- Carl Ashley
IBM Microelectronics (ASIC Cores Development)
---- ---- ---- ---- ---- ---- ----
From: Tsu-Hua Wang <tsuhua@cisco.com>
John,
In reply to ESNUG 310 Item 12, Gopi may want to try free "ciscofsm".
http://www.employees.org/~ciscofsm
Ciscofsm should be superior than many commercial tools.
- Tsu-Hua Wang
Cisco Systems San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Jon McDonald <jmcdonal@gte.net>
Hello John,
Summit Design's Visual HDL will produce Flowcharts and Statemachines from
Verilog or VHDL code.
- Jon McDonald
---- ---- ---- ---- ---- ---- ----
From: Scott Evans <scott@NPLab.Com>
John,
I saw a demo from Novas (www.novassoft.com) of a tool they have which is
pretty good at figuring out state machines. Have not used that tool, but
are quite happy with the Debussy software we have from them.
- Scott Evans
NeoParadigm Labs San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Peter Davy <peter_davy@mentorg.com>
Hello John,
Apologies for responding as a vendor but I think we can help. I am a
Technical Marketing Engineer for a product called Renoir. Renoir is an
HDL (Verilog and VHDL) design creation tool. It provides graphical editors
(State Machine, Flow Chart, TruthTable & Block Diagram) as well as design
management capabilities. The part I think you are looking for is the
HDL2Graphics capability which will convert HDL code to appropriate diagrams.
Feel free to find out more from www.renoir.com where you can also download
the product.
- Peter Davy
Mentor Graphics
---- ---- ---- ---- ---- ---- ----
From: Oliver Weber <oweber@el.nec.com>
Hi John,
I recommend Visual HDL (for Verilog) from Summit (www.summit-design.com)
This includes also an option called "Verilog to Graphics".
If the original hdl design does not include too many blocks (< 10-15, but
this is relative; depends also on the structuring, number of interconnects
....) within one hierarchy level, then the result is really good.
In the most cases, you don't need to move the blocks/signals by hand.
Also Statemachines and FlowCharts will be produced based on the source HDL
code. Flow Chart tells you not very much, but Statemachine extraction is
good. I have only tried the software for VHDL. But it should produce
nearly the same results as for Verilog.
Another tool, which also generates graphics from HDL, is Renoir from Mentor.
You can download a demo version of this tool from the mentor web page
(http://www.mentor.com/renoir/index.htm) and this demo version is able to
read in HDL and outputs Graphics (which you cannot save in the demo version)
but you will see, the result is not the best. :-)
My evaluation of Renoir, was 5 month ago; possibly they made some changes
in the latest Version.
- Oliver Weber
NEC Electronics (Germany) GmbH
( ESNUG 311 Item 4 ) ---------------------------------------------- [2/99]
From: [ The Budweiser Lizard ]
Subject: Seeking Customer Recommendations Of Verilog Cycle-Based Simulators
Hi John,
We are looking for a high performance (> 300 cps) Verilog Cycle-based
simulator. We are evaluating Speedsim but don't have time to evaluate all
others, especially Cobalt, the Cadence alternative. Our verification
environment compares responses from our C reference model simulation and
Verilog models in parallel using IPC and PLI.
Our full chip environment uses lots of PLIs.
Can anyone point out pros and cons and recommend a well proven, high
performance, easy-to-use Verilog cycle-based simulator ?
Your feedback would be greatly appreciated.
John, thanks for being an authoritative voice for us.
Plz withhold my name and co.
- [ The Budweiser Lizard ]
( ESNUG 311 Item 5 ) ---------------------------------------------- [2/99]
From: hroberts@aluxs.micro.lucent.com
Subject: How To Model A Configurable I/O Buffer In Library Compiler ?
Hi John,
Has anyone ever modeled an I/O buffer in SYNOPSYS which has pins to
configure the buffer? My specific problem is that there are pins which
affect timing but do not affect function, and library compiler will not
compile such a buffer.
- Hollis Robertson
Lucent Technologies
( ESNUG 311 Item 6 ) ---------------------------------------------- [2/99]
From: sol@lexra.com (Sol Katzman)
Subject: Yeach! Those Incremental Compiles Are Wrecking My Timing !!!
John,
Yeach! A second compile apparently wrecks timing under certain conditions.
We have found that the area-reduction phase of an incremental compile
either ignores timing violations, or incorrectly calculates timing, IF
there is a design rule violation at the start of the incremental
compile AND the max_area attribute is over constrained.
The result is that a design that met timing before the incremental compile
is turned into a design that is smaller, but no longer meets timing. Not
what you want. (Definitely not what you want.)
Our flow is as follows for module "jpt":
1) read -format verilog jpt
2) set_max_area jpt 2500
3) apply custom wire load model to jpt
4) compile jpt
-- generates designware submodule "DW01"
-- timing met
-- design rules met
-- area 6500
5) apply custom wire load model to DW01
6) compile DW01 with overconstrained timing
7) report constraint -all_violators for jpt
-- timing met
-- area not met (okay)
-- fanout design rule violation (due to step 6)
8) compile -incremental jpt
-- timing *apparently* met (0 delta delay)
-- design rules met
-- area 6200
9) report constraint -all_violators
-- timing NOT met (VERY BAD)
-- area not met (okay)
-- design rules met (good)
Key points:
In step (8) Design Compiler shows DELTA DELAY = 0, but report_timing
(corroborated with primetime) shows beaucoup violating paths.
(NOTE: the fanout violation is not known to the step (6) compile of
DW01, presumably because part of the fanout on the net in jpt is
outside DW01.)
WorkArounds:
Any of the following workarounds eliminate the problem:
(a) omit step (6) -- no fanout design rule violation
(b) loosen fanout design rule after step (6)
(c) loosen max area constraint in step (2)
(d) remove area constraint before step (8) <-- chosen approach
WorseArounds:
If a full compile (not incremental) is used in step (8), then
(c) and (d) don't work because the full compile always tries
to reduce the area, even without a max_area attribute!
My guess as to what's going on:
Due to the design rule violation, the incremental compile sets a
switch to fix it at all costs, including making timing worse. Then
in the area reduction phase, it forgets to turn the switch off.
I don't know why the incremental compile shows 0 delta delay, but
report_timing definitely finds real timing failures in the
resulting design.
This behavior was observed in both 1998.02 and 1998.08 versions
of design compiler.
Conclusion:
Watch out for incremental compiles!
- Sol Katzman
Lexra
( ESNUG 311 Item 7 ) ---------------------------------------------- [2/99]
From: [ Kenny from South Park ]
Subject: I'm Suspicious Of Buying Any Synopsys/Viewlogic Crossover Products
John,
Some time ago ago I got a letter in the mail. The text of the letter can
be found at:
http://www.viewlogic.com/prezlett/english.html
Which basically states that Viewlogic is again an independant company
from Synopsys.
The way things shook out when the merger happened was that Synopsys sales
(and support) got the ASIC end of things, and "Viewlogic" got the the
board level. "Motive", a tool which Synopsys had been trying to kill for
some time, was finally under their control (evil chuckle), and they
got a decent Verilog compiler (yay!).
Now that the breakup has happened, it looks like things are going in
all different directions. Viewlogic is now selling FPGA_Express, which
was Synopsys's attempt to do FPGAs, and so is Synopsys. Synopsys sells
"PrimeTime", but most still use Motive, and Viewlogic has a tool called
"Blast" now, which looks suspiciously like "Motive" when you invoke it.
VCS can now be purchased from both companies.
What will happen? I have it on good authority that the Viewlogic and
Synopsys sales people hate each other. So, I'm going to hold on to my
current EDA environment, watch the sparks fly, and wait for them to
settle before I do anything new with either of them.
- [ Kenny from South Park ]
( ESNUG 311 Item 8 ) ---------------------------------------------- [2/99]
From: miller@symbol.com (Wayne Miller)
Subject: Inconsistent Port Maps Between 2 Levels Of VHDL Wasn't Flagged ?!?
Hi John,
This was bugging me last week, then Synopsys filed a STAR. I thought
I'd pass it along, and see if it is valid from an LRM standpoint.
Missing component outputs don't flag errors
I added an output to a lower level block using a schematic editor, but
I did not re-netlist at the top level. This resulted in inconsistent
port maps between the two levels of VHDL code. Neither vhdlan nor
-spc_elab generated even a warning. Is this legal? The code below
should make it clearer. (Note: If I omitted an input, then the parser
flags both missing ports.)
I can understand not mapping outputs in the instantiation, but
shouldn't the component declaration be checked?
-- Lower level
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MYBLOCK is
Port ( IN1 : In STD_LOGIC;
IN2 : In STD_LOGIC;
IN3 : In STD_LOGIC;
OUT1 : Out STD_LOGIC;
OUT2 : Out STD_LOGIC;
OUT3 : Out STD_LOGIC );
end MYBLOCK;
architecture BEHAVIORAL of MYBLOCK is
begin
OUT1 <= IN1;
OUT2 <= IN2;
OUT3 <= IN3;
end BEHAVIORAL;
configuration CFG_MYBLOCK_BEHAVIORAL of MYBLOCK is
for BEHAVIORAL
end for;
end CFG_MYBLOCK_BEHAVIORAL;
-- Top level
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library WORK;
entity TOP_MYBLOCK is
Port ( IN1 : In STD_LOGIC;
IN2 : In STD_LOGIC;
IN3 : In STD_LOGIC;
OUT1 : Out STD_LOGIC;
OUT2 : Out STD_LOGIC );
end TOP_MYBLOCK;
architecture SCHEMATIC of TOP_MYBLOCK is
component MYBLOCK
Port ( IN1 : In STD_LOGIC;
IN2 : In STD_LOGIC;
IN3 : In STD_LOGIC;
OUT1 : Out STD_LOGIC; -- !!!! NOTICE !!!! OUT3 is missing
OUT2 : Out STD_LOGIC );
end component;
begin
I1 : MYBLOCK
Port Map ( IN1=>IN1, IN2=>IN2, IN3=>IN3,
OUT1=>OUT1, OUT2=>OUT2 ); -- Again !!! OUT3 is missing
end SCHEMATIC;
configuration CFG_TOP_MYBLOCK_SCHEMATIC of TOP_MYBLOCK is
for SCHEMATIC
for I1: MYBLOCK
use configuration WORK.CFG_MYBLOCK_BEHAVIORAL;
end for;
end for;
end CFG_TOP_MYBLOCK_SCHEMATIC;
-- Variant
I also experimented with implicit port ordering:
I1 : MYBLOCK
Port Map ( IN1, IN2, IN3, OUT1, OUT2 );
This also did not generate any warnings, even though I'm mapping 5
signals to 6 ports.
Thanks for your help,
- Wayne Miller
Symbol Technologies, Inc.
( ESNUG 311 Item 9 ) ---------------------------------------------- [2/99]
Subject: ( ESNUG 309 #5 ) Utility To Translate From PrimeTime To DesignTime?
> Is there any utility which functions exactly opposite to "transcript" ?
> I want to convert some pt (primetime) script to dt (design time) script.
>
> - Rajendra Marulkar
> Texas Instruments
From: [ A Synopsys PrimeTime Support Engineer ]
John,
After you apply the constraints to the design in PT, you can write them back
out in DT format:
pt_shell> write_script -format dcsh -output somefile
You can also write out the characterized constraints for a sub-block:
pt_shell> characterize_context u1
pt_shell> write_context -format dcsh -output somefile u1
There is no script available that will translate a PT script to DT syntax
(however most of the commands are very similar).
One thing to note is that in the 1999.05 release of DC (to be released on
February 22, 1999), DC will offer you either the old dc_shell, or a new TCL
based shell. This will make it much easier to move scripts between tools.
- [ A Synopsys PrimeTime Support Engineer ]
( ESNUG 311 Item 10 ) --------------------------------------------- [2/99]
From: cmatsumo@cmp.com ( Craig Matsumoto )
Subject: Do You Know Anything About Engineers Doing 'Chip Doodling' ?
Hi John - It's Craig Matsumoto from EE Times. I've got a wacky story
assignment and figured you might be the guy to turn to (uh, nothing
personal....)
I'm writing about microdrawings found on silicon chips. Whereas designers
used to put their initials in the blank spaces of a design (so i'm told),
some have now graduated to doing some elaborate pictures. Cartoon
characters are popular -- Dilbert, Mickey, Waldo -- but some look like
actual drawings. You know, drawings done by someone with real artistic
talent.
One thing I'm trying to find out is how common this is. Does everybody
do it, sort of an EEs' graffiti? I'm also curious whether companies
condone it.
Finally, I've come across two nice urban myths that might amuse you: 1)
Chip designers communicate with one another through hidden micromessages on
the silicon ; 2) Companies will put their own logo on a chip, within the
active circuitry, as copy protection -- so if you try to copy the design
but remove the logo circuitry, the chip fails.
Like I said, wacky stuff. Your readers have any thoughts or suggestions?
- Craig Matsumoto
Associate Editor, EE Times
( ESNUG 311 Item 11 ) --------------------------------------------- [2/99]
Subject: Unused Ports From Synthesis Causing Simulation Headaches
> After I synthesize a design, I'm re-simulating it as gate-level verilog.
> However, synopsys doesn't always use every port on a library component
> (e.g. Q and Q_BAR on a DFF). Verilog gives tons of warnings for this type
> of stuff. Is there a way to get rid of this?
>
> - Matt Guthaus
> University of Michigan
From: Igor Orlovsky <oia@javad.ru>
You can use +nowarnTFNPC option while verilog-xl simulation. Although you
may skip other port connection mismatches related to your hierarchical
modules.
- Igor Orlovsky
JAVAD Positioning Systems Moscow, Russia
---- ---- ---- ---- ---- ---- ----
From: david@rogoff.cnchost.com (David Rogoff)
The other way is to set VerilogOut_Show_Unconnected_Port = "TRUE" (I think I
got the name right). All your ports will be shown with no net. On the down
side I have seen this mess up some 3rd party timing estimators that didn't
understand the syntax.
- David Rogoff
---- ---- ---- ---- ---- ---- ----
From: "K. Y. Chan" <kychan@hintcorp.com>
It should be verilogout_show_unconnected_pins = true.
- K. Y. Chan
( ESNUG 311 Item 12 ) --------------------------------------------- [2/99]
Subject: ( ESNUG 310 #15 ) Is Modeling Load-Dependent Pins An Afterthought ?
> Anyone, anywhere, could you please share any experience you have modeling
> load-dependent cell library pins.
>
> The 98.08 manuals devote a whopping 3 pages to this topic in what looks
> like an afterthought, not a real feature. I say this because load
> dependent timing appears to be supported *only* for constraint arcs, not
> delay or combinational arcs. Why in the world would that be so?
>
> - Andy Pagones
> Motorola Chicago Corporate Research Laboratories
From: [ A Synopsys Field Engineer ]
John,
Andy is correct. Load-dependent timing is not available for delay or
combinational arcs. The reason for not having them previously was that
there were no vendors asking for that level of accuracy with their
libraries. With the advent of some of the new, smaller geometries, vendors
are requesting the increased accuracy, so they are being added this year.
On the technical side, the real reason that Load-dependent delays are not
available is that they require a 3-Dimensional lookup table, which has
not been supported previously. It will be part of the release coming out
around August.
- [ A Synopsys Field Engineer ]
( ESNUG 311 Item 13 ) --------------------------------------------- [2/99]
From: Daghan Altas <altas@macs.ece.mcgill.ca>
Subject: How Can I Learn About The Internal Format Of .DB Files ?
Hi John
I was wondering if synopsys provides an API (application programmer
interface) to access .db files. Or at least, is there a way to know the
internal format of .db files?
- Daghan Altas
McGill University Montreal, Canada
( ESNUG 311 Item 14 ) --------------------------------------------- [2/99]
From: Steve Hwang <hwang_cad@yahoo.com>
Subject: Anyone Have A *Current* List Of The Hidden Synopsys Variables ?
Hi, John
As we all know Synopsys DC has many hidden variables and switches for
different purposes. A few years ago someone published them on ESNUG.
Could you send a list of hidden variables and switches again for review,
so we don't have to do so much research to get those information.
- Steve Hwang
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