In ESNUG 309, John Cooley wrote:
> Yesterday, I watched the TV version of Dilbert. I tried. Honest. I
> really did want it to be funny & witty & make me laugh out loud. Hey,
> Dilbert's one of our own -- we gotta support him! Honest. I tried...
> ... but it just didn't work. Instead, it just came off as artificially
> contrived and, sometimes, outright stupid. Scott Adams has had his
> Waterloo and soon our favorite cartoon son, Dilbert, will be moving to
> "Garfield" status in the near future. A sad day for engineers... :^(
From: "Ross Swanson" <ross@sismicro.com>
John, Re: this pathetic whine, I have 6 words: what a geek, get a life.
- Ross Swanson
SIS Microelectronics Longmont, Colorado
---- ---- ---- ---- ---- ---- ----
From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
John -
Your lead-off comments in ESNUG Post 309 have got to be some of the most
shocking and controversial comments that you have ever made.
To "dis" an engineering icon and hero, such as Dilbert, was previously
unspeakable. Only you would have the audacity and courage to attack a
national engineering treasure. I'm certain that you are probably
receiving phone death threats even as you read this message.
Alas! I must painfully agree. I too fulfilled my engineering
responsibility and watched the premier of Dilbert last Monday. It didn't
do much for me. Before I give Dilbert his television "pink-slip", I will
watch at least two more episodes to make sure that Scott Adams wasn't
just having a bad tie-day while working on the premier episode.
- Cliff Cummings
Sunburst Design Beaverton, OR
( ESNUG 310 Item 1 ) ----------------------------------------------- [2/7/99]
Subject: ( ESNUG 308 #6 ) Three Other Ways To Crack FLEX-lm Licensing
> Many softwares (like Solaris software design kit, Cadence, Synopsys,
> Specctra) on UNIX use FLEXlm as their license manager, but FLEXlm is not
> secure, it can be cracked. Is anyone interested? Please email to:
> flexlm@hotmail.com. ... I use adb to crack, it is tiring, so this
> service is not free. :) Are you interested for a deal?
>
> - [ Flexlm Cracker ]
From: [ Gozer, the Gozerian ]
John,
Off the top of my head I can name three easy ways to crack FLEX-lm without
adb. (If you publish these, give me the name "Gozer, the Gozerian", OK?)
The first way to bypass FLEX-lm is to simply keep resetting your system
clock to a day when your license keys were still legitimate. This does get
to be a hassle because companies like Cadence and ViewLogic use start
and end dates in their licensing forcing you to be resetting the system
clock quite often. Also, Cadence is rumored to do some nasty things if
it finds files newer than your current date in your system.
The second way is to 'steal' EDA licenses from other companies over the
Internet. All you need is a copy of the FLEX-lm license key from your
target company to get the server name and the port number FLEX-lm uses on
it. For example, if you used to work at Texas Instruments and you're now
at a small start-up that needs more Synopsys licenses than the one you
legally have, grep your copy of that TI license key for 'SERVER'. It'll
spit out something like 'SERVER achilles 55431234 995'. This says that
'achilles' uses port 995 for FLEX-lm keys. Ping ti.com to get their dotted
quad (192.94.94.33) and add '192.94.94.33 achilles' in your /etc/hosts to
make their machine local to you. After that, 'setenv LM_LICENSE_FILE
995@achilles.ti.com' on your machine. You now have those TI Synopsys
licenses for your machine.
This works because the net admin and EDA admin people don't interact much.
The net admin guy could easily stop me by blocking external access at the
firewall to those specific ports that FLEX-lm uses.
My third, and favorite hardware hacker way to bypass FLEX-lm, is by using
my PROM burner to copy my workstation's boot PROM. That way, all 16 of my
workstations have the same machine ID, they each run their own copy of
Synopsys/Cadence/whatever, yet I only pay for one copy. They're hell to
network together, though. Makes them not too useful for large chip designs.
- [ Gozer, the Gozerian ]
( ESNUG 310 Item 2 ) ----------------------------------------------- [2/7/99]
Subject: (ESNUG 309 #13) Need An Olde 1 micron Vgt300 Lib For Compass Ver. 8
> Does anyone have a 1 micron library (vgt300) for VLSI Technology, for
> Compass version 8 tools? We're trying to open an old schematic design.
> Thanks.
>
> - Craig Kuwahara
> Alcatel USA
From: Premysl Vaclavik <tnepva@neuroth.co.at>
Hi John,
Yes we have it. In fact, we have still complete archieve of COMPASS tools
and related libraries since 1992. If there is no problem with a VLSI
License agreement at your site you can have it. COMPASS forever!
- Premysl Vaclavik
Thomas NEUROTH GmbH
( ESNUG 310 Item 3 ) ----------------------------------------------- [2/7/99]
Subject: Exactly How Does The Sunrise Test "Autopilot" Program Work ?
> Does anyone know how the Sunrise autopilot works? I have a "design_setup"
> file, and I used "autopilot -compile -tsc -noview" commend to generate the
> .tsc files. What will the output file's name be and how many *.tsc files
> will be generated? If I want the *.tsc file to be rename, should I do some
> thing with the design_setup file?
>
> - Anne Liu
> National Semiconductor Santa Clara, CA
From: NUKALA RAVIKANTH <ravikanth@msemi.com>
autopilot is a perl program which helps in generating (and maintaining )
the tsc files from the design setup file. It also maintains directory
structure for the flow.
When you use autopilot -compile -tsc -noview , a compile.tsc is created in
.srfiles directory. You can see the tsc file in Compile directory also.
The name of the tsc file is <netlist_name>.tsc.
For each step of the Sunrise flow (like compile, sdrc, atpg, etc... )
autopilot generates a different tsc file which has the relavant commands
for that particular step and maintains them in relevant directories .
One thing to remember is Sunrise has no concept of multiple tsc files.
So, though Autopilot generates a tsc file for each step, it will also
take care in using the relavant one when running a step in the flow.
For example, when you run autopilot -atpg , autopilot automatically uses
atpg.tsc file (in .srfiles directory) when running the program.
- Nukala Ravikanth
Meridian Semiconductors Irvine, CA
( ESNUG 310 Item 4 ) ----------------------------------------------- [2/7/99]
Subject: ( ESNUG 309 #2 ) Speed Up This DC Script For Clock Domain Crossings
> I've got an existing design and I need to find all of the clock domain
> crossings in order to insert lockup latches for DFT. I could probably read
> through the code and find most of them, but I was hoping to automate it
> and catch all of them. I've written a dc_shell script that will do this,
> however the run time for this script is several days, even on an Ultra-10.
>
> Anybody have a faster script that can do the same thing? It can be a
> dc_shell script, perl or dc_perl or csh or whatever would be great. It
> just needs to be complete and fast(er).
>
> - Erik Trounce
> Nortel (Northern Telecom) Ottawa, Ontario, Canada
From: Ron Mehler <rmehler@dropzone.tamu.edu>
John,
Why not just let test compiler worry about that? Include the line:
set_scan_configuration -add_lockup true
and let it rip. I'm currently doing that on a 300k gate, 12 clock design.
It's working fine.
- Ron Mehler
Consultant
---- ---- ---- ---- ---- ---- ----
From: [ An AE In The Synopsys Support Center ]
John,
Below is a Design Compiler script which does what this user is looking for.
Users of PrimeTime might want to make a PT version instead, as PrimeTime's
efficient collections would allow it to run much faster.
This script could be written more straightforward, at the expense of more
runtime. However, using attributes on flops allows the use of a filter()
command to replace a lengthy foreach/if loop. Hopefully this is a cool
example of user-defined attributes, too!
You would use this script like so:
dc_shell>include cross_domain.scr
dc_shell>echo "The cross-domain flops in this design are" cross_domain "."
Here's my cross_domain.scr below:
clocks = find(clock)
ths_clk = "" > /dev/null
base_flop = "" > /dev/null
foreach(ths_clk, clocks) {
echo "Marking capturing data pins of domain" ths_clk "..."
data_pins = all_registers(-edge -clock ths_clk -data_pins) > /dev/null
if (data_pins != {}) {
set_attribute -quiet data_pins clock ths_clk -type string > /dev/null
}
dc_shell_status = 1
}
foreach(ths_clk, clocks) {
echo "Checking clock domain" ths_clk "as source of crossovers..."
out_pins = all_registers(-edge -clock ths_clk -output_pins) > /dev/null
if (out_pins != {}) {
echo " (determining total fanout)"
data_pins = all_fanout(-from out_pins -flat -endpoints_only) > /dev/null
echo " (making list of capture flops in other domains)"
set_attribute -quiet filter(data_pins, \
"(@clock > {}) && (@clock != ths_clk)") cross_domain true \
-type boolean > /dev/null
}
dc_shell_status = 1
}
cross_domain = {} > /dev/null
foreach(ths_clk, clocks) {
echo "Collecting cross-domain capturing pins from clock" ths_clk "..."
data_pins = all_registers(-edge -clock ths_clk -data_pins) > /dev/null
cross_domain = cross_domain + \
filter(data_pins, "@cross_domain == true") > /dev/null
remove_attribute -quiet data_pins clock > /dev/null
dc_shell_status = 1
}
Hope this helps!
- [ An AE In The Synopsys Support Center ]
---- ---- ---- ---- ---- ---- ----
From: Paul Carnaggio <Paul@syntest.com>
Dear John:
This question about finding Clock Domain Crossings went from ESNUG 309
Item 2 to one of the SynTest Engineers in Taiwan to L.-T. Wang ( President
of SynTest Technologies) to me. Isn't the net wonderful?!
Anyway, we have a Tool than can help this user called "TurboCheck-RTL."
SynTest Technologies of Sunnyvale, California specializes in DFT, Fault
Coverage Enhancements and Fault Simulations. You can visit our web page at
www.SynTest.com for company background and other technical information.
- Paul J. Carnaggio
SynTest Technologies, Inc. Pittsburgh, PA
---- ---- ---- ---- ---- ---- ----
From: William Liao <wliao@vadem.com>
Hi John,
On Synopsys's Solv-It website there is an article explaining how to do this.
I used the described method once, and it was fast for my design. Here are
the steps (using Erik's DC-shell variables):
/* group all paths into the default group */
group_path -default -to ckList
/* Mark all paths that start and end on the same clock as false paths,
and all those that start and end at ports */
foreach (ck, ckList) {
set_false_path -from find("clock", ck) -to find("clock", ck)
set_false_path -from find("clock", ck) -to all_outputs()
set_false_path -from all_inputs() -to find("clock", ck)
}
/* Now all remaining paths must cross clock domains */
report_timing
Regards,
- William Liao
Vadem
---- ---- ---- ---- ---- ---- ----
From: ehlers@sd.conexant.com (Steve Ehlers)
John,
Here's a script I put together based on an article on SolvNET that may
help this guy out.
/* Remove any existing false paths (we're trying to find clock crossers,
not mask them). */
reset_path -from all_clocks();
reset_path -to all_clocks();
/* Put all paths into a single path group. */
group_path -default -to all_clocks();
/* Ignore all normal paths (ones that start & end on the same clock). */
foreach ($clk, find(clock)) {
set_false_path -from find(clock, $clk) -to find(clock, $clk);
}
/* The SolvNET article recommends false-pathing to/from all
outputs/inputs, but that can mask clock crossing signals. If the
inputs and outputs are all properly constrained relative to their
respective clocks, only clock-crossing I/O's should show up in the
timing reports, making the next two set_false_path commands
unnecessary and undesirable.
*/
/*
set_false_path -from all_inputs() -to find(clock);
set_false_path -from find(clock) -to all_outputs();
*/
/* Show path details */
report_timing -path only -max_paths 100;
/* Shorter summary */
report_timing -path end -max_paths 100 -nosplit;
This should solve his problem...
- Steve Ehlers
Conexant Systems
( ESNUG 310 Item 5 ) ----------------------------------------------- [2/7/99]
Subject: (ESNUG 309 #3) Seeking Tools That Generate Memory BIST for DRAM's
> I am looking for a tool which can generate Memory BIST for DRAM's,
> something like the Mentor Graphics Memory BIST for SRAM's. Does anyone
> know of any such tool available in the market?
>
> - Manish Shrivastava
> Siemens Microelectronics (Asia Pacific) Ltd
From: reilly@kodak.com (Denis Reilly)
John,
As a follow-up, here are the bookmarks from the research I've done on Memory
BIST tools from my preliminary investigations:
http://www.lvision.com/solution/membist_ic.htm
http://www.lvision.com/solution/membist_xt.htm
http://www.tessi.com/membist.html (Not much info here)
http://www.mentorg.com/dft/catalog/mbista.html
Many thanks to the people on ESNUG who responded with information!
- Denis P. Reilly
Eastman Kodak Company Rochester, NY
( ESNUG 310 Item 6 ) ----------------------------------------------- [2/7/99]
From: plaberge@micronpc.com ( Paul LaBerge )
Subject: What's The Rest Of The Multibit Synthesis Components Story ?
John,
I'm wondering if anyone has seen vendor libraries that support multibit
components for Synopsys? How well has it worked? Has anyone used the
multibit feature without a multibit library? Has anyone used the multibit
component features of Synopsys to replace small register files or rams by
building layout macros?
- Paul LaBerge
Micron
( ESNUG 310 Item 7 ) ----------------------------------------------- [2/7/99]
Subject: ( ESNUG 309 #1 ) Interesting Benchmark Using Ambit *WITH* Synopsys
> Circuit3:
>
> Complete CPU, about 100K gates. Asking for 110Mhz with 78th percentile
> wire loads. Multiple path exceptions (both false and disabled paths)
> as well as several hundred latches used to guarantee hold times to an
> external RAM interface.
> BuildGates 2.0.4 DC 98.02
> total compile time 37hrs 29hrs
> area slack area slack
> stats at finish of compile 4900 -0.2 5395 -0.2
>
> Both results are from top down compiles from the behavioral code.
>
> Both circuits meet the clk->clk paths at 110Mhz (9.09ns period). With
> the -0.2 slack in CLK->Q paths that end at heavily loaded outputs.
>
>
> Summary
>
> The results are very similar. BuildGates does show a consistent area
> advantage of about 10% and a slightly longer compile time. It also
> looks like the capacity of BuildGates may be more limited than that
> of DC 98.02 as the compile time difference increased as the circuit gate
> count went up.
>
> - Jay McDougal
> Hewlett-Packard
From: Thomas Tomazin <thomas.tomazin@analog.com>
John,
I know of at least two comparisons where Ambit has a clear advantage -
static timing analysis and incremental optimizations. The design
I am working on is large (suffice it to say very large) and latch
based. There are multiple synchronous clock domains. There are
asynchronous clock domains. There are thousands of lines of multicycle
paths and timing exceptions. We compile all the subblocks in Synopsys,
then read all the gates for the entire chip into Ambit. Ambit reads
all the gates and produces a timing report in ~3 hours. It takes
Synopsys longer than that just to read the gates (I'm talking about
98.02) and after 48 hours didn't produce a timing report. After
the design is read into Ambit, I can do an incremental optimization
and get ~20% improvement in timing in about 2 days (Ultra 60 with 2G ram).
Of course, some of the improvement is probably due to poor constraints
in the original Synopsys runs. Area also improves by about 20%, but
the design is harder to place and route. So the real improvement is
with timing, area improvement is secondary.
By the way, we tried Primetime. It wasn't the right solution, and besides,
a superior timing engine is built into Build Gates (Ambit).
For smallish blocks, up to 10K gates, we haven't seen much difference
between Ambit and Synopsys. However, Ambit is an "enabling
technology" for very large incremental optimizations, and allows entire
chips to be statically timed without ever leaving the synthesis tool.
Important note:
When comparing negative slack between Ambit and Synopsys runs,
be aware that the 2 tools report slack very differently for latch
based designs.
Synopsys will report slack to some budget at each stage
(latch boundary), and propagate forward the ACTUAL arrival time
of the signal to downstream stages.
Ambit will report slack to some budget at each stage, but
only propagates forward the BUDGETed time, dividing the slack
across the stages.
Here's an example. Consider the following path:
lat1 ---- 6ns logic ---- lat0 ---- 4ns logic ---- Primary out(PO)
assume lat1 is transparent clock high, lat0 transparent clock low, and
an 8ns clock period. The PO is required at 8ns.
Synopsys will add the slack across the stages and report the total
negative slack for the entire path = -2ns at PO.
Ambit will divide the slack equally among the stages, and report
negative slack = -1ns at PO (and also at lat0).
The Ambit method of reporting slack indicates how much the 1/2 cycle
time needs to be increased to meet timing.
The Synopsys method indicates how much cumulative slack is in your worst
path. To get the equivalent Ambit number divide the Synopsys slack by
the total number of latch stages in the path (not always easy to figure!).
- Thomas Tomazin
Analog Devices Austin, TX
( ESNUG 310 Item 8 ) ----------------------------------------------- [2/7/99]
From: DrVGB@aol.com (Dr. Vincent G. Bello)
Subject: Putting Together SPICE History and SMPS SPICE Models History
John,
I have started compiling a SPICE History file and SMPS SPICE Model History
file on my AOL website (http://Members.AOL.com/DrVGB). If your readers have
any additions they would like to contribute, please email them to me along
with dates and references.
Check my AOL website to see the first drafts and any updates.
- Dr. Vincent G. Bello
Father of the Averaged SMPS SPICE Models
President, SPICE Simulations Co. Norwalk, CT
( ESNUG 310 Item 9 ) ----------------------------------------------- [2/7/99]
Subject: (ESNUG 308 #4) Initialization Test Compiler Problems (Split Chains)
> The problem I currently face with test compiler is that I have a design w/
> an embedded macro which requires initialization sequence to bring it into
> scan test mode. Also there are many scan chains in the design, that we
> decided to have two scan tests - one for one half of the design and the
> other for the other half. The choice of which scan test to select is done
> via external pins ("01" means enabling scan test for one half, and "10"
> means enabling scan test for the other half). These external pins are
> called TSTPAD1 and TSTPAD0.
>
> The requirement of initialization sequence means we have to modify the test
> protocol. So our ATPG script goes like this:
>
> set_test_hold 1 find(port, TSTPAD0)
> set_test_hold 0 find(port, TSTPAD1)
>
> check_test > pass1.dft_check
> write_test_protocol -out pass1.tpf
>
> Then we modify the initialization sequence of the test protocol, and then
> we do
>
> read_init_protocol pass1_mod.tpf
> check_test > pass1_mod.dft_check
>
> John, what we found very puzzling about this check_test report is that the
> TSTPAD(1:0) = "01" during the initialization vector, after which (during
> scan in & parallel vector), it is "10" ??????!!!! This is very puzzling,
> since the "pass1_mod.tpf" test protocol is based on "pass1.tpf" test
> protocol that we've written out in the first step, for which TSTPAD(1:0) is
> asserted to "01" always. Also, in "pass1_mod.tpf" we are leaving the
> ports TSTPAD(1:0) untouched, so the test_hold effect of the original test
> protocol should be passed to the "pass1_mod.tpf". Somehow this effect is
> not as expected.
>
> Does anyone know what might have gone wrong? I'd be most grateful if you
> can shed some light on this issue.
>
> - Suttinan Chattong
> Cyberway Singapore
From: [ A Synopsys Test Guy ]
Hi John,
I work at Synopsys in the Test Products Application team. I would like to
answer Suttinan Chattong's email regarding the use of read_init_protocol.
The command read_init_protocol allows the user to read the initialization
portion of a test_protocol. What we call the "initialization part" is the
section of this file contained between the
"foreach_program(){" and "...} foreach_patterns(){"
statements. This corresponds to vectors applied to the ASIC before the scan
testing proper starts with the shifting in of the fist scan vector. Only
changes in this part of the protocol will be taken into consideration by
check_test after a read_init_protocol command. That's why after reading
the modified protocol Suttiman does not observe the right value during shift.
To force a value on a port during all the test session you need to use the
command set_test_hold. The flow I would then advise is:
set_test_hold 1 find(port, TSTPAD0)
set_test_hold 0 find(port, TSTPAD1)
check_test > pass1.dft_check
set_test_hold 0 find(port, TSTPAD0)
set_test_hold 1 find(port, TSTPAD1)
check_test > pass1_mod.dft_check
Best regards,
- [ A Synopsys Test Guy ]
( ESNUG 310 Item 10 ) ---------------------------------------------- [2/7/99]
Subject: ( ESNUG 309 #9 ) Trying To Model A Complex Cell In Library Compiler
> I to my final year project at Fachhochschule in Nueremberg/Germany. I want
> to create a new cell within the Synopsys Library Compiler.
>
> _____
> | |
> A----------------------|> |
> ____ _____ | |---------
> B---| |----| |--| FF |
> |mux | |latch| | |
> 0---|____| | | |_____|
> | | |
> sel__| | |
> ______________|> |
> |____ |
>
> Relationship between A and B
>
> A______--____
> B__--________
>
> I couldn't get the statetable right and have also problems with the pin
> describtion. It would be very kind of you, if you can give me some tips
> and tricks about this.
>
> - Klaus Gottschalk
> Fachhochschule Nueremberg, Germany
From: [ A Synopsys Library Compiler Guru ]
Hi John,
I have a statetable for the diagram Klaus has provided. However I am not
clear about a couple of things. First, I don't know, whether it's a zero
or the alphabet "O" on the mux. I have statetables for both the conditions.
Also he has not specified whether the latch is active high enable or active
low enable. I have assumed it as active high enable. For the pins, the
only additional thing that you need to do is have an additional internal
pin. This would be the pin which is the output of the latch. Let's call
it "I". Here is the statetable.
If the second input of mux is zero the table will look like this:
statetable ("A B sel G(latch gate)", "I Q") {
table : " - H/L L H :- -: H/L -,\
- - H H :- -: L -,\
- - - L :- -: N -,\
R - - - :H/L -: - H/L,\
~R - - - :- -: - N";
}
If the second input is "O" the table will look like this:
statetable ("O A B sel G(latch gate)", "I Q") {
table : " - - H/L L H :- -: H/L -,\
H/L - - H H :- -: H/L -,\
- - - - L :- -: N -,\
- R - - - :H/L -: - H/L,\
- ~R - - - :- -: - N";
}
Hope this helps in solving his problem.
- [ A Synopsys Library Compiler Guru ]
( ESNUG 310 Item 11 ) ---------------------------------------------- [2/7/99]
Subject: (ESNUG 308 #7) All In All, I Was Rather Disappointed With LSF
> Overall, I don't think I can say enough good things about LSF - but don't
> tell them that, they'll just want to raise their prices.
>
> - [ The Cisco Kid ]
From: "David C. Hoffmeister" <dch@eng.umd.edu>
John,
I've been reading your ESNUG column for three years now and this is the
first time I have felt the need to contribute. I just had to respond to
the comments praising LSF. While finishing my research for my Ph.D.
dissertation recently I was able to gain access to a cluster of Sparcs
at the Naval Research Lab. I was not using it for ASIC design but for
running discrete-event simulations of a computer network. I can only say
that either the LSF system at NRL was not configured and maintained well
or else the software is not all that reliable. I do know that NRL claimed
to be having problems integrating LSF with AFS and Kerberos, both of which
they were using. They also only had one queue set up for submitting jobs
to. So, the overall configuration may have been causing some problems.
My main gripe is the control of job submission. I think they could improve
the default job submission to be more intelligent. I had jobs that required
very little memory and were completely cpu bound. So, it would have been
nice if the default job control chose the most lightly loaded cpu and
dispatched my job there. This was not the case. Often my jobs were
submitted to hosts that had more than one job per cpu already while other
hosts had multiple idle cpus. It took a significant amount of work on my
part writing resource requirements for my jobs before I got approximately
what I wanted. On top of that, if I submitted too many jobs at once, even
with resource requirements, it allowed all of them to run and swamped the
system.
I was forced to use a Perl script (written by a fellow graduate student) to
check the number of jobs I was running and submit jobs as old jobs
completed. It was not convenient at all.
I also found that some of my jobs would continue running for more than a
full day. When I killed these jobs they would often report results as if
they had finished normally. I don't know how long they would have remained
in limbo if I had not killed them manually.
All in all, I was rather disappointed with LSF. Maybe I expect too much
functionality without a great deal of work. And, as I said, I cannot
guarantee that the system was installed and maintained properly.
- David C. Hoffmeister
University of Maryland
( ESNUG 310 Item 12 ) ---------------------------------------------- [2/7/99]
From: Gopi Reddy Sirineni <gopi@idt.com>
Subject: Any Tools To Convert Verilog To State Machines Or Flow Charts ??
Hi, John,
Does anybody aware of any tool out in the market which can take Verilog code
as a input and gives FLOW CHART or STATE MACHINES as a result ? I'm trying
to do a extention of a existing chip where I need to understand the
implementaion but not much documentaion is available for me.
I know there is a tool which generates code from state machine or flow chart
(Design Book of Escalade), but I need the other way.
- Gopi Sirineni
Integrated Device Technology, Inc. San Jose, CA
( ESNUG 310 Item 13 ) ---------------------------------------------- [2/7/99]
Subject: Cadence Sales Doesn't Like Selling Ambit To Small Customers
> We are having trouble getting the attention of our local Cadence sales folk
> to get a price and demo of Ambit. If you know, could you forward me the
> email address of the VP of sales for Cadence so I may properly complain?
>
> - Mike Dini
> The Dini Group
From: Mike Dini <mdini@dinigroup.com>
John,
We got one response from a Cadence sales guy on the east coast, and my
local people woke up about two days after distribution of ESNUG. As best we
can determine, Ambit is a very legitimate competitor to Synopsys -- in many
ways doing synthesis much better. (Remember, I run a consulting firm &
Synopsys will *not* sell us Design Compiler without absurd restrictions. So
my choices are Ambit, Exemplar, or nothing.) Unfortunately, we must now
deal with Cadence sales people rather than the hungrier, more pleasing Ambit
sales people of the past. Cadence, in this regard, seems be learning the
bad habits of Synopsys. "You want to order only $150k worth of products
from us? Why did you bother to call? Where did you get my number? That
small of an order isn't worth my time! Go away!"
- Mike Dini
The Dini Group
( ESNUG 310 Item 14 ) ---------------------------------------------- [2/7/99]
Subject: ( ESNUG 308 #1 309 #11) Tcl/Tk Doesn't Cut It; Want Perl Instead
> Does this look like a modern scripting language?
>
> set x [ expr $period / 2 ]
>
> Tcl is a bit better than the current dc_shell language, but only a small
> bit. Why couldn't Synopsys have picked perl or one of the other higher
> level scripting languages?
>
> I tried to write a histogram routine in tcl, for PrimeTime, it was ugly
> and slow. Perl did most of the work in one line with an associatve
> array (hash).
>
> - Don Reid
> Hewlett Packard, ICBD
From: Larrie Carr <Larrie_Carr@pmc-sierra.com>
John,
I agree as I, too, hate set x [expr 2 + 2]! I think languages have evolved
to a certain level of context sensitiveness. Same goes for perl with the $
in the $variable notation.
- Larrie Carr
PMC-Sierra, Inc. Vancouver, B.C., Canada
> From [ A Synopsys Techie ]
>
> Just a note, Tcl has arrays that are similar to the ones in Perl.
From: Don Reid <donr@hpcvcdo.cv.hp.com>
John,
That [ Synopsys Techie ] is right, Tcl does have an array that is similar
to a Perl's hash.
I know I had some problem coding a histogram in Tcl and that Synopsys
R&D could not tell me a better way to do it. I seem to have lost the
code and I cannot recall the details. If I find the code I will follow
up with the specific problem.
- Don Reid
Hewlett Packard, ICBD
( ESNUG 310 Item 15 ) ---------------------------------------------- [2/7/99]
From: Andrew Pagones <Andy_Pagones-ACIC22@email.mot.com>
Subject: Is Modeling Load-Dependent Pins An Afterthought For Synopsys ???
John,
Anyone, anywhere, could you please share any experience you have modeling
load-dependent cell library pins.
The 98.08 manuals devote a whopping 3 pages to this topic in what looks
like an afterthought, not a real feature. I say this because load dependent
timing appears to be supported *only* for constraint arcs, not delay or
combinational arcs. Why in the world would that be so?
- Andy Pagones
Motorola Chicago Corporate Research Laboratories
( ESNUG 310 Networking Section ) ----------------------------------- [2/7/99]
Kauai, Hawaii -- engineer w/ own Sun & high-speed lines seeks telecommute
verilog ASIC design & verification work, Brian Balthazor, "bbal@kauai.com"
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