In his ESNUG 1998 X-mas Lampoon, John Cooley wrote:
> ... I want anyone who was involved with Frameworks fired. Grrrr...
> I want <mumble mumble> FIRED! Bah-humbug!
>
> I'm just having a bad hair day today.
>
> - Wally
>
> P.S. I want my damn useless hairdresser fired, too! (Who needs them?)
>
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> "A Bad Day Fishing Always Beats A Good Day At Work"
> Walden Rhines CEO of Mentor Graphics wally@mentorg.com
From: [ The Lord Works In Mysterious Ways ]
John,
Loved your 1998 ESNUG X-mas. Especially the Cadence and Avant! letters.
For your personal well-being, though, I sure hope Wally isn't religious,
'cause if he is, it's all here with Elijah in 2 KINGS 2:23-24.
"Then he went up from there to Bethel; and as he was going up the
road, some youths came from the city and mocked him, and said to
him, "Go up, you baldhead! Go up, you baldhead!"
"So he turned around and looked at them, and pronounced a curse on
them in the name of the Lord. And two female bears came out of the
woods and mauled forty-two of the youths."
So always remember, John, God has a warm spot in his heart for the
Folliclely Challenged like me and Wally! :)
If you use this, please don't publish my name. Keep up the good work!
- [ The Lord Works In Mysterious Ways ]
( ESNUG 308 Item 1 ) ---------------------------------------------- [1/99]
Subject: ( ESNUG 304 #10 ) New Synopsys Tcl Is Wrapped Around Old Dc_shell!
> Dc_shell does suck and designers have complained about it for years (it
> always feels good to know that you're not the only one suffering).
> DC_shell was a hack that got the job done, and you have to give Synopsys
> credit for that (it got you 80% there very quickly). Dc_shell is only
> part of the problem - inconsistent command structure and arguments are
> another (forcing designers to play adventure).
>
> Next year Synopsys will incorporate Tcl/Tk into their tools (Synopsys
> was one of the investors in Professor Ousterhout's company that will
> take Tcl/Tk to the next level). Definitely Anonymous.
>
> - [ Tickle Me Elmo ]
From: Larrie Carr <Larrie_Carr@pmc-sierra.com>
John,
I just saw this new tcl/tk environment (my Synopsys Salesdroid punching bag
brought it in when he was demoing something else). These are my opinions
of the new Synopsys tcl/tk only after an hour's play...
If you think that this environment is going to bring some of the cool
features of PrimeTime, you will be disappointed. In reality, it is
just a Tcl/Tk shell wrapped around dc_shell so the features and limitations
of dc_shell are still there.
For instance, report_attribute in PrimeTime has a -app option which will
allow you to see all attributes on an object. The new Tcl/Tk dc_shell
contains the same dc_shell report_attribute which is not as user friendly.
For now, we have been writing PrimeTime scripts which spit out a dc_shell
script (create_cell, connect_net, etc) when something simple has to be fixed
(like a hold time violation). For some of my designs which are very
asynchronous in nature, the set_case_analysis is great for analysis. But
trying to get the dc tool to work is a pain without set_case_analysis so
Tcl/Tk to the rescue.
I'm not saying Synopsys is going the wrong direction. It is that they are
trying to save some of the dc_shell scripts for now by not *integrating*
Tcl/Tk, just wrapping Tcl/Tk around dc_shell.
- Larrie Carr
PMC-Sierra, Inc. Vancouver, B.C., Canada
( ESNUG 308 Item 2 ) ---------------------------------------------- [1/99]
Subject: (ESNUG 307 #11) Can I Put Text In DBs Made By Library Compiler ?
> Has anybody discovered a way to compile text strings into a db library
> with Library Compiler? We have groups within Ford who we make custom
> db libs for. We have engineers run off with a db lib, make a chip, and
> then they come back asking: "Did that db lib use the XYZ spice data?"
> or "Was the 1-2-3 bug fixed with that db lib we used?" I can't, nor
> can my db lib "customers", currently just use Design Compiler to look
> at the db to find text strings that I'd like to put into db libs that
> contain comments / text strings about revs, date created, bugs fixed,
> spice assumptions, etc. I suppose you could create some kind of phoney
> model with ascii encoded "delays", but I'd like to know if there's a
> better way to do this.
>
> - Rodney Ramsay
> Ford Microelectronics
From: dchapman@goldmountain.com (Dave Chapman)
John,
An ugly but effective way to do this is to define a ROM which contains the
string data you want, and then have the user instantiate the ROM when they
want to read the ID string.
The problems with this speak for themselves, but it will do the job.
Obviously, you do not instantiate the ROM for the final tape-out.
I hope somebody out there has a better suggestion.
- Dave Chapman
Goldmountain
---- ---- ---- ---- ---- ---- ----
From: Bob Cook <RJCook@ieee.org>
John,
In the Synopsys-format library source code:
define (my_attribute, library, string) ;
my_attribute : "Hey, I can set my own library string attribute."
Then, in Design Compiler:
dc_shell> get_attribute find(library, TECHLIB) my_attribute
Performing get_attribute on library 'TECHLIB'.
{"Hey, I can set my own library string attribute."}
Defined attributes can be of type string, integer, or float. And they
can be assigned to a library, cell, pin, etc.
- Bob Cook
R.J. Cook Associates, Inc.
---- ---- ---- ---- ---- ---- ----
From: Helmut Reinig <helmut.reinig@hl.siemens.de>
John,
Yes, you can do such a thing by adding user-defined attributes to your
library. They can be retrieved by get_attribute in Design Compiler. The
library source code looks like this:
library (<your library>) {
...
define (<attribute_name>, library, string);
<attribute_name> : "<attribute_value>";
...
}
Hope this helps.
- Helmut Reinig
Siemens Semiconductors Munich, Germany
---- ---- ---- ---- ---- ---- ----
From: Jean-Marc Calvez <jean-marc.calvez@st.com>
John,
There are always the "version" and "comment" library attributes; they will
show up in a report_lib. I don't know how much info you can put in comment
but I remember using a string over 1KB long once in a .lib file.
- Jean-Marc Calvez
STMicroelectronics Grenoble, France
---- ---- ---- ---- ---- ---- ----
From: cjy@aluxs.micro.lucent.com (Chris Younger)
John,
User defined attributes are very easy to add to .lib source. First define
the attribute in the library header:
define ("attribute_name", "group_name","attribute_type");
where attribute_name = name of attribute
group_name = name of group in which attribute is used (pin,
cell, etc)
attribute_type = string, integer or float
For example, for version strings added to each cell in the library:
library("FOO") {
...
define ("xyz_co_ver","cell","string")
...
cell("MY_CELL") {
xyz_co_ver : "created 12/98: spice=v3.1: gds=v5.0: translator=v1.0"
...
}}
To extract the info from the db use get_attribute:
get_attribute FOO/MY_CELL xyz_co_ver
Hope this helps.
- Chris Younger
Lucent Technologies
---- ---- ---- ---- ---- ---- ----
From: [ Synopsys R&D ]
Hi, John,
I'm in Synopsys R&D, and in my past I worked quite a bit on Library Compiler.
There is an easy way to do what you're asking, using user-defined attributes.
Actually there are two ways, depending on whether you want to annotate the
source '.lib' or if you want to annotate the db after it has been processed
by read_lib.
1) You can create your own attributes in a '.lib' file using the
"define" construct, at the library-level of your description.
For example,
library (demo) {
define( new_attr, library, string );
...
defines a new user-defined attribute named 'new_attr'. If you
want to supply a value for it, you could follow its definition
with the line
new_attr : "whatever string you want";
To find out the values of your user-defined attributes once the
library has been compiled, you use the 'get_attribute' command:
get_attribute find(library demo) "new_attr" -quiet
{"whatever string you want"}
The 'define' construct is quite flexible. It can create attributes
of type 'string', 'float', or 'integer'. It can create such
attributes on all the primary object types in your library (library,
cell, pin, ...). You cannot redefine an existing attribute, that's
about the only limitation (probably a good one).
This should be documented in the LC manual.
2) If you want to tag a library AFTER it has been compiled via read_lib,
you just use the 'set_attribute' command:
set_attribute find(library demo) "newer_attr" "some value" -type string
John, if you post this please keep my name anonymous.
- [ Synopsys R&D ]
( ESNUG 308 Item 3 ) ---------------------------------------------- [1/99]
Subject: (ESNUG 306 #3 307 #5) Bizarre 13 - 41% Area Increase W/ Aspec Libs
> I'm using Aspec libraries, and Synopsys 1998.02 and 1998.08.
>
> Even though I use no rams in my design, my design team shares a common
> setup script, therefore a "ram.db" is added into everyone's (including my)
> link_library and target_library.
>
> Here's the problem: Although I don't have any rams in my design, the areas
> increase about 15% to 40% if the *unused* Aspec RAMs are linked in!
>
> I submitted this bug to Synopsys two months ago. They re-produced the
> problem but no workarounds for me so far. They talked to Aspec and looked
> over their .lib source and report that it appears to be OK. When I tried
> all three above scenarios using Cascade libraries, I didn't have any area
> problems at all. (The main difference between Aspec libs and Cascade libs
> is that Aspec uses table lookup timing model, Cascade however uses
> piecewise linear model. I don't think this means anything, but it is a
> known difference between the two libs.)
>
> It's been two months. I can't wait any more. Did anyone run into the
> same situation? Any solutions? Thanks.
>
> - Eugene Ko
> Aureal Semiconductor
From: john brooks <jbrooks@brooktree.com>
Hi John,
We had same problem.
Our workaround was to NOT put the ram.db in the target library. You only
need this in the link library.
Thus, the ram lib won't be used during synthesis.
- John Brooks
Brooktree
( ESNUG 308 Item 4 ) ---------------------------------------------- [1/99]
From: "Suttinan Chattong" <suttinan@cyberway.com.sg>
Subject: Inexplicable Initialization Test Compiler Problems (Split Chains)
Hi John,
This is the first time I'm posting to ESNUG, I hope I'm posting this
message to the right place.
The problem I currently face with test compiler is that I have a design with
an embedded macro which requires initialization sequence to bring it into
scan test mode. Also there are many scan chains in the design, that we
decided to have two scan tests - one for one half of the design and the
other for the other half. The choice of which scan test to select is done
via external pins ("01" means enabling scan test for one half, and "10"
means enabling scan test for the other half). These external pins are
called TSTPAD1 and TSTPAD0.
The requirement of initialization sequence means we have to modify the test
protocol. So our ATPG script goes like this:
set_test_hold 1 find(port, TSTPAD0)
set_test_hold 0 find(port, TSTPAD1)
check_test > pass1.dft_check
write_test_protocol -out pass1.tpf
Then we modify the initialization sequence of the test protocol, and then
we do
read_init_protocol pass1_mod.tpf
check_test > pass1_mod.dft_check
John, what we found very puzzling about this check_test report is that the
TSTPAD(1:0) = "01" during the initialization vector, after which (during
scan in & parallel vector), it is "10" ??????!!!! This is very puzzling,
since the "pass1_mod.tpf" test protocol is based on "pass1.tpf" test
protocol that we've written out in the first step, for which TSTPAD(1:0) is
asserted to "01" always. Also, in "pass1_mod.tpf" we are leaving the
ports TSTPAD(1:0) untouched, so the test_hold effect of the original test
protocol should be passed to the "pass1_mod.tpf". Somehow this effect is
not as expected.
Does anyone know what might have gone wrong? I'd be most grateful if you
can shed some light on this issue.
- Suttinan Chattong
Cyberway Singapore
( ESNUG 308 Item 5 ) ---------------------------------------------- [1/99]
Subject: (ESNUG 306 #13 307 #2) Routing Layer Preferences Per Pin In DC Libs?
> I found that our Apollo P&R tool supports boolean pin swapping only to fix
> timing violations, but not for routing length reduction. Bummer. Now I
> gotta beat on the code developers (some more...)
>
> - Andy Pagones
> Motorola Chicago Corporate Research Laboratories Chicago, IL
From: Michael Rockenhauser <rocky@avanticorp.com>
John,
The issues raised here - that either the router or verification tool are
unable to handle EEQ pins, is rubbish. Those issues mentioned in this
thread about custom layout not matching the switch-level netlist: those
blocks are often black-boxed and DRC'd separately.
Handling electrical equivalence is a basic capability for both Apollo and
Hercules. Obviously, these aren't Avant! customers. If they were in
Milkyway, these issues would not exist.
- Michael Rockenhauser
Avant! Corporation Derry, NH
( ESNUG 308 Item 6 ) ---------------------------------------------- [1/99]
Subject: Cheap, Stolen Cadence, Mentor, Synopsys Software From FLEXlm Crack?
> From: flexlm@hotmail.com
> Date: 1999/05
> Newsgroups: comp.cad.cadence
>
> Hi,
>
> Many softwares (like Solaris software design kit, Cadence, Synopsys,
> Specctra) on UNIX use FLEXlm as their license manager, but FLEXlm is not
> secure, it can be cracked. Is anyone interested? Please email to:
> flexlm@hotmail.com.
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
From: miller@symbol.com (Wayne Miller)
Hi John,
Saw this on comp.cad.cadence. Is this the beginning of the end?
- Wayne Miller
Symbol Technologies, Inc.
[ Editor's Note: This got me curious, so I wrote the enigmatic
"flexlm" poster to find out more. Here's the exchange. - John ]
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
To: flexlm@hotmail.com
What's up with this Flex-LM crack?
- John
---- ---- ---- ---- ---- ---- ----
From: "Flexlm Cracker" <flexlm@hotmail.com>
To: jcooley@world.std.com
Hi,
FLEXlm on UNIX is not secure, do you have something to crack?
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
To: flexlm@hotmail.com
Please explain. How do you do this?
- John
---- ---- ---- ---- ---- ---- ----
From: "Flexlm Cracker" <flexlm@hotmail.com>
To: jcooley@world.std.com
Hi,
I use adb to crack, it is tiring, so this service is not free. :)
Are you interested for a deal?
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
To: flexlm@hotmail.com
Just curious: are you, or have you ever been, an Avanti employee?
- John
[ Editor's Note: The "Flexlm Cracker" never bothered to reply any further
e-mails after I asked him/her that question! Hmmmm... :^) - John ]
( ESNUG 308 Item 7 ) ---------------------------------------------- [1/99]
Subject: (ESNUG 304 #6 305 #11) Pros/Cons Running EDA On SUN Compute Farms
> We made the change, and I like it a lot. Before, when we needed to run
> a big job, it was a mess, both network and CPU-wise. Now we have one big
> iron: it's as if you had the whole system for yourself. Of course it has
> to be dimensioned very carefully otherwise everybody will be slowed down.
>
> The problem: any downtime and your whole department is on holidays. But
> it's so much easier to administer too. But I'm not saying it's cheaper
> (it probably isn't). One of the drawbacks is upgrade: a powerful
> configuration today will seem low-end in one year. It's easier to replace
> workstation after workstation, but changing the big iron is not always so
> cost-effective. Try to negociate a good upgrade deal.
>
> - Alain Raynaud
> Mentor Graphics Meta Systems Division
From: [ The Cisco Kid ]
John - Call me "The Cisco Kid"
In my group here at Cisco we use a system based on LSF from Platform
Computing. Most of the engineers have a single PC CPU on their desks with
two monitors, running Reflection X server s/w. To do the compute-intensive
tasks, we have a compute cluster set up with about 35 total CPUs (in 18
machines), as well as after-hours access to the remaining high-speed
desktop CPUs. The users submit jobs to a queue, which has very
fine-grained control (hours of operation, number of jobs per user,
grouping, etc.) and it is then started on the appropriate machine.
Users can specify many different parameters to control which machine gets
the job (memory requirements, run time, swap needed, tmp space needed) and
all output can be either directed to a file to the user's email. It does a
great job of smoothing out high-demand periods (sometimes the jobs may take
overnight to run) without requiring any input from the users. If there are
high-priority jobs that need to be run, the administrators can either bump
them up in the normal queue, or a high-priority queue can be set up to push
those jobs through faster. Also, there is an "interactive" queue which
users start interactive jobs on so they don't have to find a machine and
log directly in to it.
Previously, we had a few compute servers that were used interactively,
where users had to hunt around for one that wasn't being used then start
their jobs and hope that no one else came in and started another one,
killing the performance. Also, each engineer had two machines on his desk,
a PC for administrative work (Word, Excel, PowerPoint, etc.), and a Unix
box to do their "real" work.
The users that have switched love it. The extra desktop space allowed by
using two monitors really helps when you're editing lots of text files, and
Reflection has a virtual desktop manager so you can have multiple
"desktops" - kind of like CDE or olvwm. The managers love it, since we
don't buy one CPU for the compute cluster for each engineer, and the ones
we buy are used more efficiently. They also like it since they can easily
monitor usage and base purchase decisions on current usage and future
requirements - it's a lot harder to get that kind of information from a
non-managed cluster.
Overall, I don't think I can say enough good things about LSF - but don't
tell them that, they'll just want to raise their prices.
- [ The Cisco Kid ]
( ESNUG 308 Item 8 ) ---------------------------------------------- [1/99]
From: "Charles H Small" <charles.small@worldnet.att.net>
Subject: How To Run UNIX & NT Programs Simultaneously On One PC Or Server
John,
Lost in the welter of "Windows vs. NT" punditry from the trade press is the
little recognized fact that UNIX is a subset of NT. Bill Gates hired a
group of professional operating system writers away from DEC and set them to
work to craft a real OS with lots of interfaces. NT comes with, naturally,
WIN16 and WIN32 interfaces as well as OS/2 (bad guess there). But there is
also a POSIX interface -- designed right in to run UNIX programs compiled as
native PC code. The POSIX interface has been in NT from day one.
Not wanting to appear to be competing with itself, Microsoft licensed the
source code to Interix (http://www.interix.com) a couple of years ago. With
Interix's software you can run both NT and UNIX programs simultaneously on
the same PC or server. If you are familiar with how a DOS window pops up in
Windows, then you can envision exactly what a UNIX window would look like.
The latest development from Interix is a method for encapsulating a UNIX
program in a Microsoft COM wrapper, making it a dll that any Windows program
or script can call.
InteriX is NOT a UNIX emulator.
I would assume that when Intel is ready with the 64-bit processors,
Microsoft will have added a WIN64 interface. Whether or not Interix
software will be upgraded to run 64-bit UNIX program I can't say.
- Charles H Small
Senior Technical Editor
Electronic Systems Design & Technology Magazine San Jose, CA
( ESNUG 308 Item 9 ) ---------------------------------------------- [1/99]
From: [ Kenny from South Park ]
Subject: Synopsys DW -- Finding What's Available & Forcing DC To Use It
John,
Synopsys DW components are a useful "short cut" for IP. These are little
clusters of wonderful bits of VHDL and Verilog already debugged and ready
to go for the user.
Here's how I do it:
For VHDL RTL code for these various packages, go to the following directory:
$SYNOPSYS/DWXX/src/DWXX_function.vhd
for the entity and
$SYNOPSYS/DWXX/src/DWXX_function_sim.vhd
for the "sim" architecture and "DWXX_function_cfg_sim" configuration.
Compile these into a library called "DWXX" where "XX" is the number of the
DW library (ex DW04).
You will also need the following package in a library call "DWARE" in order
to compile these functions:
$SYNOPSYS/packages/dware/src/DWpackages.vhd
For Verilog, all you have to do is go to:
$SYNOPSYS/DWXX/src_ver/DWXX_function.v
I find these a wonderful way to "force" Synopsys to implement things
the way I want it to.
For example, let's take the following code:
A <= B * C;
By default, Synopsys will create a "Carry-save array synthesis" or "csa"
model of this part, which is a simple, low area, low speed version of a
multiplier -- about the worst possible choice you would want for a
multiplier.
To force Synopsys to use a much faster "Booth-coded Wallace tree" or "wall"
model, you have to do this:
constant R0: resource :=0;
attribute map_to_module of R0: constant is "DW02_mult";
attribute implementation of R0: constant is "wall";
attribute ops of R0: constant is "mul1";
begin
A <= B * C; -- pragma label mul1
Ugly, isn't it? But it works. And it's fully debugged.
- [ Kenny from South Park ]
( ESNUG 308 Item 10 ) --------------------------------------------- [1/99]
Subject: User Comments On Ambit vs. A 4.5 Year Old Verson Of Synopsys
> I am sure this has been asked a million times but I am relatively new to
> this group. I am looking into getting a synthesis tool and I am curious
> what the different design engineers (not sales reps) have to say about
> Ambit vs. Synopsys, pros and cons. We presently uses Cadence's layout
> and schematic editor and our designs are in the 1-10M gate range. I may
> also be interested in additional auto-place and route tools as well but
> at a minimum I will need to get gate level netlists from Verilog XL
> behavioral or RTL code.
>
> - Mike Pearson
From: jerry english <jenglish@planetc.com>
I have used both. I am not an expert by any means. I used Synopsys DC 3.1?
and found it to be slow. I now use Ambit's BuildGates, it is fast in
reading the design and in synthesis. May I suggest you call both of them
and get an evaluation copy for your own consideration. IMHO, feature for
feature, dollar for dollar Ambit comes out ahead over Synopsys.
Well, they did before Cadence bought them. It remains to be seen if the
value stays for Ambit, but that's a whole new thread.
- Jerry English
Planet C
[ Editor's Note: This is *really* lame because he's comparing a current
version of Ambit versus a 4.5 year old version of Synopsys. Lame!
Does anyone have any current rev to current rev comparisons? - John ]
( ESNUG 308 Item 11 ) --------------------------------------------- [1/99]
From: David Black <dcblack@qualis.com>
Subject: Five Classic Mistakes Using Verilog "Disable" Within BC
John,
Behavioral Compiler supports the use of Verilog's 'disable' to emulate
VHDL's 'exit' and 'next'. This works if you follow their official examples
closely; however, overuse can lead to problems. Here are five common
mistakes I've found using "disable" in BC:
MISTAKE 1. Disabling the wrong block
begin :LOOP forever begin :BODY
@(posedge clock);
if (COND1) disable BODY; // equivalent to VHDL 'NEXT'
if (COND2) disable LOOP; // equivalent to VHDL 'EXIT'
end end
All too often, engineers leave out the enclosing begin-end pair. It seems
more natural; however, Verilog rules dicate that the inner begin block is
not connected with the forever.
MISTAKE 2. Asserting outputs and disabling without an intervening
clock:
request_out <= 1;
@(posedge clock);
begin :LOOP forever begin
if (acknowledge_in == 1'b1) begin
request_out <= 0;
disable LOOP;
end
@(posedge clock);
end end
Verilog-XL simulation will reveal that request_out never gets set to zero.
This behavior differs from VCS which will provide the expected zero. The
reason for Verilog-XL is that all events scheduled within a block that
gets disabled are removed from the event queue. In this case, 0 was
scheduled to be placed on request_out, but the disable cancelled it.
Verilog semantics consider this behavior as unspecified and hence both
simulators are within legal bounds. Insertion of @(posedge clock) before
the disable will fix this problem both from a simulation and synthesis
point of view.
MISTAKE 3. Attempting to disable more than one level of hierarchy Verilog
allows disabling any block from a simulation point of view. Unfortunately,
BC does not support exiting more than a single level of loop hierarchy.
This should be addressed in a future BC version (time unspecified).
MISTAKE 4. Disabling a labeled block not associated with a loop Verilog
semantics allow for disabling many things. Intuitively, disabling a block
is nice as an error escape mechanism. In code:
begin :CODE_SEQUENCE
...
if (ERROR_CONDITION) begin
error_flag = 1;
disable CODE_SEQUENCE;
end
...
if (ERROR_CONDITION) begin
error_flag = 1;
disable CODE_SEQUENCE;
end
...
if (ERROR_CONDITION) begin
error_flag = 1;
disable CODE_SEQUENCE;
end
...
if (ERROR_CONDITION) begin
error_flag = 1;
disable CODE_SEQUENCE;
end
...
end //CODE_SEQUENCE
Unfortunately, Synopsys does not support this at the present time. For some
designs this appears to work occasionally (can you say "feature" with a sly
grin???).
Their work-around involves setting a bogus variable to true and using a loop
that ends with a test that unconditionally exits. Unfortunately, there is
a drawback to this that is discussed in Mistake #5 below.
MISTAKE 5. Too many disables leads to long schedule times Synopsys has a
complexity problem if the number of states and transitions gets too large.
Because BC looks for the best places to place operations, when the number
of states and transitions gets large, the search space can get large
exponentially. This leads to slow scheduling by the tool. This is related
to Synopsys' recommendation that the number of operations be kept under 150
(artificial number) viewed from another angle. If there are a large number
of operations OR transitions, then there are a large number of combinations
to consider. The number of considerations directly impacts the tools
performance.
- David Black
Qualis Design
( ESNUG 308 Item 12 ) --------------------------------------------- [1/99]
From: Brian Boorman <bboorman@harris.com>
Subject: How To Make A Clock Doubler With A FF, An Inverter, & An XOR Gate
There at one time was an App Note from Xilinx on clock doubling. If you
look in an older data book you should be able to find it. (My
interpretation is below.) The caveat is that while frequency is double,
high time pulse width may not be constant as it depends on routing delays.
___________________________________________
| |
| |\ |
| | \ _________ |
O-------------------| |O---| D Q |-----O
| _____ | / | |
|______| | |/ | |
| | | |
| XOR |----o---------|> |
1x CLK _______________| | | | |
|_____| | |_____R___|
| Reset_______|
|___________________________> 2x CLK
Be very careful to ensure that the high pulse meets your device minimum
pulse width requirements. The sum of the Flip-Flop Clock-to-Q delay, route
delay Q-to-Xor, and prop delay through Xor, total of these three will be
your 2xCLK high time.
- Brian C. Boorman
Harris RF Communications Rochester, NY
( ESNUG 308 Item 13 ) --------------------------------------------- [1/99]
From: Mike Klein <klein@chromatic.com>
Subject: Seeking Pointers On Super-High Performance Synthesis/P&R Approaches
John,
I'm on your ESNUG mail list and have been reading your great info source for
years now. I have a question, actually more a request for pointers,
regarding the use of Design Compiler on large, super-high performance
designs. I am hoping your readers can rattle something off to point me
in the right direction.
Our company (ATI Research, formerly Chromatic Research) is building higher
and higher performance processor-like chips, and we need to continue to
improve our methodology to support very high performance designs in the
future. Do you have any pointers to resources (articles, mags, people, ...)
that might give some reasonably detailed descriptions of how other groups
doing very large, very high performance chips are using Synopsys and their
favorite P&R tool to achieve good results? Throwing a large chunk of RTL
that produces a 100k gate netlist doesn't work. Example questions: How far
can you go with DC to produce near-fastest possible implementations? At
what point do you give up on DC entirely and do logic optimization by hand?
What's an optimal cell library for speed?
- Mike Klein
ATI Research, Inc. Sunnyvale, CA
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