Editor's Note: I caught on CNN last night some personally sad news. As
you probably already know, I'm kinda into all sorts of odd aspects of
popular culture whether it be the latest Star Trek movie or old Lawrence
Welk polkas. That being said, I heard on CNN that Mark Gagnon, the
songwriter who wrote the children's party dance song "The Hokey Pokey",
had died of a heart attack at the age of 83. And the really weird
part of the story was the problem the morticians had with Gagnon's
funeral. Apparently, when they tried to put him in the coffin, they'd
put his left foot in; he'd put his left foot out; they'd put his left
foot in; and he'd shake it all about... :^)
OK, that was one very corny joke. I laughed when I heard it, and the
worst part about it was that I found myself unexpectedly humming
"The Hokey Pokey" to myself for the rest of the day after I heard it!
(I wonder how many of you won't be doing this, too, today! Enjoy!)
- John Cooley
the ESNUG guy
( ESNUG 306 Item 1 ) ---------------------------------------------- [12/3/98]
From: "Brent Hayhoe" <hayhoe@nortelnetworks.com>
Subject: Synopsys Support Fatigue & Missing Altera FLEX Designware Components
Hi John,
Does anyone else get tired of reporting bugs to Synopsys? This is my
bugs-with-Synopsys scenario:
1. Oh, no, not another one. How on earth do I get around this?
2. After much farting around, decide that doing 'xyz' circumvents the bug.
3. Hmmm. Better report this to Synopsys.
4. Dear Synopsys, doing 'abc' results in an error. 'xyz' is a work-around.
5. Dear Brent, Please send your dc_shell scripts and VHDL source so that
we can replicate the problem.
6. Tar and compress files and send them off.
Reasonable I suppose, only my dc_shell environment is fairly contorted in
its set up, as are some of my VHDL libraries. I just know what their next
reply is going to be.
7. Dear Brent, Can't get your set-up to work. Have knocked up a script
to simulate what you're doing. Can you tell me what to set the
following dc_shell variables to? ...And these VHDL generics? Oh and
where are these constants set?
8. Spend another hour typing an Email explaining where everything is, etc.
9. Dear Brent, Still can't get it to work. Can you have a look at this
script and see what I need to do?
10. I really don't feel like it you know. And I've got a work around
anyway.
Now, I'm not knocking the Synopsys support guys. I think they've got a
tough job to do. My problem is that once I report a bug, I can see this
huge workload looming on the horizon and as I then have to work for Synopsys
Support in a sub-contract role! It's kind of embarrassing telling my boss
that I haven't finished what I'm supposed to be doing because I've been
typing Emails trying to sort out this bug that we've got a solution to
anyway. (Maybe Synopsys could pay my rates instead of Nortel whilst we
sort the bug out? Yea, I know: Dream on!)
So - a workaround - report it in ESNUG. Then everyone knows about it!
Here we go, latest bug...
Problem:
Whilst elaborating a VHDL design, the autolink links in a DB file of a
previously synthesized sub-design and just one of the Designware
components in this sub-design disappears.
Environment:
The design is targeted to an Altera 10K100 FPGA. The sub-design links
perfectly on its own. (It has HDL grouped process designs and Designware
designs within its DB file.) The part that is vanishing is an Altera
Designware part FLEX_ADD_MOD_6. There are other Altera Designware parts
but they link in OK.
Work-around:
Turn off the autolink around the elaborate command thusly:
auto_link_disable = "TRUE"
elaborate DESIGN_NAME_v -architecture DESIGN_ARCH_v \
-library DESIGN_LIB_v \
-update
auto_link_disable = "FALSE"
link
Now in my design flow, I synthesize each hierarchy level and save just that
level in its own DB file. As I do each level, all preceding levels are auto
linked in. So having solved the problem at this level, when I compile at
the next level up the Designware part disappears again. Fortunately my
elaborate is in a separate include file within my scripts and so once I
modify that, it's done for all levels. (Structured dc_shell scripting!
Wow! It's paid off at last!)
Any one else come across this before?
Any one else feel tired?
zzzz
zzzz
zzzz
zzzz
- Brent Hayhoe
Nortel Networks Harlow, Essex, U.K.
( ESNUG 306 Item 2 ) ---------------------------------------------- [12/3/98]
Subject: ( ESNUG 301 #1 305 #8 ) The Rest Of My Chip Express Nightmare
> I was quite surprised to read the "Crappy Chip Express" email in the
> ESNUG 299. I think it's not right to publish this kind of message from
> an anonymous source. Accusing without taking responsibility is not
> what I would expect to be an objective of ESNUG.
>
> I don't believe there is one vendor out there who does not have at
> least one unhappy customer. So, by letting him voice his opinion you
> may cause a real damage to the company. Lets say the complainer is
> right (we all know the customer is "always" right...) still the vendor
> should have the opportunity to comment on these kind of strong
> accusations. I'm glad one of our customers took the initiative to
> respond.
>
> - Tsipi Landen
> Marketing Communications Director
> Chip Express Santa Clara, CA
From: [ "FedEx, They Ain't." ]
John, Anon, please!
This is a counterpost to Tsipi Landen's complaint about my original post.
I'm posting this anonynous since it represents an opinion from an engineer
who used Chip Express's fab and not *the company* I did the work for.
My opinions are my own, plus there's enough people out there who know
me and who I currently work for. Also, this is a forum for engineers
to express learnings & comments. If John was to regulate just "good-
natured" postings, I wouldn't want to read ESNUG since it would very
biased/censored and "content free".
Here's the rest of my Chip Express horror story, details & all.
Aside from bad documentation on the vector format (the docs say
print-on-change, but your TE's wanted sampled time slots), Chip Express
did an *average* job at providing us a solution for an ASIC. However, I
wouldn't say we had a successful tapeout.
In the Chip Express gate array technology, the number of gates is
meaningless, (hence, no truth in advertising) it's the utilization numbers
that makes the difference. Our design was well under the gate count of
the CX2001 total gates (100K gates @ 33MHz), but approximated 58%
total utilization which made it unroutable. Thus, we spun a month
of effort of learning that our design couldn't be routed on CX2001
and another month to resynth it to a beta CX3001 process. Our design
routed fine in the (beta) CX3001 process, but we were initially plagued
with Chip Express routing tool problems. Then someone at Chip Express
didn't provide documentation on the packaging -- the parts were proto
builds, so the epoxy wasn't cured. This turned one of two proto chips into
a curled potato chip in the IR oven at board assembly.
In the end, we recieved only *one* workable part (the other part which
passed the tester was destroyed in the epoxy/IR oven fiasco). The yield hit
was attributed to manufacturing/fab-related issues, but we never did get
final resolution on why. We waited over 2 months and Chip Express still
couldn't ship us any working chips. At that point, we passed the
opportunity to make use of many proto units, canned the project, and
dropped further activity.
Okay, we got dorked using a beta process, so maybe we got what we paid for.
However, when the Chip Express marketing & engineering types initially
came in to discuss our design and issues for the sale, they sold us on the
current cx2001 process and that they could get it to fit and fab in a
*short* period of time. If we factor in the time we spent doinking around
with the Chip Express-related problems, we could have gone to a
Toshiba/Hitatchi/VLSI/LSI ASIC house and had the *same* turn-around time.
In retrospect, the engineering team believed the sales team and maybe we
didn't do enough homework upfront on the technology to realize the limits
that we were pushing. I also wasn't impressed with Chip Express's PLL,
clock insertion delays, or the slow pads on CX3001, but unfortunately that's
what Chip Express's laser-programmable or 1-mask technology buys you.
With that said, I was impressed with Chip Express's *effort* to try and get
the contract done in a somewhat timely fashion and their efforts in
putting the design on a beta process in order to fill the contract. Other
departments within this company have had good success with Chip Express. I
personally would not be sure I'd use them again, but I would recommend
engineers do their homework up front on the technology.
- [ "FedEx, They Ain't." ]
( ESNUG 306 Item 3 ) ---------------------------------------------- [12/3/98]
From: eko@Aureal.com (Eugene Ko)
Subject: Bizarre, Mysterious 13% - 41% Area Increase With Aspec Libraries
John,
I'm using Aspec libraries, and Synopsys 1998.02 and 1998.08.
Even though I use no rams in my design, my design team shares a common setup
script, therefore a "ram.db" is added into everyone's (including my)
link_library and target_library.
Here's the problem: Although I don't have any rams in my design, the areas
increase about 15% to 40% if the Aspec RAMs are linked in!
My original design & environment was too big/complicated to send to the
Synopsys Support Center, so I replicated the problem using your simple,
public domain 8-bit counter from your "SNUG'95 Verilog Vs. VHDL Design
Contest". Attached are 3 scenarios that use that simple 8-bit counter and
Aspec libs.
First: No Aspec "ram.db" In Link_library Nor Target_library
link_library = {"sm222s.db"}
target_library = {"sm222s.db"}
read -f verilog counter8bit.v // a simple 8-bit counter
Total cell area: 430.00 // no ram.db in the link_library and
target_library
Second: Aspec "ram.db" That Contains Only One Specific Aspec RAM
link_library = {"sm222s.db", "ram.db"}
target_library = {"sm222s.db", "ram.db"}
read -f verilog counter8bit.v // same RTL, same constraints
Note: with each different specific Aspec ram in "ram.db", Synopsys puts
out different results! And my design DOES NOT use any RAMs!
Total cell area: 538.00 // one ram, cs1rwd128x1t16d1.lib, in ram.db
Total cell area: 492.00 // one ram, cs1rwd2048x16t16.lib, in ram.db
Total cell area: 488.00 // one ram, cs1rwd1280x8t16.lib, in ram.db
Total cell area: 554.00 // one ram, cs1rwd3840x21t16.lib, in ram.db
Total cell area: 549.00 // one ram, cs2rwd512x24t16.lib, in ram.db
Third: Aspec "ram.db" That Contains 1, 2, 3, 4 Specific Aspec RAMs In It
link_library = {"sm222s.db", "ram.db"}
target_library = {"sm222s.db", "ram.db"}
read -f verilog counter8bit.v // same RTL, same constraints
Total cell area: 492.00 // 1 ram in ram.db
Total cell area: 549.00 // 2 rams in ram.db
Total cell area: 595.00 // 3 rams in ram.db
Total cell area: 608.00 // 4 rams in ram.db
Again, remember, my design doesn't use any RAMs, yet my areas grow
if Aspec RAMs are in my link path.
I had submitted this bug to Synopsys two months ago. They re-produced the
problem but no workarounds for me so far. They talked to Aspec and looked
over their .lib source and report that it appears to be OK. When I tried
all three above scenarios using Cascade libraries, I didn't have any area
problems at all. (The main difference between Aspec libs and Cascade libs
is that Aspec uses table lookup timing model, Cascade however uses piecewise
linear model. I don't think this means anything, but it is a known
difference between the two libs.)
It's been two months. I can't wait any more. Did anyone run into the same
situation? Any solutions? Thanks.
- Eugene Ko
Aureal Semiconductor
( ESNUG 306 Item 4 ) ---------------------------------------------- [12/3/98]
From: [ Asterix, the Gaul ]
Subject: I'm Not Half As Starry-Eyed About Module Compiler As Synopsys Is !
Let's bounce the Module Compiler thread around again. I feel that Module
Compiler is worth talking about, I've been evaluating it and my experience
is not half as starry-eyed as the marketroids would have you believe.
Basically, it is a capable niche tool that fails totally to integrate with
Synopsys. I cannot see any medium-sized or non-specialist company making a
business case for it.
Reuse Wasn't Thought Out Well:
Module Compiler only considers reuse explicitly for structured expressions
using a MUX operator, as far as I can see. Module Compiler will not
spontaneously extract high-level structural information, such as the
similarity between an adder and a multiplier; this is disappointing.
I would have to manually restructure my design.
Restricted Input Format:
Module Compiler only considers combinational datapath expressions with
registers allowed only for pipelining. (For example, ordinary explicit
synchronous reset and load on registers is not possible!) Furthermore,
Module Compiler does not support any conditional constructs (other than
MUXing) -- so all IF and CASE statements would have to be totally
rewritten - not a good proposition.
Lack Of Integration With Design Compiler:
So where does this fit into the Design Compiler flow? The design engineer
would have to
a/ rigidly partition every register and conditional logic gate
out of their design into a separate module
b/ treat it as a blackbox inside Design Compiler
c/ characterise all loads and timing constraints to a script file
d/ haul the datapath into Module Compiler
e/ import the constraints (how?)
f/ optimise
g/ write Verilog output
h/ haul the datapath back into Design Compiler
i/ and treat it as a blackbox again for the purposes of optimization.
Would somebody like to estimate the complexity of a design required for
which the extra effort would break even compared to using the fastest DW
components and then fine-tuning Design Compiler?
I am not aware of the standard commercial pricing but I would strongly
expect that one seat of DesignWare would be far more generally useful
than Module Compiler.
On the positive side, the Module Compiler optimisation engine, for what
it is, is very promising. Synthetic cells are the way forward, to hide
spurious or marginal wireload-inspired 'optimizations' from the compiler,
while achieving genuine structural optimisations, such as an inverting
carry-chain, FAS cells, and various flavours of FFs.
But, can somebody tell me what Synopsys has been doing with it in the
two-and-a-half years since they bought SiArc? Tailoring it to CBA?
Disclaimer: please do not print unless I'm an utterly anonymous user of
Module Compiler. I don't want to be shot as a messanger by Synopsys.
A pseudonym might be Asterix, the Gaul.
- [ Asterix, the Gaul ]
( ESNUG 306 Item 5 ) ---------------------------------------------- [12/3/98]
Subject: ( ESNUG 305 #3 ) Test-Smart Avoids TC; Helps Mentor's DFT Advisor
> Synopsys has the ability to do a "Test-Smart" compile. The command to
> configure this is:
>
> set_scan_configuration -style multiplexed_flip_flop
>
> Valid commands are "multiplexed_flip_flop", "clocked_scan", "lssd",
> "aux_clock_lssd", and "combinational", but nobody ever uses any of them
> but "multiplexed_flip_flop". The neat thing about this command it that it
> DOESN'T grab the "Test-Compiler" license. So you can use it to feed the
> Mentor Graphics DFT Advisor (which is what most of us actually use).
>
> - [ Kenny from South Park ]
From: William Liao <wliao@vadem.com>
Hi, John,
I guess where I work is an exception. We use Test Compiler to create LSSD
scan chains and test vectors. I've heard that a number of other major
design centers like IBM and SUN Microsystems also use LSSD. I've written
an internal paper on the subject, and submitted an abstract/outline
to SNUG Tech Committee. If I am lucky, I'll present the paper in SNUG99.
- William H. Liao
Vadem
PS: Have you seen Clio? It's a neat WindowsCE subnotebook with amazing
battery life! Yea, this is a shameless plug for a Vadem product. But
I thought I'd try anyway seeing as to how often I write in ESNUG! :)
( ESNUG 306 Item 6 ) ---------------------------------------------- [12/3/98]
Subject: ( ESNUG 304 #3 305 #12 ) Find 3 Unloaded Nets Out Of 300,000 Nets ?
> I am looking for a command, or script, to report the nets that have NOT
> been loaded by a set_load command. This is because I want to determine if
> there is any net that escaped the set_load command, and hence the timing
> report may be erroneous.
>
> - Andi Carmon
> Orckit Communications Ltd. Tel Aviv, Israel
From: chris.bohm@analog.com ( Chris Bohm )
Hello John,
The following UNIX shell script can examine a report_net report file and
will filter out all nets which have no annotated capacitances:
touch annotated_nets.report
/usr/bin/rm annotated_nets.report
touch annotated_nets.report
touch not_annotated_nets.report
/usr/bin/rm not_annotated_nets.report
touch not_annotated_nets.report
nawk '
BEGIN{
if (FILENAME == "-")
print "ERROR: specify input file (report containing report_net section)."
else {
print "examining report file: " FILENAME
approaching_report_net_section = 0
in_report_net_section = 0
annotated_count = 0
not_annotated_count = 0
while ((getline < FILENAME) >0)
{
if (next_line_is_in_report_net_section == 1)
{
if ($1 == "----------------------------------------------------")
{
approaching_report_net_section = 0
next_line_is_in_report_net_section = 0
print "... found end of report_net section"
}
}
if (next_line_is_in_report_net_section == 1)
{
if ($7 == "c" || $7 == "c,")
{
print $1, $4 >> "annotated_nets.report"
annotated_count = annotated_count + 1
}
if ($7 != "c" && $7 != "c,")
{
print $1, $4 >> "not_annotated_nets.report"
not_annotated_count = not_annotated_count + 1
print "not annotated " $0
}
}
if ($3 == "annotated" && $4 == "capacitance")
{
approaching_report_net_section =1
}
if (approaching_report_net_section == 1)
{
if ($1 == "----------------------------------------------------")
{
approaching_report_net_section = 0
next_line_is_in_report_net_section = 1
print "... found start of report_net section"
print "... examining"
}
}
}
print " "
print "Summary:"
print "========"
print "Annotated nets: "annotated_count
print "Not annotated nets:"not_annotated_count
print "for more information see output files"
print "not_annotated_nets.report & annotated_nets.report"
}
}' $*
echo " "
echo "... finished."
To use it, do the following:
1) In design compiler do a
report_net -nosplit -transition_times >> report_file
2) run the UNIX script (giving it the "report_file" as an input parameter)
The script will walk through the report file and examine each line. Please
consider the following excerpt from a report_net:
> Attributes:
> c - annotated capacitance
> d - dont_touch
> p - includes pin load
>
> Net Fanout Fanin Load Resistance Pins Attributes
> --------------------------------------------------------------------------
> NET__65 1 1 0.04 0.00 2 c, d, p
If there is an attribute 'c' then this means that a cap value has been
annotated.
Please be aware of the fact that I use the script in a slightly different
way -- you may have to make some minor modifications. It's a good idea to
try it on a small test case. And, of course, I can't accept any legal
responsibility for misinformation reported by this script, use at your
own risk, objects in mirror are larger than they appear, etc., etc., etc.
- Chris Bohm
Analog Devices B.V. Limerick, Ireland
( ESNUG 306 Item 7 ) ---------------------------------------------- [12/3/98]
Subject: (ESNUG 305 #6) DC Won't Buffer Module Outputs W/ Bottom-Up Approach
> We are using a bottom up synthesis approach for a chip that we are doing
> with LSI. On our critical paths dc is leaving ***A drive parts on the
> outputs when all the cells in the paths up to the output have C and D
> drive. We are using
>
> set_load load_of (lcbg10pv/BUFA/A) * 5.0 all_outputs();
>
> which might be a little weak for nets that are enclosed by a much larger
> wireload model, BUT even at the lowest compile level the last
> incremental delay is the largest in the path because dc won't upgrade
> from an A drive cell at the output! And these are paths that don't meet
> their constraints at the lowest levels! Why won't dc increase the drive
> strength of our output cells?
>
> - Greg Brookshire
> Peracom Cary, NC
From: Don Devine <devine@Cadence.COM>
John,
I had a similar problem to this in the past. In my case I had clock which
drove some flip flops AND some combo logic, at a lower level, and after a
series of gates became the clock for another flip flop (ugly I know).
When I did a compile at the top level I had DRC errors. Obviously I wanted
to remove any anomalies, so I performed another compile but it was to of no
avail.
Anyway, I found the problem arose in the COMBO path which was driven by
the clock at top level. This occured because I had placed a
'set_dont_touch_network' on the clock signal and this prevented DC from
changing the cells 'on this combo clock network' from being changed. I was
using 1997.08 at the time, so as I'm not an expert with the latest versions,
I don't know if this can be avoided.
The workaround I had to do was to break the signal path to the sub block
and thus with the different clcock name 'combo_clock' and not defined as
a clock, the 'combo_clock & set_dont_touch_network problem' was no more.
- Don Devine
Accent S.r.l Vimercate, ITALY
( ESNUG 306 Item 8 ) ---------------------------------------------- [12/3/98]
Sunject: ( ESNUG 305 #13 ) What Other Tools To Estimate Power Consumption ?
> Does anybody know of commercial tools that do power estimation for VLSI
> circuits ? I know of PowerMill. Anything else available out there ?
>
> - Bruno Melli
> Hewlett-Packard Fort Collins, CO
From: William Liao <wliao@vadem.com>
John,
Sente sells WattWatcher. It's been a while since I evaluated it, so I have
no current opinion on the tool. Their web address is www.powereda.com.
- William H. Liao
Vadem
---- ---- ---- ---- ---- ---- ----
From: sgolson@trilobyte.com (Steve Golson)
Hi, John,
Sente has a product called Watt Watcher which can do *pre-synthesis* power
estimation (from Verilog and VHDL) as well as gate-level power estimation.
Lots more info at http://www.senteinc.com
- Steve Golson
Trilobyte Systems
---- ---- ---- ---- ---- ---- ----
From: "David Brantley" <dmb@dalsemi.com>
John,
You might want to check into WattWatcher from Sente. It does power estimates
at the RTL level. It requires a well characterized cell library. When we
evaluated the product, we got answers within 10% of our powermill results.
We have purchased a copy but have not yet released it into production, a
bandwidth issue in support area.
- David Brantley
Dallas Semiconductor Dallas, TX
---- ---- ---- ---- ---- ---- ----
From: Eric Filseth <efilseth@senteinc.com>
Sente (www.senteinc.com) develops tools which do accurate VLSI power
estimation and analysis, at both RTL and gate levels, both module-level
and full chip, both average and peak power.
Simplex (www.simplex.com) also provides transistor-level power analysis
tools in the same class as PowerMill.
- Eric Filseth
Sente
---- ---- ---- ---- ---- ---- ----
From: "Edward L. Hepler" <elh@ece.vill.edu>
Mentor has a tool that was originally part of SCS (Silicon Compiler Systems),
a company that they purchased a few years ago... A version of their Lsim
simulator does power calculations... I have not used Lsim for power,
but have been a very pleased user of it for switch level simulation...
- Ed Hepler
VLSI Concepts, Inc.
---- ---- ---- ---- ---- ---- ----
From: cmurphy@sugar.mti.sgi.com (Colin Murphy)
Estimation? Not sure what you are looking for but we have gotten very good
results from simplex from extracted finished layout.
- Colin Murphy
SGI
( ESNUG 306 Item 9 ) ---------------------------------------------- [12/3/98]
Subject: Why Does Synopsys Use The "Find" Command Everywhere In Their Docs?
> This question stems more from curiosity than any design issue. I have
> noticed that in the majority of tutorial/sample scripts for Synopsys'
> Design Compiler, the "find" command is used to locate signals by their
> full name, for input to other commands. For example:
>
> create_clock -period 50 find (port, clock)
>
> Can anyone provide me with a reason as to why the first construct would
> be used, other than for the purpose of displaying your understanding of
> the find command?
>
> - Jamie Travers
> Ericsson Mobile Communications AB
From: Jan Decaluwe <jand@easics.be>
Because dc_shell maintains multiple namespaces for different types of
objects, such as pins, ports, clocks, nets etc., and many commands can work
with various types.
With 'find' you specify in which namespace you are looking, or, to put it
differently, which type of object you want. It's good practice to use
it, because the "reasonable default" may not always be what you want.
E.g. note the difference between:
report_timing -from clockpin
report_timing -from find(clock, clockpin)
Regards,
- Jan Decaluwe
Easics Leuven, BELGIUM
( ESNUG 306 Item 10 ) --------------------------------------------- [12/3/98]
From: "Michael Patti" <mpatti@sarnoff.com>
Subject: Summit Design's "Visual HDL" vs. Escalade's "DesignBook"
John,
We have an internal debate going on between buying Summit Design's
Visual HDL vs. Escalade's DesignBook. What we are looking for is a
productivity improvement over hand writing VHDL and Verilog code. We
also would like a tool to help us reuse and modify legacy code.
Do you have any opinions on these tools?
- Michael Patti
Sarnoff Corporation Princeton, NJ
( ESNUG 306 Item 11 ) --------------------------------------------- [12/3/98]
Subject: ( ESNUG 305 #15 ) We Got Results With Power Compiler/DesignPower
> I'm trying to use Power Compiler/DesignPower to reduce power in a design.
> All my gated-clocks are done manually, so I'm not using the "elaborate
> design -gate_clock" approach. When I try optimizing the design for power,
> it only gives a 1-2% decrease in power. From the documentation, I expected
> a 10-20% reduction in power... In one case, the power actually went up
> 1% after the final compile! I can give my test case or more info if it's
> needed. Thanks for any help.
>
> - Will Lentz
> Trimble
From: Zia Khan <zia.khan@intel.com>
John:
I have used Power Compiler and saw substantial power reduction. The results
of this work should be published in SNUG-98 this year. Briefly, one could
get 15% power reduction but at substantial area cost. By manipulating the
cost function one could limit area penalty for a lower power saving. For my
test cases, I was able to get 10% power reduction for 2% area penalty.
I also understand that Power Compiler now has a new option:
set_cost_priority -firm_area_limit
that could give user better control. I have not tried it yet so I can't
speak from experience.
- Zia Khan
Graphics Components Division
Intel Corp
---- ---- ---- ---- ---- ---- ----
From: Hesham El-Adly <hesham@cae.ca>
Hi, John,
We've been getting fairly sizable power reductions using Power Compiler for
many of the blocks we've passed through the flow. Analyzing the results of
power optimization, I've noticed that much of the savings in power is due to
downsizing of drivers with relatively minor restructuring changes. Although
our ASICs are running at very high frequencies, we're targeting an advanced
ASIC technology with a rich library that leaves us room to "maneuver" to
optimize power.
We have also not seen any significant area increase during power optimization
but again this is mostly due to the richness of our ASIC library. (I'll
assume that switching power dominates the power in Will's design.) Success
with Power Compiler is linked to:
1) successful annotation of switching activity to the design
2) ASIC libraries which include multiple drive strengths and complex
combinational cells
3) timing not limiting power optimization
Switching Activity
------------------
For production work, we only extract switching activity from gate level
netlists. We are currently experimenting with applying switching activity
of only primary inputs, captured from RTL simulation, onto the gate level
netlist and using Power Compiler to propage the switching through the
design but we're unsure whether this will be successful and do not advise
it (at this time).
As the quality of power analysis is directly related to the success of
back-annotation of switching activity to the db, a procedure for checking
success of back-annotation should be a standard part of the methodology.
Steps to check coverage quality include;
-- Back-annotate switching activity
dc_shell> include designName_toggle.scr -quiet > designName_toggle.log
-- Report power per net to a log file
dc_shell> report_power -flat -net -nosplit > designName_toggle.rpt
-- Check the value of the switching activity attribute applied to each net
(write a little Perl script)
This is not an elegant solution - I'm hoping that Synopsys add a feature to
check coverage quality without forcing users to perform a complete power
analysis cycle.
ASIC Libraries
--------------
Libraries with multiple drive strengths, especially with more granularity in
drive strengths at the low end, are needed for large power gains. DC tends
to jump to the easy solution of using high drive buffers fairly early during
timing optimization. Power Compiler does a good job of resizing these
buffers during incremental compile with a power constraint.
Complex combinational cells are also important because Power Compiler tends
to enclose high switching nets within the complex cells resulting in a
reduction of capacitances of the enclosed nets.
Simply put, the richer the library, the better the results for timing and
power.
Timing Quality
--------------
Timing constraints take precedence over power constraints (and power
constraints take precendence over area constraints). If you have trouble
meeting timing with your current library, Power Compiler may not be able to
reduce power without structuring the gate level netlist differently.
You may be forced to apply switching activity of only the primary inputs of
the design to the elaborated db and use a power constraint during initial
compile to improve power. However, this still may not work if your timing
is very tight and your pushing the limits of your ASIC library.
It's not obvious to draw a conclusion why you haven't seen reduction in
power with Power Compiler but check whether the points I outlined make any
sense for your design and environment to start.
- Hesham El-Adly
CAE Electronics Ltd.
( ESNUG 306 Item 12 ) --------------------------------------------- [12/3/98]
Subject: (ESNUG 305 #4) Use Cadence, Avant!, But NOT DC To Build Clock Trees
> Generally people don't build a clock tree with Synopsys. This is done
> better on the layout synthesis portion of design. You can back annotate
> your design and look for problems/optimizations in Synopsys though.
>
> Avant! has a program called Solar that I hear does well with clock tree
> synthesis.
>
> - Matt Guthaus
> U Michigan
From: paul.sheridan@analog.com (Paul Sheridan)
Hi John,
Regarding using Synopsys for Clock Tree synthesis (ESNUG 305 Item 4), you
might refer readers back to ESNUG 219 Item 1:
> ( ESNUG 219 Item 1 ) ---------------------------------------- [5/95]
>
> [ It's a Red Letter Day, Comrades!: This is the first ESNUG contribution
> coming from the other side of the old Berlin Wall! Cool! - John ]
>
> From: OIA@ashtech.msk.su (Orlovsky Igor)
> ........
Orlovsky provided a Synopsys+UNIX-based script which he wrote to generate a
"multi-level balanced tree for any named net in the design". He shows an
example of it working for a clock.
Keep up the great work!
- Paul Sheridan
Analog Devices
( ESNUG 306 Item 13 ) --------------------------------------------- [12/3/98]
From: Andy Pagones-ACIC22 <Andy_Pagones-ACIC22@email.mot.com>
Subject: How Do I Put Routing Layer Preferences Per Pin In DC Libs?
Dear John,
I'm a new Synopsys user. Our cell library has lots of ways to save metal2
tracks by routing metal1 between adjacent cells.
We'd like Synopsys to choose pin connections based on routability. That
is, if a cell has a set of boolean equivalent pins but only one can connect
with metal1, then Synopsys should connect to *that* pin if its target
connection pin is also metal1-enabled.
Is there a way to specify this in the library??? I'd rather not try to
tweak delay numbers to make one pin more "attractive" than the others.
Perhaps there is another clever workaround.
- Andy Pagones
Motorola Chicago Corporate Research Laboratories Chicago, IL
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