Editor's Note: Oh, well, it's groveling & begging forgiveness time for
me right now. Do you remember that old Disney movie "Fantasia" where
Mickey Mouse played the Sorcerer's Apprentice? Mickey got himself into
a complicated situation involving walking brooms carrying buckets of
water and some great classical music. Mickey thought he could solve his
problem by taking an axe and cutting the walking brooms in half. But it
only made things worst for Mickey, because cutting up those brooms only
created MORE walking brooms carrying MORE buckets of water.
Right now I am that cartoon mouse in the Sorcerer's Apprentice role.
Some time back, Paul Zimmer sent me a really complicated, multi-part post
for ESNUG. And usually when I get multi-part posts, I break them up
into separate items within ESNUG. Why? Because it's easier for users
to discuss "I Love/Hate Dc_perl" separately from "Testing RAMs Via Scan
Chains". The problem was that the complicated, multi-part post that
Paul Zimmer sent me wasn't just complicated -- it was the Mother Of All
Complicated Posts. Like Mickey, I had unwittingly cut it in half putting
each part in separate files and forgot about it. When it came publishing
time, I read the half that was going to be published in ESNUG 304 and it
had many references to a "sid/sod syntax". I was stumped. Never heard
of that one before. I e-mailed Paul. No reply. I phoned Paul. No reply.
Thinking of myself as a clever boy, I tried to figire out what "sid/sod"
meant based on Paul's recent post about ied. Aha! Paul talked about
"stdin/stdout" in his ied post! "sid/sod" MUST MEAN "stdin/stdout" !!!
I congradulated myself on how clever I was, edited Paul's post to reflect
what "sid/sod" REALLY was & gleefully published it.
And BOY WAS I WRONG! Turns out "sid/sod" is "standard_input_delay /
standard_output_delay". (Ooops. Sorry....)
- John Cooley
the ESNUG guy
( ESNUG 305 Item 1 ) --------------------------------------------- [11/98]
Subject: ( ESNUG 304 #11 ) Paul Zimmer's Mother-Of-All Headaches ESNUG Post
From: "Paul.Zimmer" <paul.zimmer@cerent.com>
John,
You munged my posting! Compare the attached original to what you just
sent out in esnug 304. You substituted stdin/stdout for set_input_delay/
set_output_delay! You also removed some important introductory info.
Could you please do me a favor and just shoot the original posting out
ASAP? I'm getting emails from confused readers (who think I'm even more
confused than I am).
I know the posting is long and full of gorey details, but that's sometimes
what techinical discussions are like. Feel free to preface it with a
warning that it may not be appropriate for all audiences. It's a tough
problem!
Thanks,
- Paul Zimmer
Cerent
P.S. Enclosed is the post:
Hey John,
I've got a couple of related questions to throw out to the ESNUG community.
This is pretty tricky. I suspect there are less than 10 engineers worldwide
who could understand and/or answer these questions.
Question 1:
-----------
Like a lot of people, I use default scripts to compile most blocks, and
I don't mess with these defaults unless I have to. This implies setting
appropriate constraints WITHOUT knowing the details of the logic inside,
specifically without knowing what sort of paths exist (seq vs comb).
So, imagine I've got a module that has inputs that go to flops, outputs
that come from flops, and outputs that come from both inputs and
flops (commonly known as a Mealy state machine).
So, I want to budget this thing such that the input-to-clock paths get
0.85 clock period, the clock-to_output paths get 0.15 clock periods,
and the combinational (input-to-output) paths get 0.50 clock periods.
This was easy with the old set_arrival, set_max_delay syntax:
all_inputs_no_clocks = all_inputs() - find(port,clkname)
set_arrival 0.15 * clk_per all_inputs_no_clocks
set_max_delay 0.15 * clk_per all_outputs()
set_max_delay clk_per * ( 0.15 + 0.50 ) \
-from all_inputs_no_clocks -to all_outputs()
Which is why I've kept using the old syntax all this time.
Now, because of question 2 below, I have to move to the "new" syntax
of set_input_delay and set_output_delay.
The input-to-clock and clock-to_output paths are easy enough:
all_inputs_no_clocks = all_inputs() - find(port,clkname)
set_input_delay -clock clkname 0.15 * clk_per all_inputs_no_clocks
set_output_delay -clock clkname 0.85 * clk_per all_outputs()
Unfortunately, this doesn't work for the input-to-output paths.
We've now told dc that all the inputs and outputs are related to the clock,
and that the combined delays take an entire clock cycle. So, there's
nothing left for the comb budget.
Basically, the sid/sod syntax ASSUMES that a clock cycles is consumed in
the middle. This isn't true for combinational paths.
The only way that I've found to get around this is to declare the
combinational paths to be multicycle:
set_multicycle_path 2.0 -setup -from all_inputs_no_clocks \
-to all_outputs()
set_multicycle_path 1.0 -hold -from all_inputs_no_clocks \
-to all_outputs()
(The second line is needed to make the hold calculation work correctly.)
Now we have the clock-related constraints out of the way, and we can put
combinational constraints on. You would think that this could be done by
using set_max_delay. Unfortunately, I haven't been able to get this to
work. Instead, I have to create a virtual clock and put output (or input)
delay on it.
create_clock -name combclk -period 10.0 -waveform {0, 5.0}
set_input_delay -clock combclk 0.0 all_ins_no_clks -add_delay
set_output_delay -clock combclk 17.0 all_outputs() -add_delay
All those single-path timing exceptions sound like a potentially serious
performance hit (although I must admit that on 9802 I haven't actually
seen much of a problem). Besides, this is MESSY.
Has anyone found a better way?
Question 2:
-----------
[ Editor's Note: "sid/sod" == "set_input_delay/set_output_delay" ! - John ]
The reason I have to go to the sid/sod syntax (aside from the fact that
set_arrival has disappeared from the man pages :-) )is because I am now
dealing with modules that have multiple clocks all mixed in with logic to
be compiled (don't ask).
Now, this is what sid/sod was invented for, so this should be easy, right?
Well, wrong. The sid/sod approach assumes that the constraint setter
KNOWNS what inputs and outputs are related to what clocks. That's fine
at the top of the chip, where I've been using sid/sod for years so that
I can break bidi loops, but my lower-level generic scripts DON'T know that,
and don't WANT to know that.
If you do the sid/sod for each clock and clk_per in a foreach loop,
you'll get silly things like a path from the slow clock, plus the
input delay of the slow clock, ending at a flop clocked by the
fast clock.
Well, I guess this isn't really silly from dc's point of view. You've
effectively told dc that there is a source for each input from each
clock domain with a certain delay, and a sync for each output in
each clock domain with a certain delay, and it doesn't know any better.
But, this isn't what you really WANT. What you want is for the input
and output delays for a clock to only be applied to paths that end/start on
that clock. So, an input that goes to flops on both the fast and slow
clocks (for example) should have the slow clock's input delay budget on
the path going to the slow clock flop, and the fast clock's input
delay budget on the path going to the fast clock flop. Likewise for
outputs.
How do you do this? I'm still trying it out, but the only way I've found
so far is to do all the same stuff above (Question 1), and then set
false paths across all the clock boundaries.
foreach(_clock,all_clocks()) {
foreach(_other_clock,all_clocks() - {_clock}) {
set_false_path -from _clock -to _other_clock
}
}
That's a shame, since I've already gone to a lot of trouble to define the
clocks using harmonics of the fastest clock, then shrinking them to the
target period using minus clock skew. So, I shouldn't have to disable
all the cross-clock paths.
Does anybody know of a better way to do this?
- Paul Zimmer
Cerent Corporation
( ESNUG 305 Item 2 ) --------------------------------------------- [11/98]
Subject: (ESNUG 303 #2 304 #9) Variable For Annoying Buried Translate_off's
> If you check the time stamps on the IEEE std_logic_1164, Vital_Timing and
> VITAL_Primitives packages, you'll see that the files are really out of
> date (.sim and .syn). This is a software release problem that Synopsys
> has finally admitted to in the 1998.02 and 1998.08 releases. They have
> posted a fix for this on SolvNet, but I wouldn't recommend it. It should
> be fixed in the next VSS release (?April '99?), not in the DC release
> scheduled for February '99.
>
> - Wayne Miller
> Symbol Technologies, Inc.
From: [ Synopsys Pulled The Olde Switcheroo! ]
The Vital source files in the IEEE/src library are not the ones used to
generate the .sim files in the IEEE/lib directory. Synopsys R&D has
optimized the Vital library packages for simulation, and that's what
they use to generate the .sim files on the CD. (They also redefine
some of the Vital procedures.)
I followed the SolvNet suggestion to re-analyze Vital_Timing and
Vital_Primitives, and then I couldn't analyze a Vital library from
my semiconductor company without errors. I traced this down to the
difference in the Vital files. I got the correct source files from the
Synopsys hotline and was OK. This should all be fixed in about 5
months or so. (Synopsys R&D knew what they were doing, but the AE I was
working with was quite surprised at the switcheroo.)
No name, no company please.
- [ Synopsys Pulled The Olde Switcheroo! ]
( ESNUG 305 Item 3 ) --------------------------------------------- [11/98]
From: [ Kenny from South Park ]
Subject: Test-Smart -- Avoids Test Compiler & Helps W/ Mentor's DFT Advisor
John, company politics says I stay anon.
Synopsys has the ability to do a "Test-Smart" compile. The command to
configure this is:
set_scan_configuration -style multiplexed_flip_flop
Valid commands for this are "multiplexed_flip_flop", "clocked_scan", "lssd",
"aux_clock_lssd", and "combinational", but nobody ever uses any of them but
"multiplexed_flip_flop". The neat thing about this command it that it
DOESN'T grab the "Test-Compiler" license. So you can use it to feed the
Mentor Graphics DFT Advisor (which is what most of us actually use).
What does this REALLY do? According to Synopsys:
"Test-Smart Compile prevents the use of functional cells with no scan
equivalents during mapping. This is accomplished by restricting the
set of cells that can be used by optimization."
This works by reading an attribute in your library which list the cells with
scan attributes. Note that some scan cells have scan attributes.
Thus a "dont_use" on scan cells and pawing through the library for cells the
Mentor's DFT Advisor can deal with is no longer necessary.
- [ Kenny from South Park ]
( ESNUG 305 Item 4 ) --------------------------------------------- [11/98]
Subject: Use Cadence Or Avant!, But NOT Synopsys To Build Clock Trees
> I would like to build a clock tree into my design with Synopsys. Can
> someone tell me the commands to build it?
>
> - Manu
> Universita' degli Studi di Roma "Tor Vergata" Italy
From: Matt Guthaus <mguthaus@holabird.engin.umich.edu>
Generally people don't build a clock tree with Synopsys. This is done
better on the layout synthesis portion of design. You can back annotate
your design and look for problems/optimizations in Synopsys though.
Avant! has a program called Solar that I hear does well with clock tree
synthesis.
- Matt Guthaus
U Michigan
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
I just wanted to agree with you, Matt, generally I hand design all my clock
trees because it's such a tricky thing and then use Synopsys to analyze it
afterwards relative to my design. The only gotcha is that in many cases you
only have front annotated numbers and skew can be difficult to estimate.
Usually, you can't use the individual buffer/inverter skews you find in the
data books because they're way too conservative. To get around this you
either have to do your own P&R or go back to your foundry and ask them to
analyze your hand designed clock tree for skew.
- John Cooley
the ESNUG guy
---- ---- ---- ---- ---- ---- ----
From: Massimo Zucchini <zucchini@cadence.com>
John,
I also agree with you... Generally I design my clock-trees following these
steps:
a/ Insert a "place-holder" library macro foreach clock-tree at RTL level.
Investigate latency and skew issues foreach clock-tree.
b/ Write down an agreement with silicon vendor about clock-trees issues.
Depending on technology and layout-guy skill, today we can work with
very performant clock-trees...(assuming no latency issues, we can
deliver a clock-tree with a few ps. of skew (100,200 ps) and a latency
of 1-2 ps Typ. case for hundreds of fanout flops)
c/ From the RTL point of view, you can work with place-holder, paying
attention for buffer-insertion during synthesis ( clock-trees branches
must be clean) and using Synopsys "uncertainty" option if you like.
Again, working with "place-holder" lets you backannotate clock latency
directly on it rather that re-built a new netlist with all clock-trees
buffers inserted...
- Massimo Zucchini
Accent Vimercate (MI) Italy / Cadence
---- ---- ---- ---- ---- ---- ----
From: iannuccelli@eln.uniroma2.it ( Manu )
I have try to build the automatic clock tree with CTS of Cadence (Cell
Ensemble) but this software have a bug. So I would like to build the clock
tree in Synopsys before.
- Manu
Universita' degli Studi di Roma "Tor Vergata" Italy
( ESNUG 305 Item 5 ) --------------------------------------------- [11/98]
Subject: Synthesis with Altera RAM Instances
> I have used Altera's "genmem" to create a RAM. The output files were:
>
> 1. syn_ram_8x14_irou.v which contains the Verilog simulation model and
> the RAM instantiation for Synopsys synthesis.
>
> 2. syn_ram_8x14_irou.lib which is to be (somehow) inserted to the
> flex10k-2.db library.
>
> I tried doing a read_lib syn_ram_8x14_irou.lib unsuccesfully. Apparently
> it needs a library header to be able to load. I could not find an app-note
> for this in the Altera web site. Thanks in advance for your help...
>
> - SFCFM Volunteer
From: doron nisenbaum <doron@chipx.co.il>
Hi. I have no experience with Altera rams, but from question I can guess
that the command you should try in order to read the ram is:
update_lib <altera library name> syn_ram_8x14_irou.lib
You can find out the library name using 'list -libraries' command.
- Doron Nisenbaum
Chip Express (Israel) LTD. Haifa, Israel
---- ---- ---- ---- ---- ---- ----
From: "SFCFM Volunteer" <stahr@andix.com>
Thank you! This "update_lib" command is exactly what I needed. Later I
found it in an Altera app note.
- SFCFM Volunteer
( ESNUG 305 Item 6 ) --------------------------------------------- [11/98]
From: Greg Brookshire <gbrookshire@peracom.com>
Subject: Synopsys Not Buffering Outputs Of Modules In Bottom-Up Approach
John,
We are using a bottom up synthesis approach for a chip that we are doing
with LSI. On our critical paths dc is leaving ***A drive parts on the
outputs when all the cells in the paths up to the output have C and D drive.
We are using
set_load load_of (lcbg10pv/BUFA/A) * 5.0 all_outputs();
which might be a little weak for nets that are enclosed by a much larger
wireload model, BUT even at the lowest compile level the last
incremental delay is the largest in the path because dc won't upgrade
from an A drive cell at the output! And these are paths that don't meet
their constraints at the lowest levels! Why won't dc increase the drive
strength of our output cells?
- Greg Brookshire
Peracom Cary, NC
( ESNUG 305 Item 7 ) --------------------------------------------- [11/98]
Subject: ( ESNUG 303 #5 ) The Never-ending EDA-Should-Support-Linux Debate
> During the time Wellspring supported a Linux version of VeriWell, we had
> lots of downloads of the free version, but very few sales (which, I
> suppose, could mean something else...). So, the sales of the Windows
> version was supporting the Linux support. We could not maintain this
> drain. We had problems keeping up with the kernel, as well. So, as
> altruistic as we would like to be, we could not continue to sink resources
> into something that, albiet popular, was not generating revenue.
>
> Other companies have attempted Linux versions of their products and have
> given up. As Richard Goering pointed out, maybe there are lots of
> individual engineers who use Linux, but the CAD buyers aren't interested.
> It is a lot of effort to support another OS. And, the critical mass of
> products have to be there (simulators, synthesis, etc.). And, for a short
> time, there almost was a critical mass at the lower end (Exemplar,
> Wellspring, Fintronic, etc.). But, this is a chicken-and-egg problem,
> isn't it?
>
> So, here is what I did: I punted on Linux.
>
> - Elliot Mednick
> Wellspring Solutions, Inc. Salem, NH
From: lee@alantro.com (Lee Bradshaw)
Hi John,
It's taken me a few weeks to get around to writing this note, but I'm a
happy EDA linux user. I've been using linux at home for several years
now. Initially I was just using it as an X terminal to access the unix
systems at work. I tried veriwell a couple years ago, but there was no
waveform viewer and I dropped it like a hot potato. So I'm one of those
who downloaded the free version, emailed Elliot and then didn't purchase
anything.
Lately things have been changing. In March I changed jobs and decided to
try to use linux as my primary development machine. I evaluated speedsim
and finsim with some code that had already been developed at Alantro.
Speedsim seemed to be picky about what it would handle, and I didn't
spend much time trying to get it to handle the old design. Finsim worked
perfectly after adding libext=.v to all the `uselib statements. I've
been very happy with finsim. It sounds like polaris will soon be
available as well if people want a third choice (I hope I didn't leave
anyone out.)
Undertow is available for linux and I believe a couple of veritools'
competitors have waveform viewers available for linux or are working on
them.
We're using linux and NT machines on the desktop and linux and hp-ux
servers in the machine room. The linux machines seem to handle
displaying X apps better than NT, and they run our matlab jobs faster
than NT. Linux also handles our DHCP, DNS, email, and IP masquerading.
I seem to recall a marketing guy from exemplar saying that customers
evaluated and liked the linux version of galileo, but ended up buying
it for other platfroms because there wasn't a complete set of software
available for linux. The synthesis tool was probably the wrong one to
port first. The vendors tell me that engineers want to use linux at home
for simulations or checking waveforms. I think companies are more likely
to pay for these tools than they were for a synthesis tool without any
supporting software.
Now for a synopsys/linux question. The synopsys man pages seem to be in
ditroff format. Does anyone know how to convert these files to plain
text on linux? xditview displays the pages graphically, but I'd rather
use less (as the $PAGER) so I can search the pages. I've used the alias
below on solaris and hp-ux (both in bash).
alias synman="MANPATH=$SYNOPSYS/doc/syn/man man"
Unfortunately the linux man program I'm using doesn't convert ditroff to
text the way solaris and hp-ux do. Any suggestions?
- Lee Bradshaw
Alantro Communications
( ESNUG 305 Item 8 ) --------------------------------------------- [11/98]
Subject: ( ESNUG 299 #2 300 #1 301 #1 ) Chip Express Documentation Cost Us
> I was quite surprised to read the "Crappy Chip Express" email in the
> ESNUG 299. I think it's not right to publish this kind of message from
> an anonymous source. Accusing without taking responsibility is not
> what I would expect to be an objective of ESNUG.
>
> I don't believe there is one vendor out there who does not have at
> least one unhappy customer. So, by letting him voice his opinion you
> may cause a real damage to the company. Lets say the complainer is
> right (we all know the customer is "always" right...) still the vendor
> should have the opportunity to comment on these kind of strong
> accusations. I'm glad one of our customers took the initiative to
> respond.
>
> - Tsipi Landen
> Marketing Communications Director
> Chip Express Santa Clara, CA
From: danlutes@crystal.cirrus.com (Daniel Lutes)
John,
I can only say it is VERY RIGHT to publish the criticism from "FedEx, They
Ain't." As you are well aware, many of us couldn't say anything at all if
we couldn't be anonymous. Frankly, one of the the things that is GREAT
about this forum is the opportunity to hear honest reports on tool, vendor,
and methodology effectiveness without the confusing filters of corporate
marketing and legal departments.
Personally, I am more leary of Chip Express after the protests of their
"Marketing Communications Director". If she really cared about delivering
a quality service, her response would have been to contact her top 5 or 10
customers to make sure they weren't having the same problems as "FedEx, They
Ain't." Seems to me like Tsipi is trying to shoot the messenger.
Thanks for the good work,
- Dan Lutes
Cirrus
( ESNUG 305 Item 9 ) --------------------------------------------- [11/98]
From: David C Black <dcblack@qualis.com>
Subject: In BC Source Code, Initialize Variables Close to Their Usage Site
John,
Your BC users should know that Behavioral Compiler needs to have variables
initialized properly to provide good results. If you fail to initialize the
entire variable in one chunk, BC doesn't recognize the initialization as
valid. Failure to initialize results in a warning messages, may create
simulation mismatches, and may create unnecessary registers.
Warning: Variable 'MAIN/ERROR_CONDITON/x_loop_connect' is not
initialized (HLS- 155)
The following is an example that might puzzle designers expecting more than
the tool currently delivers:
reg [31:0] x;
...
while (COND) begin :WHILE
if (COND) begin
x[31:8] = a;
end //if
else begin
x[31:8] = b;
end //else
x[7:0] = 0;
data_out <= x;
@(posedge clock);
end //while
Simply adding 'x = 0;' directly after the 'while' and before the 'if' saves
a register and a warning message. BC doesn't recognize that x was fully
initialized. Note that if BC sees a loop, it will put a register unless it
can determine the old value is of no use. Initialization solves this.
Alternately, you can assign a register to itself in all branches of a
conditional (pain). I recommend eliminating all BC warning messages. Only
occasionally is it acceptable to leave the warnings.
- David Black
Qualis Design
( ESNUG 305 Item 10 ) -------------------------------------------- [11/98]
From: "Sean Atsatt" <seana@sierraimaging.com>
Subject: Does Anyone Have A VHDL "make" Program ?
Hi John.
At my last company we wrote a VHDL make tool that would automatically
generate a make file given the top level VHDL module and search paths for
the source code of lower level modules. Unfortunately I no longer have
access to that tool. The firmware engineers who work with us sneer (in a
friendly patronizing sort of way) at our clumsy manual make generation. We
use vmake with modeltech to generate a make file for an already built
design, but this still requires an initial user controlled compile. Does
anyone know of a good tool for automatically generating a VHDL make file?
We also auto generate our hierarchical VHDL code from a list of modules at
each level of hierarchy. The tool we use is hand rolled and a little clumsy
since we are too busy getting chips out to refine it. If someone has a
better one we would probably switch. Any ideas?
- Sean Atsatt
Sierra Imaging
( ESNUG 305 Item 11 ) -------------------------------------------- [11/98]
Subject: ( ESNUG 304 #6 ) Pros & Cons To Running EDA On SUN Compute Farms ?
> We are investigating converting our individual high performance desktop
> Sun workstation computing model to a compute server, specifically Sun's
> E10000 server with multiple processors and up to 1 Gig of RAM on each
> processor. Does anyone have any experience with this type of compute
> server for EDA applications? What are the pros and cons of a single
> compute server model versus a "compute farm" network of high performance
> workstations?
>
> - Shuhui Lin
> Alcatel Telecom Raleigh, NC
From: Mike Coffin <mhc@Eng.Sun.COM>
John,
I'm the project lead for Dream, which is the load-balancing system for
the Sun Microelectronics ranch.
Here are some advanatages to a compute farm of high performance
workstations:
- After the workstations are a couple years old and no longer
considered fast, you can pull them out of the ranch and give them
to users. Hard to do with a E10000.
- An E10000 is a single point of failure. They are pretty reliable,
but if one goes down, or has to be off line for some reason, your
entire engineering staff may be idled.
- The workstations can be replaced incrementally with faster
machines---you don't have to upgrade everything at once.
- If you do not need the parallel processing capability of the
E10000, you are paying somewhat more for the same amount of CPU
horsepower than equivalent workstations. On the other hand, see
below.
Advantages of big servers like the E10000:
- Less system administation because fewer machines.
- Less space required.
- Less networking required.
Personally, I like Sun Microelectronics' model: a compute ranch of high
performance workstations that also contains some big servers, including an
E10000. :-)
- Mike Coffin
Sun Microsystems
---- ---- ---- ---- ---- ---- ----
From: Peter.Denyer@Eng.Sun.COM ( Peter Denyer )
John,
Take a look at my whitepaper at
http://www.sun.com/technical-computing/Publications/cfarm.html
It expands a bit on what Mike put forth. We have a couple of big compute
farms here at sun. The productivity increase in this style of EDA computing
over a desktop-centric compute model is quite amazing. Let me know if you
have additional questions on this.
- Peter Denyer
Sun Microsystems
---- ---- ---- ---- ---- ---- ----
From: alain_raynaud@mentorg.com (Alain RAYNAUD)
John,
We made the same change, and I like it a lot. Before, when we needed to run
a big job, it was a mess, both network and CPU-wise. Now we have one big
iron: it's as if you had the whole system for yourself. Of course it has
to be dimensioned very carefully otherwise everybody will be slowed down.
But you save a lot on network bandwidth (CAD jobs tend to rely heavily on
I/O). You also never swap (with several GB of main memory), so your tasks
finish earlier. Basically, you have in one place very fast disks (RAID),
the I/O that goes with it, and a powerful CPU (think L2 cache). I would
recommend no more than 30 engineers working on one such machine. But you
don't need one CPU per user, that's where you save a bit.
The problem: any downtime and your whole department is on holidays. But
it's so much easier to administer too. But I'm not saying it's cheaper
(it probably isn't). One of the drawbacks is upgrade: a powerful
configuration today will seem low-end in one year. It's easier to replace
workstation after workstation, but changing the big iron is not always so
cost-effective. Try to negociate a good upgrade deal.
- Alain Raynaud
Mentor Graphics Meta Systems Division
---- ---- ---- ---- ---- ---- ----
From: "Jim Avant" <javant@homewireless.com>
Hi John,
This is in response to Shuhui Lin's question about a Sun server vs.
individual workstations. I've been meaning to write this for awhile and
I finally got a little break in the action so here goes:
At my last company, I put together a hybrid system with a big server and
some Sparc 20s. This was supplemented with fairly high-end PCs which
everyone had. At the peak of the design effort, we had 3 ASIC designs
and about 8 large FPGA designs going on. At the time we used FPGA
Compiler on the Sparcs. Today I would do all FPGA designs totally on
the PCs (with Synplify).
I've found that wherever you go you have UNIX bigots (& Linux) & PC
bigots and you're just fooling yourself if you try to convert them. The
best you can do is have the UNIX people typing on a workstation keyboard
and the PC guys on PCs. If you set up your networking right and use NFS
& X server S/W you can create an environment where everyone is fully
productive (which is much more important than saving a few bucks). The
PC folks did all the front-end development on the PC and then logged
into the server for the rest. The workstation guys did all their
development work on the workstation and used PCs for documentation, etc.
We didn't use WABI or anything like that but you could possibly use this
to eliminate some PCs (but why bother? give the UNIX guys the
hand-me-down PCs).
We were just starting to worry about version control and were looking at
using ClearCase with the database being on the UNIX server. In general,
I've found implementing revision control in an ASIC design environment
about as easy as herding cats.
Another goal was to have an environment conducive to telecommuting (we
had to call it tele-overtime because telecommuting was against company
policy). One point that I'd like to make that has been a particular
boon of having PCs in the loop is this: The traditional way of kicking
off sim's & synthesis runs is to use telnet & X-windows server software
from home to get into your server or workstation but the problem is that
when you disconnect, you lose the connection to your windows. You
examine log files to determine progress. Now I dial into our RAS server
and connect to my PC with pcANYWHERE (over TCP/IP with full security)
and work there. I can disconnect and reconnect at will and everything's
still there! And it's still there when I come in in the morning. This
is very handy, especially with ISDN or better connection rates.
One thing we stumbled on early on was the UNIX/DOS text file
differences. We worked with several vendors to make sure their software
didn't care how the lines were terminated. Today only Synopsys has
totally ignored this request (there may be others that I don't know of).
The key to working in a mixed environment is that you DON'T CARE whether
the file is stored on a hard disk on a UNIX workstation or a PC. Keep
the file in the format that IT'S most comfortable in without regard to
where it's stored. We store MSWord files on workstations and edit UNIX
text files on PCs all the time. Text editors like pfe understand this.
Crisp is a great text editor that's available on both UNIX & NT
platforms but they just don't understand this point (believe me I've
tried).
One last point. If anyone tells you that modern PCs running NT 4.0 are
inherently unreliable please disregard this bigotry. We have PCs that
run for months without being restarted. A good network systems
administrator is worth his/her weight in gold and can make any
reasonable system run smoothly.
These opinions are my own and have changed somewhat over the years. I
hope this helps someone.
- Jim Avant
Homewireless Norcross, GA
---- ---- ---- ---- ---- ---- ----
From: Jean-Marc Calvez <jean-marc.calvez@st.com>
John,
I have seen both models... Right now, I know that for the money needed to
ensure decent working conditions for 4 persons in a centralized environment
(two Sun UltraII 336MHz processors, 2 GB RAM, one motherboard, 2*18G disks)
I could get 4 ultra60/300 workstations with 512 MB RAM (and those are OK for
simulation/synthesis, but probably weak on memory and disk for P&R). In
other words, more computing power (in the form of more processors), with
screens, keyboards and mouses thrown in as bonuses.
Still, I have no answer on which one is "better overall".
- Jean-Marc Calvez,
STMicroelectronics Grenoble, France
( ESNUG 305 Item 12 ) -------------------------------------------- [11/98]
Subject: ( ESNUG 304 #3 ) How To Find 3 Unloaded Nets Out Of 300,000 Nets ?
> I have a huge file of set_load commands, obtained from the layout tool.
> The command report_internal_loads can confirm what nets have been assigned
> via the set_load command.
>
> I am looking for a command, or script, to report the nets that have NOT
> been loaded by a set_load command. This is because I want to determine if
> there is any net that escaped the set_load command, and hence the timing
> report may be erroneous.
>
> - Andi Carmon
> Orckit Communications Ltd. Tel Aviv, Israel
From: Jean-Marc Calvez <jean-marc.calvez@st.com>
John,
One possibility is to use the following dc_shell script snippet:
foreach(netname, find(-hier,net)) {
if (get_attribute(-quiet,netname,load) == {}) {
echo "net" netname "not backannotated"
/* or whatever processing */
}
}
Note that the find(-hier,net) is usually very time consuming (alas, I would
like Synopsys spending some time optimizing those "find" and "filter"
functions that are really handy but really slow too), unreasonably so wrt
the time spend in synthesis IMO. Also you may want to redirect the output
to /dev/null to avoid too much clutter in your output file/console.
- Jean-Marc Calvez
STMicroelectronics Grenoble, France
---- ---- ---- ---- ---- ---- ----
From: Jay McDougal <jaym@hpcvcdt.cv.hp.com>
Hi John,
In dc_shell, try the check_design -post_layout command. It will generate
lots of other info about sdf annotations etc., but you can find the
non-annotated nets in the report that is produced.
In pt_shell try the "report_annotated_parasitics -list_not_annotated"
command.
- Jay McDougal
Hewlett-Packard
---- ---- ---- ---- ---- ---- ----
From: jeffb@el.nec.com (Jeff Buckles)
John,
The "-post_layout" option of "check_design" will do this for you, if you're
using 1997.01 or newer.
% man check_design
...
...
-post_layout Checks the design for annotated
information in a Links-to-Layout flow.
This information is annotated on the
design after the design has been placed
and routed by the back-end tool. This
includes delay back-annotation,
resistance back-annotation, capacitance
back-annotation, and PDEF back-
annotation (for example, clusters, cell
locations, and so on). This option lists
designs or instances that have any of
these annotations missing. The
-post_layout option must be used at
least once for a design flow to validate
the back-annotation part of the Links-
to-Layout flow.
One note: depending on how your asic vendor models I/O delays, it may
be OK to have missing net or capacitance annotation on the external
side of I/O buffers.
- Jeff Buckles
NEC Electronics Portland, OR
---- ---- ---- ---- ---- ---- ----
From: Scott Evans <scott@NPLab.Com>
John,
If your design is flat, then you can use "report_net" to get a report which
looks something like:
Attributes:
c - annotated capacitance
r - annotated resistance
Net Fanout Fanin Load Resistance Pins
Attributes
---------------------------------------------------------------------------
B 1 1 7.36 0.00 2
BBOT 1 1 7.36 0.00 2
BBOT_int 1 1 0.28 0.29 2 c, r
BIN0_int[0] 1 1 0.10 0.14 2 c, r
The c,r in the last column shows that a capacitance and resistance have
been annotated to the net. Just delete all the lines that contain c,r and
you are left with those nets that haven't been annotated.
If hierarchical you need to do something like:
report_net find(net -hier"*")
Not terribly efficient but works.
- Scott Evans
NeoParadigm Labs San Jose, CA
( ESNUG 305 Item 13 ) -------------------------------------------- [11/98]
From: bruno@fc.hp.com (Bruno Melli)
Sunject: What Commercial Tools Are There To Estimate Power Consumption ?
John,
Does anybody know of commercial tools that do power estimation for VLSI
circuits ? I know of PowerMill. Anything else available out there ?
- Bruno Melli
Hewlett-Packard Fort Collins, CO
( ESNUG 305 Item 14 ) -------------------------------------------- [11/98]
From: vschuetz@informatik.infomatik.uni-frankfurt.de (Volker Schuetz)
Subject: Problems Invoking BC-View From A UNIX Shell
Hi,
I want to use the Behavioral Compiler and the Behavioral Compiler View from
Synopsys. When invoking the bc_view from bc_shell, the configuration-file
.synopsys_dc.setup is being read by the bc_shell. The value of the variable
search_path in the bc_shell is also used by the bc_view. But when invoking
bc_view from a UNIX-shell, no configuration-file is being read. The
search_path contains only the actual directory.
Is it possible to store the value for the search_path in any configuration
file and force the bc_view to read this file?
- Volker Schuetz
Johann Wolfgang Goethe-Universitaet Frankfurt, Germany
( ESNUG 305 Item 15 ) --------------------------------------------- [11/98]
From: wlentz@ENG.Trimble.COM (Will Lentz)
Subject: Anyone Get Good Results With Power Compiler/DesignPower ? Not Me!
Hi John,
I'm trying to use Power Compiler/DesignPower to reduce power in a design.
All my gated-clocks are done manually, so I'm not using the "elaborate
design -gate_clock" approach. When I try optimizing the design for power,
it only gives a 1-2% decrease in power. From the documentation, I expected
a 10-20% reduction in power...
Has anyone had good results with power optimization using DesignPower?
I'm using the following basic methodology:
1 - compile design normally
2 - write out netlist & timing
3 - simulate design and generate ".dp" or ".saif" file (I've tried both)
4 - read design back in dc_shell
5 - read in ".saif" file (or .dp file)
6 - set_max_dynamic_power 0
7 - compile -inc
On a large design, I "characterize -power" the sub-designs and then try to
optimize them. On small test cases, I just try to optimize from the top
level.
In one case, the power actually went up 1% after the final compile! I can
give my test case or more info if it's needed. Thanks for any help.
- Will Lentz
Trimble
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