( DAC'20 Item 06a ) ----------------------------------------------- [12/02/21]
Subject: Siemens Solido Variation Designer invisible ML is Best of 2020 #6a
WHOA! SOLIDO THRIVED!: In 2019, Solido Variation Designer surprisingly
ranked at #6a in my report. It was a surprise because usually when a
really *big* fish (Siemens), eats a medium fish (Mentor), that had eaten
a tiny fish (Solido) -- the tiny fish is totally forgotten.
But instead, Solido thrived inside Siemens! So that year I had to give
kudos to the top MENT/Siemens execs behind that Solido acquisition.
Based on customer response this year (2020), Solido's usage & interest level
continue to scale. As a proxy measure, I cite I got 6,400 words this year.
2020: ########################################## 6,410 user words
2019: ############################## 4,490
2018: ################## 2,748
2017: ####### 1,282
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INVISIBLE ML: What caught my eye on the tech side was that most engineers
liked that Solido's machine learning did the job invisibly. Sort of a
I-want-the-benefits-of-machine-learning-without-having-to-handhold-it
type of outlook.
"With Variation Designer, all the machine learning is under the
hood, so the engineers don't see it. This is good thing, as
the tool should be easy to just click and use."
"I see Solido's AI as a positive. The engine has more intelligence;
and it's all behind the scenes."
"We love that its ML just works."
"I believe machine learning used by Solido can be very helpful in
analog design. It would be great if other analog tools could also
automatically optimize analog design parameters."
"I think for us Solido's machine learning is most useful when it's
automatically cutting the turn-around time for analog design tasks
with lots of iterations."
"... why did we pick Solido? We are not statisticians and we don't
know ML. It just works and it boiled down to that Solido was way
more credible and gave better support after we bought it."
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LESS IS MORE: Solido's claim-to-fame from the start has been that its users
need fewer SPICE runs to verify designs to a certain sigma level. Fewer
simulations mean less time needed and less compute resources.
"... it is the heart of the tool's value. Solido's 300 samples
could be equivalent to us having to do 10,000+ SPICE runs otherwise."
"From my and my colleague's SPICE runs, we've seen Variation Designer
cut the number of simulations from 2x to 20x depending on the sigma
target, netlist, and detail setup."
"I ran 500 MC + mismatch simulations with ADE-XL and Solido. ADE-XL
reported no failures, whereas Solido found 5 corners where the output
current was null. (I kept the number of ADE-XL simulations to 500,
rather than doing more runs in ADE-XL as full 'brute-force' analysis.)"
"... doing brute force would have taken at least 10,000s of simulations.
Depending on the circuit size, it might only take hours with Solido,
instead of days."
"Brute force is 1,000,000,000 runs. It's simply not possible to do.
Solido's sampling algorithm takes that down to 4,000 to 7,000."
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SOLIDO =/= SOLIDO: Years ago "Solido" was just what engineers used as a
shortcut for the more verbose "Variation Designer". But over time Solido
has grown to be a whole suite of specialized tools ... (to be exact, the
users discuss 6 different "Solido's" in this report.)
- Solido PVTMC Verifier "If the result is unclear, we run it to highlight
the outliers. E.g., if a result looks strange, such as a tail in a wrong
direction, or if silicon came back not showing the expected behavior."
- Solido High Sigma Monte Carlo (HSMC) Verifier "Generates normal high
-sigma (e.g. 6-sigma) results from the same number of SPICE runs for
low-sigma (e.g. 3-sigma) distributions."
- Solido Fast PVT "We use this for 3-sigma. It's a subset of standard
MC, but can run over different conditions, meaning different voltages
and different temperatures. It runs fast."
- Solido DesignSense "I like its sensitivity analysis feature, DesignSense.
It helps me quickly find the weakness of my design faster plus gives me
the overall sensitivity/yield picture quickly, too."
- Solido Monte Carlo "This is super useful for runs that take very long to
complete. Case in point: a parasitic-extracted full-chip netlist that
needs 7 to 8 days to complete a 20 run Monte-Carlo simulation. I don't
really trust the standard-deviation I get out of 20 runs using Cadence
ADE-XL, but this where I do trust Solido."
- Solido Hierarchical Monte Carlo "We use it for our SRAMS, analyzing
16-bit cells and yield for 6-sigma. That's mission critical for us.
It's more accurate because a real chip/memory block has hierarchy.
Without their HMC tool, we have to make more pessimistic assumptions."
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen in 2020? WHY did they interest you?"
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Siemens/Mentor Solido Variation Designer is a fast Monte Carlo tool
to help us determine our design's yield and find its weaknesses.
For our high sigma (>5 sigma) designs, Solido VD gave us ~100x speed
up vs. brute force MC.
Solido's use of machine learning (ML) to predict the tail helps its
scalability (as the transistors become more complicated.) Without ML,
I can't imagine we'd get higher sigma results within a reasonable
number of simulations and in a reasonable time. We love that its ML
just works.
My designs normally target >5.8 sigma. Solido was accurate there.
However it had some accuracy issues for our low yield (less than
3.5 sigma) designs.
I like their sensitivity analysis feature, DesignSense. It helps me
quickly find the weakness of my design faster plus gives me the
overall sensitivity/yield picture quickly, too.
I recommend it.
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Cadence Virtuoso ADE + Solido Variation Designer
Our normal design flow is to run process corners to make sure
our design works over all corners -- and then run process
Monte Carlo with mismatch over all corners -- to make sure
the design is within specifications.
- Our designers would have to run a large number of simulations
in ADE for Monte Carlo with mismatch to get the confidence in
meeting the specifications.
- For us, Variation Designer significantly cuts that number
of SPICE runs that normally be needed in a traditional
Virtuoso ADE MC flow. Solido's a quick sanity check.
Variation Designer hooks into ADE nicely. It uses our existing
Virtuoso ADE set-up (schematic/testbench/models) and shows which
corners, if any, did not meet our specifications.
I am looking for 4.5 sigma accuracy for my designs. Because of time
constraints, I would normally do a reasonable number of SPICE runs
and then extrapolate to 4.5 sigma. Solido is an alternate way for me
to check if my extrapolations are good or not. It tends to highlight
weaknesses in the circuit which brute force ADE MC and extrapolation
sometimes cannot highlight.
For my design, I was able to get reasonable results from Solido running
less than 1/2 the number of simulations that I would have run using
traditional brute force method.
GOTCHA #1 -- Solido's GUI is user friendly and the setup is simple.
With every tool, there is a learning curve. Solido uses our
existing ADE session. Having said that, I would like a way to debug
my circuit through the Solido sensitivity analysis, "DesignSense",
to point out which devices are aggressors -- but to have a way to
back annotate the operating point on the ADE schematic for the failing
corner. That would help me fix our issues faster.
GOTCHA #2 -- With machine learning, I like an intelligent and adaptive
methodology that allows faster and accurate simulations. Even so, one
must proceed cautiously when using ML tools, as there is this "behind
the scenes" thing going on where the user does not have access to the
ML algorithm.
Regardless, I recommend Variation Designer as a faster and accurate way
to evaluate our design; and to highlight weaknesses in it. It's a very
efficient tool to supplement the brute force method.
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Before Solido, we would have to run a lot of Monte Carlo simulations
to get 3-sigma or higher verification. With Solido, we get the same
confidence with 80% fewer SPICE runs.
For example, for our typical do 4-sigma verification:
- Pre-Solido (normal Monte Carlo), it took us 1,000 simulations.
- Using Solido, it takes us under 200 simulations.
We use it primarily with the Mentor ELDO circuit simulator.
Solido's visuals are good.
- To give us confidence, Variation Designer will display a
Gaussian curve for our sigma and parameters. Then the final
confidence/confirmation is getting good silicon. We've
done 1 successful chip this way so far; and the initial
results of chip #2 also matching well.
- The Solido help tool also has good visual explanations. For
example, there are 2-3 pages with visuals with 1-2 lines of
explanation each for a simple Monte Carlo use model.
With Variation Designer, all the machine learning is under the hood, so
the engineers don't see it. This is good thing, as the tool should be
easy to just click and use.
Beyond Solido, we haven't seen much ML with the analog EDA vendors.
We are starting to see some ML with the digital EDA tools, including
routing, and even in firmware that we develop -- but not analog yet.
Needs improvement: I'd like to see better Solido ML tool documentation,
without losing simplicity. We have to rely on the AEs to explain ML
ideas and some of my engineers are more reading vs. hearing focused;
(which reminds me -- we are very happy with Solido's support. Even
though they're deep inside Mentor and Siemens, I can still talk to their
AE about custom fixes, or to find the tool's limits. If we need custom
scripts, the Solido AEs helps us.)
We've been using it across process technologies, and it scales well.
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We use Solido during our early design stages to find worst-case corners
at a 95% confidence level in our PVT corner space. In most cases Solido
does not require us to simulate all PVT combinations.
PVTMC Verifier
Once our design reaches a certain maturity level, we use PVTMC Verifier
to find out which operating conditions will give us the worst-case
performance -- once again without needing to simulate all the operating
condition combinations.
HSMC
We use Solido's high-sigma Monte-Carlo during sign-off to verify if
our circuits meets our sigma specs and to catch outliers. It cuts
the number of SPICE runs (needed compared to brute-force) but it
still requires a significant computational effort to reach an
acceptable certainty level.
DesignSense
It allows our designers to save the worst-case PVT or worst-case
statistical corners; we then use DesignSense to fix the circuitry
if it doesn't meet the specs.
Speed Gains
Solido is fast because it drastically cuts the number of SPICE runs
to find our worst-case corners, or verify a certain target sigma.
- To do this, the algorithms must succeed in creating the models
and converging.
- From my experience, the number of SPICE runs needed to get
high-sigma verification depends on the IP. For instance, to
HS verify a linear circuit (such as the output voltage of
a low-dropout regulator) takes less effort than to high-sigma
verify a non-linear circuit -- such as the phase noise of an
oscillator. It also depends on the complexity of the IP.
WATCH OUT: There are some problems when we use Solido in a
Virtuoso/Assembler environment, like the "pre-run" scripts for
calibration. This is a major roadblock in cases where calibration
is needed, especially with a complex setup.
Learning Curve
The Solido GUI is intuitive and user-friendly. The reports give
useful information about design robustness against process and
mismatch variations. They're easy to read and are available either
in tabular form or in plots. That is good.
But because it is an advanced statistical tool, the level of designer
experience required to use it is medium to high. It's easier for an
experienced designer to use Solido and interpret the results than it
is for a junior designer, but Solido's support is high level.
Solido helps us design circuits that are robust against variation.
Through clever sampling, it drastically cuts the number of SPICE runs
needed; which means increased throughput speed. I recommend it.
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Solido Variation Designer helps with statistical analysis for our analog
designs (oscillators, comparators...). It looks at permutations of
transistors, corners (temperature, voltage, process, e.g., MOSFET,
transistor), and design variables. Mentor/Siemens claims it will give
the statistical information using fewer simulations.
Based on my experience, I believe it -- it is the heart of the tool's
value.
My group targets a minimum of 4 sigma for our designs. Our team runs
Cadence ADE-XL first, then Solido for deeper analysis.
- Once we see our design does not have a Gaussian distribution,
we use Variation Designer. The tool recommends how many
samples to run. Solido's 300 samples could be equivalent to
us having to do 10,000+ SPICE runs otherwise.
- If the result is unclear, we run Solido PVTMC Verifier to
highlight the outliers. E.g., if a result looks strange,
such as a tail in a wrong direction, or if silicon came back
and doesn't show the expected behavior.
- Then we use Solido HSMC (High Sigma Monte Carlo).
Some of our team members use Solido more heavily, depending on how many
licenses are available.
Mentor/Siemens support for the Solido tools has been very good. They
come back with help quickly; usually we meet right away to share a
screen and then they have solution within hours. Sometimes the issue
is just our set-up.
The Solido tools' ML/AI aspect is about getting more information with
fewer simulations. If ML is tested and robust, I am fine using it. I
see Solido's AI as a positive. The engine has more intelligence; all
behind the scenes.
I definitely recommend it. It's a tool to use regularly or when in
trouble and speeds up the process of finding design issues.
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For me, Solido fills a real need for fast PVT + Monte Carlo simulations
that plot data in an easily viewable format. (This is in contrast to
Cadence Virtuoso ADE's built-in Monte Carlo tool suite.)
Further, being able to easily switch tabs in Solido to see which devices
in our design cause the greatest impact on test output variation is
extremely powerful for tweaking the design to optimal performance.
Solido PVTMC Verifier
Overall, I would recommend Solido for PVTMC Verifier alone. It's a
powerful tool to have, especially for device impact analysis. It
does the same work with 95% fewer samples compared with standard
Virtuoso ADE Monte Carlo runs.
In one recent run set, Solido PVTMC Verifier reduced the number of
samples from ~64K down to only ~2.5K for a 3-sigma run. This is
comparable to Cadence's ADE (with Virtuoso Variation Option) Yield
Verification's reduction results -- and they both trade blows in
performance depending on the use case.
All my designs are 3-sigma, but generally require relatively quick
turnaround times. Solido's accuracy and coverage depend a lot on the
test case setup, but the tool's results appear to match well, if not
almost exactly, with longer "full" MC runs.
Comparing Solido to Cadence's Virtuoso ADE Explorer/Assembler:
- Some things about Solido GUI are much more intuitive and
user-friendly. Visualization of the results, statistical
information, device impacts, etc. are much more easily read
and interpreted.
- Solido's integration within ADE is also to be commended,
even if it isn't quite perfect yet.
- Every new version of Solido keeps improving, so if someone
hasn't used it in a few years, it might be a good idea to
check back in and see what's new and improved.
Solido Variation Designer can give a different perspective from the
traditional Cadence ADE flow -- and Solido PVTMC Verifier sometimes
outperforms the Virtuoso yield analysis for a given scenario.
Sometimes there are still a few integration issues with the ADE Explorer
/ Assembler setup if used from within Virtuoso, but the Solido support
staff is extremely quick and helpful to debug any issues that arise, and
their software designers appear to be on top of fixing any issues.
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We use Solido to do Monte Carlo variation simulations on our device
parameters. It takes netlists and device model files and outputs
distributions of target results. Variation Designer is able to
handle my designs, and I do not see any limits on it scaling.
It has its own sampling algorithm to cut the number of simulations to
hit similar accuracy as random Monte Carlo. I normally need 4-sigma
verification, and it does reduce a lot of simulation time.
Their customer support team is awesome. They respond quickly and are
very knowledgeable. It usually takes only one email or one call to
solve my problem.
I believe machine learning used by Solido can be very helpful in
analog design. It would be great if other analog tools could also
automatically optimize analog design parameters.
I would also like to see Siemens provide more detailed manuals.
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We target 6+ sigma for in our designs. Solido HSMC sampled simulations
let us verify out to 6+ sigma space much faster than brute force Monte
Carlo. We use it to verify circuit functionality across an extreme
PVT space. We can get functional yield within +/-0.1 sigma with it.
Our circuits range from a handful to 100+ transistors; each requiring
variation across several PDK parameters. Variation Designer's
scalability gives us acceptable runtimes on a per circuit basis so
that we can apply HSMC simulation to all the circuits that require it
across our products.
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Siemens Solido Variation Designer -
We use it to determine the distribution of parameters in our PSoC
(programmable system-on-a-chip) designs.
We've used:
a. Solido Standard Monte Carlo. We use this for 3-sigma. We
run 1 corner and specify the number of samples -- e.g.,
1 voltage setting and 1 temperature setting. We do 300-1000
samples/runs on that condition. In some cases, we know the
worse condition and only run that one.
b. Solido Fast PVT. We use this for 3-sigma also. It's a
subset of standard MC, but can run over different conditions,
meaning different voltages and different temperatures. They
have sampling algorithms that minimize the number of runs
needed to get an accurate result.
If it's a simple circuit, Fast PVT runs fast. Our designs
have 1000 or more devices, and they can take longer. We
start with 300 samples. The tool looks for the worst-case
corners across those conditions; the majority run quickly
(~15 min), but the last 10-20 samples can take an hour.
Note: we run Fast PVT *or* Standard MC, depending on what
we need.
c. Solido HSMC does 5 sigma or higher; our group doesn't use it.
d. Solido PVTMC Verifier -- I primarily run this now (except
I continue to use Solido Standard MC for one corner). PVTMC
Verifier will specify the number of samples for you.
For example, for 4 sigma mismatch analysis, we set up
environment variables (V, T, etc.), and the tool only needed
to run 100s of simulations to equal to the millions of
samples we would expect for statistical analysis of a wafer.
Bottom line: It's more accurate -- especially at 4-sigma.
And doing brute force would have taken at least 10,000s of
simulations. Depending on the circuit size, it might only
take hours with Solido, instead of days.
We use this tool to do Monte Carlo runs for mismatch for our
PSoC/Automotive designs, at 4-sigma. We were actually able
to simulate some yield problems that we would not have found
otherwise. It's very valuable.
Two items we generate a Gaussian distribution for:
1. To meet our specs, we must sometimes do wafer sort trimming.
We have internal control bits to trim circuits -- to meet
design specs to cover the distribution inherent on the wafer.
2. There are also conditions/cases where we do not trim the
circuit. For that case, we must ensure that the distribution
meets our specs without trimming.
Solido is fantastic when it comes to customer support. I've never dealt
with a vendor so supportive. We have a contact, I email him, and he
usually responds within 1-2 hours. He is very technical in certain
aspects of tool, and if he doesn't have the expertise, he invites in the
right expert. They spend real time with me.
I absolutely would recommend the Solido tools -- they are valuable.
Great people, good company. We started working with them before the
acquisitions (Mentor, then Siemens). It hasn't changed, it is still
exceptional.
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We use Solido HMC (Hierarchical Monte Carlo) for our SRAMS, analyzing
16-bit cells and yield for 6-sigma. That's mission critical for us.
Solido HMC's hierarchical features are more accurate because a real
chip/memory block has hierarchy. Without their HMC tool, we have to
make more pessimistic assumptions.
For example, the memory array is connected to the sense amp, which is a
column decoder that reads the column bit cells. Multiple memory
locations are accessed by which row is selected. So, for 128 memory
(bit) cells, all will carry the same bit line (i.e. are in same column)
and accessed by interacting with same sense amp. I.e. every bit cell
does not have its own sense amp.
So, if there are 100M bit cells on a chip, there are far fewer sense
amps. So, analyzing sense amps to 6 sigma -- it would be way
overanalyzing them and over pessimistic.
Solido HMC lets us adjust our analysis to verify the bit cells at 6
sigma and the sense amps differently, e.g. 4.9 sigma.
Solido's Simulation Reduction
Brute force is 1,000,000,000 runs. It's simply not possible to do.
Solido's sampling algorithm takes that down to 4,000 to 7,000.
There are textbook techniques to do this, such as Importance Sampling.
So, why did we pick Solido? We are not statisticians and we don't know ML.
It just works and it boiled down to that Solido was way more credible
and gave better support after we bought it. Solido still gives good
support even after Mentor acquires them, and Siemens acquired Mentor.
Solido's Accuracy
Solido HMC accuracy is 100% dependent on the transistor model you feed
it. It's predicated on the BSIM transistor model to predict parametric
yield being correlated with silicon data. Statistical analysis for
yield is highly dependent on this.
This is relevant as design teams on the bleeding edge of a process
node don't always have a great model, e.g., if they are the first
ones to tape something out.
The meat and potatoes: does Mentor Solido HMC solve our mission critical
requirement? Yes. I would recommend it.
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We use Siemens Solido on SRAM design for Monte Carlo 4 to 6 sigma,
but we usually need 5.5 to 6 sigma accuracy.
We also use it to find out which transistors are sensitive to variation.
It is useful for circuits sensitive to variation, such as SRAM circuits,
near-threshold operations, and analog circuits.
The Solido GUI is easy to use. The interface is straightforward. The
setup/inputs process is easy if you already have a SPICE Monte Carlo
simulation input file. It can take some effort to comprehend the report
Solido produces.
The tool is still improving. We sometimes find bugs; Siemens customer
support is responsive.
Solido's PVTMC Verifier verifies across PVT corners with Monte Carlo.
It is a useful flow to find best and worst cases across different
conditions with variation.
I would recommend the Solido tools for high sigma simulation for its
ease-of-use and to give designers peace of mind.
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We use Solido Variation Designer mainly for Monte Carlo simulation
focused on high sigma analysis, and random variation over PVT.
- Tool input: the same as a Spectre simulation netlist
- Tool output: table + figure-based statistic summary
For the majority of our design, we need 3-sigma, and in some special
cases, 6-sigma. From my and my colleague's SPICE runs, we've seen
Variation Designer cut the number of simulations from 2x to 20x
depending on the sigma target, netlist, and detail setup.
I think for us Solido's machine learning is most useful when it's
automatically cutting the turn-around time for analog design tasks
with lots of iterations.
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Some practical uses for Solido come to mind immediately. You can use
it to:
- Generate normal high-sigma (e.g. 6-sigma) results from the same
number of SPICE runs for low-sigma (e.g. 3-sigma) distributions.
- Generate more accurate/correct normal-sigma distributions from
a reduced number of SPICE runs. For example, if you need 300
runs to generate an accurate 3-sigma distribution, Solido will
do the same thing for 20 to 30 runs.
This is super useful for runs that take very long to complete.
Case in point: a parasitic-extracted full-chip netlist that needs
7 to 8 days to complete a 20 run Monte-Carlo simulation. I don't
really trust the standard-deviation I get out of 20 runs using
Cadence ADE-XL, but this where I do trust Solido.
But It's All About Outliers
Finding outliers. This is easily my #1 use of Solido. Outliers mean
something more than high-sigma -- they make the difference between
a circuit being functional or not.
For example, when factors that cannot be accounted for in schematic or
spice models (dependence on layout, or thermal stress, or mechanical
stress or what not) outliers in simulations might end up being closer
to the norm in silicon. Outliers can reveal sensitivities in the
circuit that may later be magnified in silicon.
Bias generator example: based on other designs I knew of cases at -40 C
where the bias generator would fail (i.e. not turn on at power-up).
I ran 500 MC + mismatch simulations with ADE-XL and Solido. ADE-XL
reported no failures, whereas Solido found 5 corners where the output
current was null. (I kept the number of ADE-XL simulations to 500,
rather than doing more runs in ADE-XL as full 'brute-force' analysis.)
My designs require 3-sigma verification which is equal to a yield of
about 99%. A conventional simulator requires about 750 runs to find
one failure, whereas Solido will be fine with 200.
Variation Designer tells users the number of simulations needed as a
brute-force alternative based on the sigma they input. For a 4 sigma
analysis it's in the order of tens of thousands of runs. For Solido
it's hundreds. Since I stop at 3 sigma, I have no way to confirm that
4 sigma claim -- part of it may just be PR by Mentor -- but I tend to
believe it from what I've seen at 3 sigma.
Other comments:
- The Solido integration with Cadence is not flawless, there are
a few bugs here and there.
- The GUI may seem hard to use at first but after some time you
get used to it and actually find it well organized.
I would definitely recommend it. We now use Solido as our sign-off
tool; not just for the full chip, but for every block.
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Related Articles
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Solido ML, BDA Ravi, Tom Beckley SSS makes #2 for Best of 2017
MunEDA on why analog designers can NOT trust Solido HSMC results
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