( DAC'19 Item 7b ) ------------------------------------------------ [04/30/20]
Subject: Avatar Aprisa benchmarks vs. Innovus/ICC2 at 7nm is Best of 2019 #7b
AVATAR MAKES 7NM: Last year's "Best of 2018" report got a lot feedback from
engineers who were happy to see Avatar back in the game. See DAC'18 #4a.
BUT, I had my typical engineer's wait-and-see doubts:
This year users shared that Avatar has since crossed that hurdle and is 100%
functional and WORKING at 7 nm.
"Avatar has rearchitected Aprisa for geometries 7nm on down, and
it showed in their results."
"The fact that we could do a 7nm design with Aprisa shows the
tool is capable and that Avatar continues to improve it."
GOING AGAINST CADENCE: This year, the users shared their results showing how
Avatar beat both Innovus and ICC2 -- but ironically, most of comparisons
are against Cadence Innovus -- a kind of back-handed compliment that Cadence
is the one to beat these days.
And it's not lost on many that this is ex-Cadence, now Avatar Chi-Ping Hsu
head of PnR R&D going directly against his old Cadence employee, Anirudh. :)
"We did a 3-way PnR evaluation of Avatar Aprisa, Cadence Innovus, and
Synopsys ICC2 this past year. ... For larger blocks in excess of
1M gates, Aprisa's TATs are 10% better than its closest PnR competitor.
For smaller blocks, Aprisa's TATs can be 15% better."
"... our Aprisa power consumption results that are consistantly
10% to 15% lower power than Innovus. Also, Aprisa runs 10% to 15%
faster TAT than Innovus for our designs."
"For my last project in 16nm, I had no choice but to use Aprisa for
our most challenging block. Both Innovus & ICC2 produced terrible
congestion and failed. By doing placement with Aprisa, we were able
meet our die size plan, which saved us millions of dollars."
SHOW ME THE MONEY: The other user's bragging point about Aprisa was something
that I don't see often. He liked Aprisa because it costs less.
"Avatar does not require us to purchase additional licenses to use
its multi-threading, while Cadence does."
"... comparable or better to those of the other two big place and
route tool vendors -- at a far lower cost point."
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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I nominate Avatar Aprisa.
We have Avatar, Innovus, and ICC2 in house here.
In general, we use Aprisa for placement, then Innovus for incremental
placement.
- Aprisa's placement is 1.2X faster than Cadence Innovus with
the same number of CPUs.
- Aprisa's placement also met our timing specs but gave us
better area results than Innovus. This is because Innovus'
placement produced congestion, and the only way we could
eliminate it, was to enlarge our block size -- which gave
us unacceptably larger area.
For my last project in 16nm, we had no choice but to use Aprisa for our
most challenging block.
- Both rival PnR tools (Innovus & ICC2) produced terrible
congestion and failed. The cost for their additional area
and project delays would have been unacceptable.
- The *only* way I could tape out and still meet our costs and
deadline was to use Aprisa's placement.
By doing placement with Aprisa, we were able to improve utilization of
that key block and meet our die size plan, which saved us millions of
dollars.
Aprisa also has good usability. In our view for floor planning, it
is the best tool available -- it is much better than Innovus or Synopsys
ICC2. Especially when you are trying to use commands rather than the
traditional "moving by cursor" floorplanning.
Avatar's technical support and access to R&D is also the best; they are
much, much better and more flexible than Cadence or Synopsys.
They listen to you.
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Avatar Aprisa
We did a 3-way PnR evaluation of Avatar Aprisa, Cadence Innovus, and
Synopsys ICC2 this past year.
Avatar has rearchitected Aprisa for geometries 7nm on down, and it
showed in their results.
Turnaround Time
Avatar's TATs are better than both CDNS and SNPS -- but it varies
depending on the blocks.
- For larger blocks in excess of 1M gates, Aprisa's TATs are
10% better than its closest PnR competitor, Innovus.
- For smaller blocks, Aprisa's TATs can be 15% better.
Avatar's reporting runtimes are much lower than Innovus or ICC2.
Aprisa's multi-threading is fairly extensive across the flow stages.
What we liked
1. Aprisa's big strength is that it's detailed routing centric
and written from the ground-up for advanced nodes. Hence,
it has a tighter pre-to-post route correlation.
2. It's adaptive MCMM gave us good runtime savings.
3. In-hierarchy-optimization for hierarchical flows gives us
good optimization across hierarchical interfaces when we do
large, bottom-up hierarchical block implementation.
4. Very good initial placement compared to ICC2/Innovus, that
translated to improved overall convergence. Aprisa placements
are less congested in our later routing stage.
5. Slack-driven CTS makes an adaptive clock tree that is
proportionate to the timing slack at the clock sinks.
Routability
We find Aprisa's congestion estimation to be much better than Innovus
or ICC2. It predicts congestion reliably at an earlier flow stage
such as pre-CTS.
Additionally, Aprisa's net and path delays scale well across the flow
stages; hence, the overall correlation is much better.
Its detailed router navigates through the complex 7nm rules to create
a post-route layout with a DRC count small enough to fix by hand.
Ease-of-use
Aprisa's Tcl-ware is straight forward and it works off standard LEF/DEF
and .lib formats -- unlike "other" PnR tools that each have proprietary
databases that cause additional lead times for flow setup.
Aprisa's commands and general scripting are intuitive, and the default
setting is tuned for the most common use cases. So, the amount of user
intervention required to guide Aprisa in terms of placement or routing
blockages, density screens, layer guidance is surprisingly low.
This could be a clincher for large organizations that spend significant
time trying to tune their PnR tool for varying block sizes and types.
Avatar's customer support is quite good. Their AEs are very prompt and
always ready to help.
We really like that the tool is easy-to-use and scalable across blocks
where we are not required to do any significant tuning or user guidance.
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Avatar Aprisa
We've found it's good at optimizing power, with our power consumption
results that are consistantly 10% to 15% lower power than Innovus.
Also, Aprisa runs 10% to 15% faster TAT than Innovus for our designs.
Aprisa's out-of-the-box flow and scripts generally work well. We did a
relatively small amount of script tweaking to get our PPA results.
For an apples-to-apples speed and costs comparison, I used a basic
Innovus license, which can use 4 cores, but we ran Aprisa on a
32-core machine. Aprisa used those extra cores to its advantage.
Avatar does not require us to purchase additional licenses to use its
multi-threading, while Cadence does. Aprisa's peak memory usage was
higher than Innovus by about 40% -- likely because Aprisa's multi-
threading more fully utilizes our available hardware than Innovus.
Other observations:
1. Aprisa's built-in timing engine correlated well with our sign-off
timing tool, Cadence Tempus, after a few signal integrity-related
settings tweaks.
2. Avatar Aprisa's area and routing was on par with Innovus for us.
3. Avatar's built-in DRC checking is on par with Cadence's built-in DRC
checking in Innovus. Other than a handful of more esoteric double
patterning related violations, Aprisa's DRC results correlated well.
4. The native LVF worked well. I use libraries with LVF support and
Aprisa has no issues reading and using them.
5. Aprisa was fine reading Verilog, SDC, or the DEF we generated from
Innovus. We had no issues with it reading the exported DEF during
QRC extraction.
6. Aprisa's double-patterning aware routing worked well overall. I did
run into some small issues with Aprisa coloring differently than the
signoff rule deck, which resulted in a handful of double patterning
related violations that I needed to fix manually or with a script.
7. Avatar's application support is very responsive and helpful. If we
find a problem with the tool, they either solve it themselves or get
the R&D team involved quickly. They turn around fixes quickly as
well.
As for Aprisa's learning curve, it is straightforward to use for an
experienced Innovus or Physical Compiler user. The commands may be
different, but the concepts are basically the same.
Aprisa is definitely worth considering as part of your tool flow. Its
capabilities are comparable or better to those of the other two big
place and route tool vendors -- at a far lower cost point.
Plus, Aprisa's ability to run on essentially as many CPU's as your
hardware supports without any additional per CPU licenses is a big win.
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We've been using Avatar Aprisa for many years. I can share some details
and describe how we use it.
Our most recent design had 6 million std cells at 7nm. The largest
design we used Aprisa for was 14nm, with 150+ Million std cells.
This is what we have done for our last few tape outs:
- First, we ran our blocks through PnR. For some, we used Aprisa
and for others, "another" layout tool. For both tools, we could
run the blocks overnight and get the results next day.
- In most cases we used Aprisa's multi-threading with 8 to 16 CPUs.
For small blocks, we used 4 CPUs, and for larger ones, we used 8
or 16.
- We then ran the top-level design through Aprisa. Once our complete
P&R flow was in place (IO, block locations, CTS grouping, custom
routing, etc.), it took me about 5 days to run the entire top-level
chip through the entire flow. This was a design with 70 blocks and
a minimal top-level logic.
For top-level, I used Avatar instead of the "other" tool because I worked
with Aprisa more and happened to know it better. Otherwise either tool
would have been ok to use at the top level.
Pre-route & Post-route Consistency
We iterate on placement before going to the routing step. We must close
timing on placement first, or there would be no point in running routing
for hours.
So, we need to have pre-route and post-route consistency, without any
significant discrepancies between the placement, clock tree, and routing
steps.
They must to be comparable, or it would be a moving target. Aprisa had
no issues here. I won't say what the "other" tool did.
Aprisa also has double-patterning aware routing that we use for 7 nm.
It works and we've also had no issues with it.
Timing optimization and correlation with PrimeTime-SI
- Aprisa has a built-in timer; its final timing was within +/- 50 psec
of PrimeTime for most of our paths -- we would not be able to finish
the chip otherwise.
- We used Avatar's settings to help ensure their results match with
PrimeTime's results, e.g. adjusting our capacitance values between
wires to be more optimistic or pessimistic.
- OCV support
The latest and greatest OCV values are modeled inside the LVF
(Liberty Variance Format) .lib timing files in a form of tables.
Aprisa can read those tables.
With the newer OCV method, Aprisa can check if a path is long or
short, and use the OCV tables, to assign appropriate OCV values.
(The old way was to blindly divide up the OCV effects for each
path, e.g. each path would get a 4% delay due to OCV, which in
case of the long paths was overly pessimistic.)
- Adaptive MCMM
We run multi-corner modes for timing -- as many as 16 corners.
Fixing timing violations in one corner, for example "hold",
where timing may be too fast, can introduce violations in a
slow corner.
Avatar uses "adaptive MCMM", so that fixing timing in one corner
doesn't create a new violation in a different corner.
- Slack-driven CTS means that Aprisa can adjust the clock delays
to pass timing.
DRC Correlation with Calibre
Aprisa has built-in DRC checking.
At the beginning of developing our 7nm flow, there were some issues
where Calibre would catch more DRC violations that Aprisa -- but we
worked closely with our Avatar AE support and now it tracks well
with catching all the DRCs that Calibre does at 7nm.
In-hierarchy optimization
Aprisa also has a hierarchical design feature where you can load the
database for the blocks you create, and then make timing fixes across
blocks within the blocks.
However, we haven't used this -- as we try to complete timing as much
as possible across blocks, so that we don't have to later reopen the
boundary path.
Conclusion
Overall, the fact that we could do a 7nm design with Aprisa shows the
tool is capable and that Avatar continues to improve it.
Plus, Avatar has great support -- much better than their PnR competitor.
With Avatar, we have a direct AE who then directly interfaces with R&D.
With the competitor there are layers between their AE's and R&D.
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We met up with Chi-Ping of Avatar at DAC. Charlie wasn't there.
Chip's going through a big change from his CDNS R&D days.
I'm talking with my mgmt about bringing them in for a closer look.
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Atoptech Avatar
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