( ESNUG 584 Item 9 ) -------------------------------------------- [10/03/18]
Subject: SCOOP -- Avatar rumors plus 6 core questions to ask at TSMC OIP
UNRELATED COINCIDENCE: On the same Monday where I heard the news about
Trump's new remake of a NAFTA2 agreement with Canada and Mexico ...
... my spies reported Avatar (Atoptech) was launching its own REV2 remake
of their Aprisa PnR tool at TSMC OIP in Santa Clara on Wednesday (today).
Word is both Mellanox and eSilicon will be speaking up for this Aprisa REV2
but it's not know whether they'll be in the Avatar TSMC OIP booth or not.
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IT'S ALL ABOUT THE 7NM PHYSICS
Supposedly this new Aprisa REV2 has a totally new "detailed-route-centric"
architecture which they claim gets 2x faster timing closure than Cadence
Innovus and 5X faster timing closure than Synopsys ICC2 "at 16nm and below".
Why? Because at 10/7/5nm local wire and via resistance crushes any
transistor delay concerns. Or to quote an earlier DeepChip write-up:
See at N16 a wire delay is 1,000X slower than a gate delay. Note that
from 16nm to 7nm there is an ADDITIONAL order of magnitude difference
(now 10,000X!) between wire delay and transistor delay. This extra
jump in wire delay has changed the classic physical layout problem from
mostly predicting long wires and high-fanout delays -- to now also
accounting for small stuff like via cuts for local interconnect. Even
very short distance, low-fanout wires are now a problem at 7nm.
- from Why we switched to Genus-RTL at 7nm
What the Avatar guys are effectively saying is placement-centric PnR tools
like Innovus and ICC2 seriously struggling at 7nm -- as in "taxicab mode"
with lots of *additional* CDNS and SNPS AE's running their respective PnR
tool to "help" the user company at 7nm -- because they're old placement-
centric tools that simply aren't detailed-route-centric like Aprisa REV2 is.
(And what the physics at 7/5nm require.) "Innovus and ICC2 are fighting
yesterday's 16/14nm PnR war; not today's 7/5nm PnR war."
Or that's what my spies tell me that the Avatar folks are saying.
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COOLEY'S 6 AVATAR QUESTIONS
Since, I have no idea who'll be at the Avatar booth at the TSMC OIP event
today, I have a fun set of questions to ask 4 different key guys who may
or may not be there.
Chi-Ping Hsu
Avatar Director
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Ping San Tzeng
Avatar CTO
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Charlie Huang
Avatar Director
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Suk Lee
TSMC Director
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Cooley Questions to ask Chi-Ping Hsu and Ping San Tzeng
- What's this about your claims that the Avatar data model and
Avatar database are more unified than Innovus / ICC2 databases
and data models?
- The standard everyday PnR flow goes in 8 basic stages
1. placement
2. trial route
3. post-placement optimization
4. clock tree
5. post-clock tree optimation
6. global route
7. detailed route
8. chip assembly
INSTEAD your detailed-route-centric approach is supposed to
run at every point in the 7 stages??? WTF? How does this
even work???
- you put out marketing hype on Path Based Timing analysis;
isn't this like what CLK-DA did -- and won't it consume too
much compute time to be viable?
Cooley Questions to Charlie Huang and Suk Lee
- Why aren't there any *certified* TSMC 7nm tech files out yet?
- Is Avatar in trouble because it doesm't have native access to
Primetime and Tempus for *basic* STA stuff? How do you do
final signoff *without* PT or Tempus?
- On SI and crosstalk issues, Avatar has zero access to Cadence
Celtic, Apache RedHawk, nor Synopsys PT-SI -- won't your
beloved Aprisa REV2 suffer from a "Gargage In, Garbage Out"
problem with 7/5nm delay calculations?
For now, I'll be interested in seeing the answers the users get on these
basic Avatar questions. I just want to understand on a core technical
level how they intend to take on Anirudh's big (and Aart's lessor) lead
in digital PnR, before I go deep on them.
- John Cooley
DeepChip.com Holliston, MA
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Related Articles
Synopsys layoffs means ICC2 rewrite is unknown for 3 to 4 years out
ICC2 patch rev, Innovus penetration, and the 10nm layout problem
Anirudh's 32 jabs at Aart de Geus's ICC/ICC2 on his Pegasus launch
8 engineers give the dirt on the Cadence/Imec first 3nm tape-out
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