Editor's Note: Yup, this year's DAC Trip Report is about *twice* its
normal size. Why? Because that physical stuff that only the foundry
people used to secretly discuss has now become part of mainstream
design! So mixed in with the usual frank discussions about coverage,
C, and synthesis, expect to also see news and gossip about IC layout,
RC extraction, and OPC tools. Enjoy!
- John Cooley
the ESNUG guy
P.S. Photos of some DAC'99 'adventures' with EE Times reporter Mike
Santarini are on the ESNUG archive site at http://www.deepchip.com !
( DAC 99 Subjects ) ---------------------------------------------- [6/99]
Item 1: DAC'99 Trip Report: "The DAC That Shagged Me"
Item 2: The Numbers
Item 3: The DAC Women's Conference numbers were half ( around 75 attendees) of what
Item 4: The Two Bigwigs' Two Big Speeches
Item 5: WE'RE ALL GOING TO THE PROMISED LAND! (YET AGAIN) Christianity talks
Item 6: Looking bass ackwards at this religious C-to-Verilog mindset, CAE Plus
Item 7: Going beyond C translating and into the C HW/SW co-design are the standbys
Item 8: LET'S GET PHYSICAL: OK, using the title of that old Olivia Newton-John
Item 9: "We have already leased several back-end tools, but we do not have a
Item 10: "IC Layout tools:
Item 11: "CadMOS Suite Demo: PacifIC noise tool. Includes device coupling
Item 12: "Physical Verification and Optical Proximity Correction (OPC):
Item 13: "IMHO one of the most noteworthy companies at DAC was Numerical
Item 14: "Synopsys EPIC demonstrated their Cedar and Arcadia tools for 'Third
Item 15: HOISTED BY THEIR OWN PETARDS In a recent EE Times, Rajeev Madhavan, the
Item 16: "Cadence: went to Verification Cockpit presentation, formal methods
Item 17: "I don't know if this is an R&D model that's sustainable."
Item 18: IS THE ESDA MARKET FLATTENING OUT? That quote: "A [ Mentor ] Renoir
Item 19: UH-OH, THE PEASANTS ARE REBELLING! In the 5 weeks before DAC'99, ESNUG
Item 20: "The drawbacks to their 'new' Avant! Nova-RTL linter are so many that
Item 21: THE "TACO BELL CHIHUAHUA" AWARD: Synopsys bought System Science. Cadence
Item 22: MAD DOGS AND ENGLISHMEN One of the more unexpected new tools from this
Item 23: BIG BROTHER INFOMERCIAL EDA In a fairly troubling new developement for
Item 24: GETTING PERFECT COVERAGE: There must be at least 6 major companies and
Item 25: "Product: SureFire's SureSolve Rating: 1 Gator (out of 4)
Item 26: "HDL code coverage
Item 27: WHERE NO SYNTHESIS HAS GONE BEFORE... In the days of olde, when the Earth
Item 28: "Cadence's Envisia (Ambit PKS) - This presentation also emphasized
Item 29: "Cadence's Distributed Synthesis (Ambit PKS/Envisia) :
Item 30: "Cadence and Synopsys are in a leapfrog race towards the goal of
Item 31: "Tera Systems demonstrated their RTL partitioning tool to automate
Item 32: IT'S DEJA VU ALL OVER AGAIN! After reading those user quotes that gave
Item 33: "Product: Avant! Jupiter Rating: 2 gators (out of 4)
Item 34: "The buzz words seem to be "one-pass" and "timing closure". I heard
Item 35: SIAMESE TWINS EDA: The next two "synthesis-aware P&R" tools are so close
Item 36: "Magma: FLOOR DEMO
Item 37: "John - A highly unscientific poll of big-chip people coming through
Item 38: "For the world of Place and Route things are about the same if you want
Item 39: THE EMPEROR HAS NO CLOTHES? For this DAC Trip Report, I had 77 engineers
Item 40: AN ACE UP THEIR SLEEVE... Scoop time! Synopsys demoed an unannounced
Item 41: OLDE FASHIONED ATPG, MEM, & BIST: Although commonly used, these types of
Item 42: "Denali makes PLI-based Memory Models, and demoed some interesting
Item 43: "Synopsys Test roadmap featured TetraMax for ATPG. They claim 5X
Item 44: AND TWO DATAPATH PLAYERS REMAIN Three years ago, Viewlogic strutted about
Item 45: WE DID NOT PRINT THAT Two weeks before DAC, Kluwer Academic sent out a
Item 46: BRAVE NEW (TEST) WORLDS In professional wrestling terms, EDA tools for
Item 47: "This year I decided I would ignore the big flashy booths in the middle
Item 48: "The company 'Formalized Design' ( http://www.formalized.com ) had an
Item 49: "BFM or Test Bench generators: Chronology's writes em just like we do,
Item 50: "Product: Summit's Visual Testbench Rating: 1 Gator (out of 4)
Item 51: "Chronology's Quickbench Verification Suite
Item 52: "According to the last data in 1997, Verisity had 84 percent and
Item 53: "Demo: Synopsys Intelligent Testbench
Item 54: MORPH'N POWER RANGERS DAC newbie Summus ( http://www.summusdesign.com )
Item 55: SKEWED DATA One the more popular new tools 'discovered' at this year's
Item 56: THE BEST DAC PARTY This year, the DAC party that got the most praise was
( DAC 99 Item 1 ) ----------------------------------------------- [6/99]
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / DAC'99 Trip Report:
_] [_ "The DAC That Shagged Me"
- or -
"74 Engineers Review DAC'99 in New Orleans, LA, June 21-25, 1999"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
As I got out of the taxi in front of my hotel and the driver had handed me
my 40 lb duffel bag -- "*HOLY-MOTHER-OF-GOD!!!" -- my back VERY painfully
went out. They checked me into my hotel room with the bellhop bringing me
in on his cart. (I tipped him $15.)
I spent 10:PM to 4:AM Saturday night three blocks from Bourbon Street on
a gurney in the hallway of the Tulane Hospital Emergency Room. They
started with Codine pills. What eventually worked 4 hours later was the
intramuscular shot of Demerol. By 4:30 AM, I was back in my hotel room,
chemically numb, tired and happy. Ah... Demerol dreaming...
I was excited about DAC. And the night before I saw that new movie
"Austin Powers: The Spy Who Shagged Me" with my girlfriend. Glasses, bad
teeth, 'International Man Of Mystery' (POOF!) I'm 'Austin Powers'!
Missing-but-we-know-he'll-be-back, past personal rival... (POOF!) Joe
Costello becomes 'Dr. Evil'. Technically-incoherent, concentrated evil,
and 1/8th the man that Joe Costello is... (POOF!) and, of course,
Ron Collett becomes the evil little 'Mini-Me'!
It's fun to dream laughing. :^)
"This is the best of all possible worlds."
- German philosopher, Baron von Leibniz, 1646 - 1716
"If this is the best of all possible worlds, what are the others like?"
- French wit and philosopher, Voltaire, 1759
( DAC 99 Item 2 ) ----------------------------------------------- [6/99]
The Numbers
-----------
This year's DAC had a 30 percent drop in attendance. DAC'98 in San
Francisco had 21,800, DAC'99 in New Orleans had 15,000. In a nutshell,
DAC is an EDA shopping trip and this year none of the cashless students
came (because it cost too much) yet most of the serious sellers and buyers
still came. ( Student/University numbers -- mostly attendees signing up
for Free Monday was 6,000. This year it was 1,600 -- the same as the last
time DAC was in Las Vegas. Also, the number of exhibitor badges was down
significantly -- 6,700 this year compared to 8,000 in San Francisco.)
As a buyer, DAC'99 was a *better* place to do some serious comparision EDA
shopping. Those reduced crowds made it easier in those 4 short days to
quickly sort out what was 'hot', what was not, and you had a few thousand
other serious fellow buyers around to compare informal notes with. ( Try
doing that same amount of EDA shopping at home and it's wasted man-months
in meetings and a momba line of glad-handing, smiling, sleazy EDA
salesdroids parading through your company's conference rooms. Ugh.)
As a EDA seller, this year's DAC was either GREAT or it sucked big time;
all depending of if you had a 'hot' tool or not.
"The amount of money spent by the EDA companies to prepare for and
staff the show was outrageous. The customers would have been much
better off if all the vendors had merely written $1K checks to each
customer who attended and said, "have a good time on us." It would
have been much cheaper and the savings could have been used to
provide better tools and support."
- from an EDA vendor who didn't have a 'hot' tool.
"One aspect I liked this year was less people crowding out the booths.
I work at a medium sized company that buys a few licences so I usually
don't get as much attention as I see those Intel and SGI badges get.
This year I didn't have to fight for demo time like I did last year."
- from an EDA buyer
"What's Not So Hot: Aspec
Hate to say it but these guys are the most unenthusiastic bunch of
people. But I guess you can't blame them. They are trying to sell
libraries which no one cares about these days."
- an anon engineer
( DAC 99 Item 3 ) ----------------------------------------------- [6/99]
The DAC Women's Conference numbers were half ( around 75 attendees) of what
they were last year (around 150 attendees), but this was to be expected
since the event ironically fell on Father's Day.
"Always make it easy for your manager or team to say 'yes' to
your proposals.
Do your homework in advance of a presentation and present the
ideas with conviction.
Always give people two acceptable alternatives when you present
them with a decision-making situation; make sure that neither of
the alternatives is a simple 'no'."
- some of the commandments, Kathryn Kranen, past-President
of Verisity, presented at the DAC Women's Conference
( DAC 99 Item 4 ) ----------------------------------------------- [6/99]
The Two Bigwigs' Two Big Speeches
---------------------------------
"First CEO Speech by Paul Otellini, Exec. VP Intel. This speech was a
not-so-vaguely disguised sales pitch for Intel IA-64 architectures and
how it should rule the world. Reportedly, a number of Sun people got
so upset about his speech, that they walked out about 2/3s of the way
into the speech. I eventually left, too. I don't like infomercials."
- an anon engineer
"BEST/WORST DAC SPEECH?
Worst - Paul Otellini's Keynote
Best - Aart de Geus's Keynote"
- an anon engineer
"Aart began by drawing a parallel between today's world in 1999 and
the world in 1499. In his view, both places were or are on the
threshold of a renaissance based on the convergence of key
technologies that had just been developed. He kept referring to a
"DAC" conference of 1499, a keynote speaker for that conference of
Captain Christopher Columbus, worries about the impending Y1.5K bug,
and a visionary in Leonardo da Vinci about a radical idea called
"System on a Ship". Lots of accurate industry insights followed."
- an anon engineer
"Next was a keynote by Paul Otellini, Exec. VP of Intel. This was a
semiconductor and Intel lovefest. Great opportunity. I recorded
Otellini and play it at night for my insomnia. Who needs melatonin?"
- an anon engineer
"I think the biggest booth presentation I ever saw was the keynote
address by INTEL. I am sorry, but that was not a keynote -- it was a
sales pitch by and for INTEL and their support companies. How does
one get a DAC booth as large as an auditorium? Present a keynote."
- an anon academic
( DAC 99 Item 5 ) ----------------------------------------------- [6/99]
WE'RE ALL GOING TO THE PROMISED LAND! (YET AGAIN) Christianity talks
about getting into Heaven; Islam focuses on Paradise; Buddism and Hinduism
offer an ultimate reincarnation into blissful Nirvana -- every major world
religion offers its followers entrance into some sort of 'Promised Land'.
This year's DAC was no different in offering the promise of C/C++ based
design as being the ultimate chip/software/system designer's ticket into
personal ecstasy. The basic idea is that in the near future, simulation,
synthesis, timing, and even your system's software will all be written
in C/C++ with happily blurred lines between what part of your design is
ASIC and what part is microprocessor(s) running software. And, Oh! What
a blissful state that will be!
To make the first converts, some start-ups offer C/C++ to Verilog/VHDL
translators like C-Level Design ( http://www.cleveldesign.com ), CynApps
( http://www.cynapps.com ), and Frontier ( http://www.frontierd.com ).
And there's already a company, LavaLogic ( http://www.lavalogic.com )
that's offering the heretical idea of translating *Java* to synthesizable
Verilog. These tools all effectively give designers the basic ability to
create C/C++/Java -> translate 2 Verilog/VHDL -> Design Compiler to gates.
(Not to be left behind, Synopsys in their NDA suites, discussed 'Scenery',
a way to standardize C/C++ for synthesis purposes and their C-based
synthesis tool -- which is almost identical to CynApps' Cynlib approach.)
"Try using the C/C++ EDA tools, and you will quickly see what they can
and cannot do. The company I work for has used high-level synthesis
tools for a long time. So far, no C/C++ tools can provide what we
need. But then again, we are tough customers."
- Geir Hedemark, Univ. of Oslo, Norway
"I agree with Geir. Evaluate some of the tools and you will quickly
see how restricted you are and the things you cannot model. Stick
with behavioral Verilog or VHDL and the world will be a better place.
The observation that one engineer had around here when discussing the
C/C++ vs. HDL argument was that the more you restrict C++ by using
class templates, etc., the more you shave off the language so that
you can synthesize it, the more funky crap you add into the language
to simulate concurrency already found in HDLs, your 'language'
approaches Verilog/VHDL! So, just stick with an HDL and be done
with it."
- John Reynolds of Intel
( DAC 99 Item 6 ) ----------------------------------------------- [6/99]
Looking bass ackwards at this religious C-to-Verilog mindset, CAE Plus
( http://www.cae-plus.com ) offers to 1000X speed up your Verilog
simulations by translating your Verilog to C, have you debug and run 1000X
faster in C, and then when everything's done, you translate your C back
to Verilog again for synthesis to gates. Watch out VCS & NC-Verilog!
The Old-School-Tries-To-Go-New-School fanatics in this new C/C++ cult
within the EDA world is Co-Design ( http://www.co-design.com ). They're
offering yet another new hardware description language called 'Superlog'
(which is supposed to combine the 'best' of both Verilog and C.) OK...
"Superlog? Isn't that the guys who did Verilog? I'm having really
tough time with another language when everyone's going C and C++.
Too many retraining, support, compatibility w/ other tools issues.
And if Synopsys is heading to synthesis from C++, the arguement is
over. All the other EDA companies are playing with C and C++, so
they can race to be the next Synopsys."
- an anon engineer's phone response when asked about Superlog
"Superlog is the way to go! Well, that's what people are telling us.
[ After being asked for names and phone numbers of these 'people' ]
Hey John, you know we can't do that -- just like at Chronologic it
took ages before people would speak in public -- and also at Ambit
it was the same. In the early days nobody wants to upset their
other mainstream suppliers (Cadence, Synopsys, etc.) by basically
telling them that they are way, way, way behind.
When we do go public with our older customers, we can let you know."
- Simon Davidmann, CEO of Co-Design, who makes Superlog
"Isuzus only cost $9, they get 94 miles to the gallon, and if you buy
one soon, you'll get a free house. They go 300 miles per hour, they
seat the same number of people as the Astrodome, and they're roomy
enough to carry the state of Texas."
- Joe Isuzu, the constantly lying car salesman in the Isuzu ads
( DAC 99 Item 7 ) ----------------------------------------------- [6/99]
Going beyond C translating and into the C HW/SW co-design are the standbys
Synopsys (Eaglei), Mentor (SEAMLESS), CAE-Plus (ArchGen), CoWare (N2C)
( http://www.coware.com ), NuThena (Foresight) ( http://www.nuthena.com ),
VaST (CoMET) ( http://www.vastsystems.com ) and Summit (V-CPU). The new
kid, TransModeling ( chip@transmodeling.com ) offers simulation over
distributed CPUs. All of these approaches offer a 'Promised Land' of
"happily blurred lines between what part of your design is ASIC and what
part is microprocessor(s) running software", but the reality is you always
have a well defined ASIC part and a uP-running-assembly part if you use
these tools. You might as well add using those olde Synopsys LMC C BFMs
with a Verilog PLI to this supposedly 'new' Mix-N-Match world of C/Verilog
HW/SW co-design 'tools'. ( http://www.synopsys.com/products/lm ) Yup,
the more things change, the more they stay the same!
"Are you trying to decide between using a processor core in an ASIC
vs. pure HW? Or, just whether to use an off-the-shelf processor
versus gates? Some random thoughts..
- Obviously, you need to size your processor. How many MIPs do
you need, 32-bits?, 8-bits? etc. etc. Use a conservative
technique like RMA to analyse your SW tasks and analyse your
system in terms of throughputs, latencies, etc. Analyse your
memory requirements. You can do a lot of this with just a
simulator/debugger.
- Sometimes, a small cheap CPLD or FPGA can augment your processor
and provide input/output processing, FIFOs or some DSP that
enables you to use a much smaller processor than if you tried to
do absolutely everything in the processor.
- You can get good, cheap GNU or other compiler/simulator/debuggers
that will help you very quickly get some performance and memory
metrics before committing to a particular processor. Vendors
will often loan you tools for such evaluations.
- In my experience, processor-based solutions demand more detailed
system analysis than HW approaches since running out of MIPS
can be death, whereas adding another HW FIR filter to an ASIC
is more of a "graceful degradation" of the solution.
- Electrical properties... Be real careful about PLLs when
considering power consumption (they're an analog component that
don't folow CMOS power rules). Check out the "sleep" modes
that processor cores offer. If you really care about power and
sleep modes aren't an option, then power-crafted HW might have
an edge.
- Don't always assume that you have to have 32-bit this or that or
multiply, etc. Compilers and their real-time libraries can
emulate such things (at a price). Benchmark with a compiler and
simulator and maybe you don't really need a DSP or 32-bit uP.
- Processors (at least the ones with good tools support) are IP
that you have to pay for.
How will you boot your processor? Flash? That costs, whereas custom
ASIC doesn't. Memory costs can swamp other costs. And finally, don't
forget auxillary costs associated with processors like supervisory
circuits, memory, etc."
- Tom Coonan of Scientific Atlanta
( DAC 99 Item 8 ) ----------------------------------------------- [6/99]
LET'S GET PHYSICAL: OK, using the title of that old Olivia Newton-John
song is a cheesy intro to user opinions about IC layout, RC extraction,
physical verification, "Optical Proximity Correction" (whatever *that*
is), noise, and delay calculation tools. Can *you* do better???
"RC Extraction and Analysis:
There were a bunch of people with RC extraction and timing analysis
products at the show including as leaders Simplex, Arcadia, Frequency
Technology, Cadence, Avant!, Mentor. The two best technical products
at the show were Star from Avant! and 'Fire & Ice' QX from Simplex.
( http://www.simplex.com )
The Avant! tools is fairly integrated with their place and route tool
and as a result does not have a very good GUI for doing custom product
flows and the resulting timing and IR drop analysis. Simplex's
solution is a drop into to the Cadence Silicon Ensemble P&R flow, and
increase the speed of their product to now time efficiently handle
>2M device databases. They have also enhanced their analysis tools
and are now the leader in post extraction RC analysis. Mentor is
focusing on DRC/LVS strategies this year and their xCalibre product
did not get any earthshattering improvements. It is still in the top
tier of extraction tools, but its current packaging w/ a reducer tool
and capacitance analysis tool (for runset generation) is still not up
to speed for production use -- expect another year for these guys to
pull the product together." ( http://www.avanticorp.com )
- an anon engineer
( DAC 99 Item 9 ) ----------------------------------------------- [6/99]
"We have already leased several back-end tools, but we do not have a
delay calculator or power analyzer. Dave and I attended several
demonstrations of physical design tools. Later, I looked at Ultima's
tools. The delay calculator I saw from Ultima seems to be a good one.
Simplex's power simulator seemed O.K. One issue is most back-end
tools will work with NCL, including delay calculators. A hot issue is
incorporating static timing analysis into the physical design to
improve performance. Concerning Simplex's Power Grid Simulation: if
we want to emphasize low-power circuits, we will want a power analysis
tool. This tool seemed easy to use, although it wasn't clear how
accurate it was." ( http://www.ultimatech.com )
- an anon engineer
( DAC 99 Item 10 ) ----------------------------------------------- [6/99]
"IC Layout tools:
IC layout had a few new players and interesting products. The big
thing now is the port of layout to the PC NT platform from the
Workstation. The new PC based IC layout products that seem to work
for large design data are ICEditors, and Silvaco's Expert. The
majority of the other vendors - Tanner, Caetena, MyCad do not do well
w/ large data or output files created by Dracula or Hercules.
( http://www.tanner.com ) Synopsys acquired Stanza this week and
Cadence is working on a similar PC based IC layout editor -- neither
of which is available as standalone commercial products right now.
( http://www.stanzas.com )
Sagantec has an interesting twist on the symbolic layout & compaction
market with a new Virtuoso add-on called 'Companion'. This is a
compactor-based interactive cell creator that works w/ new topologies
and makes them DRC clean. It is a very good technology for your
processes as the transistor definitions are very straight forward but
the underlayers and spacings are very difficult and confusing in the
design rules. At $50K/license it is reasonable as a supplement for
layout designers." ( http://www.sagantec.com )
- an anon engineer
( DAC 99 Item 11 ) ----------------------------------------------- [6/99]
"CadMOS Suite Demo: PacifIC noise tool. Includes device coupling
(Miller cap). Customers include AMD K6 and K7. Example: using a
peak-noise metric saw 4k failing nets. Using noise stability, saw
1 fail and 8 marginal nets. Interconnect model: RLC. Input is Spice
and bsim3 models. Logic/timing constraints entered via TCL files.
Could also be used in estimation scenarios, or as a custom design aid.
Runtime (based on examples shown in suite) appears strongly based on
number of transistors. 2M tx's in 21 hours on ultra 60. Required
2GB, about 1M cross-coupling caps. Provides some flexibility in
analysis (e.g., just do coupling, ignore R's.) Uses logic constraints
only on hazard free signals. (I think you have to assert that things
are hazard free). Key idea: noise stability lets you fix noise
problem by loading up output of receiver. ( http://www.cadmos.com )
Ultima Suite Demo: Nautilus-SI. Signal integrity "at 0.25micron".
Plans: Nautilus-PV for 0.18, incl. parameter variation. Nautilus-LM
for 0.13, include L's. Noise failure determined purely on a noise
margin/voltage basis." ( http://www.ultimatech.com )
- an anon engineer
( DAC 99 Item 12 ) ----------------------------------------------- [6/99]
"Physical Verification and Optical Proximity Correction (OPC):
The big news on this front was the almost non-existent position of
Dracula and the other tools by Cadence in a prominent role. Avanti
rolled out Hercules II which is a faster hierarchical checker with
enhanced flat mode checking. They are now claiming that their flat
and mixed mode checking for LVS is almost as good as Calibre. EPIC
Synopsys announced Cedar last month. ( http://www.epic.com )
The technology and integration leader at this years DAC for physical
verification was Mentor's Calibre. They have finally taken a lead
position in the marketplace and should not face any major competitors
for dealing with large designs (over 500K devices) mixed hierarchy
and mixed design methodology devices for the next 3-4 years. They
have a number of nice integration issues with the product that make
it very attractive -- including a standardized verification language
that extends to PDR verbiage as well as verification code. This
standard language is Mentor product independent -- that is their old
tools, current tools, and new tools will read the same decks so there
is no legacy data problem on old tech files. Additionally, they have
run-time optimization of the run decks, which allows for multiple
styles of run set development to still result in high performance
verification runs. Politically, Mentor had some major coups -- they
attracted several very high up technical people from the Avanti
Hercules program to aid the propagation of the Calibre program.
( http://www.mentorg.com )
Avanti has now _linked_ their DRC/LVS tools to some of the old TMA
process development to make a pseudo-suite for OPC. The tools have a
high degree of technical merit -- however they are not integrated
together well as yet and their support for the area is weak. Mentor,
through the acquisition of OPC technologies has developed a very
viable and usable OPC solution. They integrated the product around
the Calibre engine and created a GUI based tool for doing OPC runset
generation which is very easy for the process development people to
use. The runtime performance and data handling capabilities,
including new 64 bit fast viewers for the large databases, seem to
easily handle 1999 and 2000 OPC solutions. The MicroUnity and
Numerical Technologies folks have very high end technical OPC products
that are not really usable in a production environment. Their run
times are long, they produce only flat OPC data rather than
hierarchical which creates huge (>2GB) data files that cannot as a
result be viewed by current layout editors in any sort of convenient
fashion. (Virtuoso under 950x and IC442 has a 32bit address or 2GB
max file/data size limit). These products also do not really have a
maintainable runset structure that would allow for limited manpower
to maintain multiple process flows." ( http://www.numeritech.com )
- an anon engineer
( DAC 99 Item 13 ) ----------------------------------------------- [6/99]
"IMHO one of the most noteworthy companies at DAC was Numerical
Technologies or Numeritech. They offer a `phase-shifting' program
which facilitates creation of sub-0.25um geometries with +0.35um
equipment. My impression is that their s/w essentially analyzes
a database and adds patterns which cause creation of required polygons
through a combination of direct illumination and interference. This
eliminates some of the problems associated w/ sub-lambda lithography.
The license costs about $400K and is probably cheap compared to the
cost of equipment required to achieve similar geometries. However
it should be noted that the phase-shifting technique really only
applies to polysilicon and thus probably wouldn't achieve the max
possible density." ( http://www.numeritech.com )
- an anon engineer
( DAC 99 Item 14 ) ----------------------------------------------- [6/99]
"Synopsys EPIC demonstrated their Cedar and Arcadia tools for 'Third
generation physical verification and extraction'. First generation
tools ran on flatten designs, second generation do hierarchical but
impose methodology restrictions. Third generation tools used abstract
views to increase flexibility and facilitate verification re-use, i.e.
if an instance of a block has been DRC'd then other instances will not
be checked. Such abstract methodologies facilitate verification of
up to 500 million transistors. A final hierarchical run is required
to ensure no violations are overlooked. Distributed processing is
possible with Cedar. Accelerated symmetric comparison of parallel
circuits gives a 3X-50X runtime improvement. Cedar took 1 minute to
run 98 DRCs (200+ operations) on 60K transistors. In abstract mode
it took just 18 minutes to run these DRCs on 7 million transistors.
It took 9 hours to run this job in flat mode. Synopsys claim to have
a translator for Dracula and Hercules runsets. http://www.epic.com
Cadence left me with no confidence that they will be a key player in
the extraction/LVS/DRC/ERC arena as we look for a 3rd-generation
alternative to Dracula.
Pathmill now has a CTX option for cross-talk analysis."
- an anon engineer
( DAC 99 Item 15 ) ----------------------------------------------- [6/99]
HOISTED BY THEIR OWN PETARDS In a recent EE Times, Rajeev Madhavan, the
CEO of Magma, said "Technology comes from start-ups. Big companies aquire
the technology and lose the technologist." Rajeev ain't being brilliant
here; he's just saying what everyone in the industry knows. Take, for
example, the FPGA synthesis company Synplicity -- it was founded by Ken
McElvain who had just prior worked at Mentor Graphics. Synplicity now has
about 200 employees, an embarrassingly growing market share of the FPGA
synthesis business, and just announced 'Certify', a tool that does RTL
partitioning across multiple FPGAs (plus their synthesis tool) to make
ASIC prototyping trivial. ( http://www.synplicity.com ) Yet the e-mail I
received about Exemplar, the FPGA synthesis company bought by Mentor was:
"A [ Mentor ] Renoir developer told me they're being (or about to be)
re-deployed on other products. Renoir will be placed into maintenance
only mode. This is how it was told to me. Do I believe it? I did
express some incredulity at the time, but EDA is a funny business. Maybe
the bundling of MTI-Exemplar-Renoir is nothing more than a visit to the
Last Chance Saloon." ( http://www.renoir.com ) How different would this
have been if Ken McElvain had been rewarded to innovate while at Mentor?
"Adv Synth: Meropa, ( http://www.meropa.com ) a startup by the main
group of people who made the behavioral compiler. Looks promising.
Gets rid of a bunch of BC drawbacks. Also has a main synth engine,
that people who have tried it want to buy. I bet avanti buys em."
- Peet James of Qualis
( DAC 99 Item 16 ) ----------------------------------------------- [6/99]
"Cadence: went to Verification Cockpit presentation, formal methods
emphasis. Seems their formal model checking is too raw to be useful.
Seems Cadence is playing catch-up to the likes of VCS and Chrysalis
by acquiring Design Acceleration and stitching it into a cockpit
to try to sell as a solution. The glory days of Verilog-XL are
gone. Cadence is slipping. They are a logic verification has-been."
( http://www.cadence.com )
- an anon engineer
( DAC 99 Item 17 ) ----------------------------------------------- [6/99]
"I don't know if this is an R&D model that's sustainable."
- Erach Desai, Analyst at Credit Suisse, talking about the big
EDA vendors buying innovation through acquiring start-ups.
( DAC 99 Item 18 ) ----------------------------------------------- [6/99]
IS THE ESDA MARKET FLATTENING OUT? That quote: "A [ Mentor ] Renoir
developer told me they're being (or about to be) re-deployed on other
products. Renoir will be placed into maintenance only mode." says a lot.
The top four execs at Summit Design ( http://www.summit-design.com ):
their CEO, VP of Sales, VP of Marketing, and CFO have all recently quit
even though Summit has roughly $20 to $25 million in the bank. Escalade
( http://www.escalade.com ) now focuses on IP reuse and doesn't even
mention ESDA tools in the DAC'99 Exhibit Guide write-up. Novas Software
( http://www.novassoft.com ), the remnants of Summit, and TransLogic
( http://www.translogiccorp.com ) seem to be the only ones hyping next
generation ESDA developments now.
"Product: Novas DeBussy Rating: 3 gators (out of a possible 4 gators)
After hearing so much interest from Eric, Jeff, and Karthik, I took
a look at the tool myself. Debussy is a design debug/verification
tool that is coupled with the Verilog simulator of your choice. I
was also impressed by the state machine tool which extracts the state
machine diagram from the RTL code and shows the transition sequences,
the schematic drawer (both RTL and gates can be drawn), and the
automatic driver/logic cone tools. It seems to be a good tool and
would be very useful in helping people figure out IP obtained from
other sources. Debussy claims to have upgraded just in time for DAC!"
- an anon engineer
"Novas debussy adopted by Verplex and Verisure. Seems we made
the right decision going with Novas."
- an anon engineer
"Novas: HDL debug environment 'DeBussy'. "Knowledge based." Load
verilog. Browse verilog via code with hypertext links. Waveform
viewer: driven from compressed database (10x smaller than VCD file).
Drag items of interest between HDL and wave windows. Annotate source
with transitions from cursor on waveform window. All views are
coupled. Schematic editor (browser?) has coning capability. 4th
part of suite is state machine recongition. Appears to be good
environment for focusing on simulation results. Verification
engineers might have a use for this."
- an anon engineer
( DAC 99 Item 19 ) ----------------------------------------------- [6/99]
UH-OH, THE PEASANTS ARE REBELLING! In the 5 weeks before DAC'99, ESNUG
had an on-going thread where disgusted Avant! customers openly complained
about the 'new' Avant! repricing strategy for interHDL's Verilint tool.
Avant! must have been listening because, well, see for yourself.
"Somewhere in there InterHDL figured out each customer only needed one
copy because the tool is just a syntax checker and ran pretty fast.
To help their sales they put in a 27 minute timer that allowed access
to only one user for that time. This was the first way they screwed
their customers. We only bought one anyway - so there!
Now Avant! has purchased InterHDL & sent a fax to all the Verilint
customers offering to "upgrade" the license to flexlm and remove the
27 minute timer -- all for only $10K and $7K in annual maintenance.
This for a tool that originaly cost less than $10K. That's screw
number 2. If you want to buy the tool new from Avant! the list is
$47K!!! Screw 3. Sheesh, that's more than a verilog license. Who
are they kidding? This thing is a SYNTAX checker."
- [ I Am Sparticus ] from ESNUG 319 five weeks before DAC.
"It looks to me like their strategy is to move their Verilint customer
base to their Nova-Explore-RTL product. This product requires you to
run interactively in a multi-window GUI type environment. Just like
every other EDA vendor, they want to have the Holy Grail of EDA. That
is, a tool that a designer is going to sit in all day long while doing
code development and debug. I don't think Nova-Explore-RTL is it.
- Tom Loftus of Hughes in ESNUG 321 three weeks before DAC
"I just saw an ad for the Proton Rule Checker -- a lint-like tool from
ASC, Inc. ( http://www.ascinc.com ), and was wondering if anyone else
had used it and what they thought of it in comparison to Verilint. It
looks like it's time for capitalism to fix this little problem."
- Billy Vitro of Cisco in ESNUG 322 one week before DAC
"EDA Mall introduces a new concept, Session-Based Licensing. With
either a Credit Card (Available Now!) or a Purchase Order Account,
you can purchase the number of Verilint or VHDLlint licenses you need,
when you need them." ( http://www.interhdl.com )
- from http://www.edamall.com , the new Avant! website selling
Verilint at $10 per use, announced at DAC.
"Jail?!? Jail's too good for Gerry Hsu! Oh, no! And I just said
this in front of a bunch of press people!"
- a quote attributed to Penny Herscher, the CEO of Simplex, by
a number of reporters in the DAC Press Room. Gerry Hsu is the
CEO of Avant! and the EDA community widely believes he stole
Cadence EDA source code to found Avant!.
( DAC 99 Item 20 ) ----------------------------------------------- [6/99]
"The drawbacks to their 'new' Avant! Nova-RTL linter are so many that
I felt a sense of outrage about who would be stupid enough to buy this
tool. A license is required even for people who have opened the GUI
and are entering their RTL code. Thus, you are 'encouraged' to buy
enough seats to support your entire design staff. There is no
batch-mode version available although it should be out 'soon' as well.
The scorecard might be attractive for managers who like to micromanage
their staff, but I fail to see how real users would really benefit
from it since they can easily turn off any checks that they want to
make the picture 'pretty'. The list price is $35k/seat which is way
overpriced for what this tool provides. Using a text editor, a
Verilog lint checker and/or purifier, and our own scanchek tool
provides an equivalent capability to this overpriced fluff."
- an anon engineer
( DAC 99 Item 21 ) ----------------------------------------------- [6/99]
THE "TACO BELL CHIHUAHUA" AWARD: Synopsys bought System Science. Cadence
bought DAI. Avant! bought interHDL and still has some customer anger to
calm. So, this year's EDA Taco Bell Chihuahua (i.e. small but seen
everywhere) Award goes to Veritools. ( http://www.veritools-web.com )
"Avanti is 'actively' encouraging users to move to Nova-RTL by
implementing a high maintenance fee and a 23-minute lockout license
scheme that prevents users from accessing another license for 23
minutes after one use. I told Avanti in no uncertain terms that
this did not sit well with me and I would actively search for another
solution."
- an anon engineer
"I heard a lot of complaints about interHDL. Sorry if I offended
anybody... We've been using X-tek's translator, and it works great.
Everyone that has it really thinks it's superior, plus it's a LOT
cheaper." ( http://www.x-tekcorp.com )
- Joe Kryzak on comp.lang.verilog replying to interHDL founder Eli
Sternheim's suggestion to use interHDL's VHDL-to-Verilog tool
"Veritool's Undertow/IV Package http://www.veritools-web.com
Many of the same features that Debussy has are present here including
the state machine tool, source code browser, posedge/negedge source
line analyzer, perl scripting interface, RTL and gate level schematic
generation, and a built-in LINT tool (goodbye Avanti !)."
- an anon engineer
( DAC 99 Item 22 ) ----------------------------------------------- [6/99]
MAD DOGS AND ENGLISHMEN One of the more unexpected new tools from this
year's DAC was ChannelSim from Cogency. ( http://www.cogency.com )
Essentially they greatly reduce power consumption and noise generation by
promoting the design of asynchronous (they call it 'self-timed') logic.
They also claim speed-up of large combinational logic blocks like 32-bit
multipliers, etc. It's kind of odd stuff, this asynch based design. The
Cogency web site has an async tutorial, but you may also want to check out
Theseus, a company making asynch-based chips ( http://www.theseus.com )
and the University of Manchester's Asynchronous Logic Home Page at
( http://www.cs.man.ac.uk/amulet/async ).
"Most interesting niche tool? I think it is the Cogency tool for
self-timed (asynchronous) synthesis. The tool attracted me from
the practical point of view. It integrates neatly within our
existing flow like DC Synopsys, DAI's SignalScan and VCS."
- an anon engineer
"Asynch designs will be the only way these future monster Systems
on a Chip will work ten years from now. No, wait, I'll be bold
and make that five years from now. This is the most fun I've
had since the introduction of logic synthesis 12 years ago."
- Michiel Ligthart, who was employee #5 at Exemplar and is
now employee #15 at Theseus Logic
"Session 7: Asynchronous Logic Synthesis
Steve Nowick of Columbia U. presented an overview of asynchronous
circuits. He kept saying words like 'difficult' and 'complicated'
and 'hazards'. Their experimental burst mode FSM design tools can
synthesize about 15 gates. (Yes, it's that small. 15.) Ken Yun of
UC San Diego talked about timed asynchronous circuits. These are
circuits whose timing properties are very carefully analyzed. They
can run very fast, but there are no tools for them. Overall, the two
made asynchronous circuits seem difficult. Alex Kondratyev, U. of
Newcastle, mentioned that more concurrency does not mean a faster
circuit, and showed some examples. Shai Rotem and Ken Stevens, both
Intel, discussed timed asynchronous circuits, and the EDA tools
needed. They needed tools, since it's exploring a new territory."
- an anon engineer
( DAC 99 Item 23 ) ----------------------------------------------- [6/99]
BIG BROTHER INFOMERCIAL EDA In a fairly troubling new developement for
EDA, OrCAD has announced eCapture, a free version of their schematic
capture program -- but 'free' with a catch. It's hooked to the Internet
and when it senses what types of parts you're placing, for example DSP
chips, you'll suddenly see lots of paid ads for brands of DSP chips.
Big Brother Infomercial EDA. Yeach. ( http://www.activeparts.com )
"Big Brother Is Watching You!"
- a motto from Aldous Huxley's book "1984"
( DAC 99 Item 24 ) ----------------------------------------------- [6/99]
GETTING PERFECT COVERAGE: There must be at least 6 major companies and
God-knows how many side companies offering some sort of code coverage.
"Surefire's SureCov, Summit's HDL Score, and TransEDA's Verisure:
I attended these three demo suites and I feel like I'm splitting
hairs to differentiate the tools. Each of the demos pretty much
said the same things.
Surefire ( http://www.surefirev.com ) is a small startup that really
seems to want our business. They claim SureCov requires less time
overhead than their competition. They've said that each RTL file
could be instrumented separately to fit our simulation environment
and that they could recognize our state machine coding style (or they
would write the code to do it if we gave them a sample).
TransEDA. ( http://www.transeda.com ) Verisure. I did not get as
good a first impression from these people. They create one
instrumented file for the entire design which would not work in our
environment. I asked about alternatives and didn't really get a
response. They do have the cool ability to put '//Verisure Off' and
'//Verisure On' around parts of code you don't want to be covered.
For example, a default in a case statement. The tool then warns you
if you did cover the area you had turned off.
Summit (http://www.summit-design.com ) is the market leader in code
coverage. They have the advantage of being the first in the market
and acquiring the big name/big money accounts. Their tool had no
problem with the state machine example Paul sent them. They claim to
be able to handle separately instrumented RTL files. Also, they have
a bit vector coverage mode. This means that they can check that each
bit in the expression bus has triggered code. For example, if (|bus)
... would check that each bit of "bus" had triggered the "if" to
occur. They say that no one in the industry has this capability yet,
but Surefire is working on it.
Synopsys, Cadence and Veritools ( http://www.veritools-web.com ) also
have code coverage tools. Cadence is weak but free (under our current
licensing agreement)."
- an anon engineer
( DAC 99 Item 25 ) ----------------------------------------------- [6/99]
"Product: SureFire's SureSolve Rating: 1 Gator (out of 4)
Suresolve is an automatic RTL test pattern generator which works
with their code coverage tool and generates test sequences to achieve
100% code coverage. It is intended to work at the module level and
relieve the burden of writing exhaustive testcases. In some cases,
I can see this tool being useful. However, generating tests just to
achieve a goal of 100% coverage seems strange to me. Many problems
in verification are found when modules interact with each other. As
modules get larger, the number of possible states grows exponentially
and the tool will break down.
Product: SureFire's SureThing Rating: 2 Gators (out of 4)
This new product combines several tools from their product line
together within an integrated environment. Although I'm always wary
when vendors try to provide a complete solution, this suite combines
an interpreted Verilog simulator, a source-code debugger, a waveform
viewer, a built-in lint tool, automatic FSM analysis, code coverage,
and automatic RTL test vector generation. This is a nice package of
tools together, but the same capability can be provided using a number
of point tools together. Several of these point tools exceed the
capabilities of the Surefire tools, so the main advantage in these
tools is their integrated environment.
- an anon engineer
"Cover Tools: same old. Most have added linters or other things.
Surecover generates a testbench to bring your test coverage up to
100%. No correlation to reality. I think it would die easily on
a large scale verification environment with lots of levels, and even
if it didn't, there is no correlation to what it has done for you."
- Peet James of Qualis Design
( DAC 99 Item 26 ) ----------------------------------------------- [6/99]
"HDL code coverage
Surefire verification is on the show floor now. Technology looks
excellent. They actually bundle a simulator and linter with code
coverage and block-level test stimulus generation for under $25K.
Covermeter, Verisure, et all are jumping each in tiny leaps.
Recent enhancements include automated FSM extraction. Yawn.
Silicon Forest is unusable. If I can't understand the demo for
something as simple as functional verification coverage in 5 minutes,
they don't understand what problem they are trying to solve.
( http://www.sifr.com )
Didn't have time to check Leda." ( http://www.leda.fr )
- an anon engineer
( DAC 99 Item 27 ) ----------------------------------------------- [6/99]
WHERE NO SYNTHESIS HAS GONE BEFORE... In the days of olde, when the Earth
was still cooling and the dinosaurs ruled the planet (i.e. about 3 years
ago), designers used to synthesize from Verilog or VHDL to a netlist,
hand that netlist to the Foundry Gods, and do 'The Waiting'. During 'The
Waiting', the all-knowing, all-seeing Foundry Gods magically did P&R and
other mystical things and eventually gave us back chips. Now, in modern
times, mystical P&R is creeping into synthesis. And big synthesis running
across *multiple* workstations is on the scene, too.
"Synthesis:
a) Merging of synth and layout is coming. The best solution looks
to be from the Cadence Ambit PKS/Envisia tool. We need to get our
hands on it. Avanti is hurting without a real synth connection.
Synopsys has Chip Architect as a stop-gap. Most current solutions
are tool combo's that take a couple of existing tools and have sort
of a glue tool in between. The down side is that the databases are
still not capable with all the necessary info, and the user is
required to wear two hats (needs to be P&R person plus RTL synth
person to run them). The Ambit PKS/Envisia stuff has the database
best suited for both P&R for RTL features. Theirs also looks like
the easiest for an RTL person to use with minimal P&R knowledge.
They are hungry to try it on a big chip. They are hungry to drive
Ambit. I got no vibe from any Ambit/Cadence people about Cadence
shelving BuildGates. Quite the opposite. Cadence may be fearing
losing P&R buisness if they do not integrate synthesis and do the
work up front.
b) Automatic synth and distributed process runs. Synopsys ACS is
here. It looks to be viable. It does distribution to multiple
machines (using multiple licenses of course; they all do). It only
comes with an ultra license. The Synopsys offering is a bit further
along and changable by the user. Ambit's offering is free, has
more distributed stuff (like a very cool job status and control
center), has the push button approach, but is less configurable.
Both tools have nice stop, check and restart features. Both are
hungry to get these working on big designs. We need a multi
license, multi server environment to take advantage of the features.
c) Post synth design exploration. Synopsys is *finally* upgrading
the older-than-time-itself Design Analyzer. Auto cones of logic,
with timing info. No fix-on-the-fly yet, but they say it is coming.
No name for it. No word on if they will charge or give it free.
I requested something like this 10 years ago. Ambit has had this
from the start, and theirs lets you fix stuff on the schematic
for automatic updating. Synopsys is doing a HDL compiler re-write."
- an anon engineer
( DAC 99 Item 28 ) ----------------------------------------------- [6/99]
"Cadence's Envisia (Ambit PKS) - This presentation also emphasized
single-pass timing closure. It showed how system-level constraints
were used throughout physical design:
Floorplan
Block place
Power plan
Standard cell place and optimize
Clock tree synthesis
Delay optimization
Power routing
Clock routing with power and ground shielding
Final routing
RC extraction
It's clear that Cadence is solving deep sub-micron issues with this
approach. It also makes sense to incorporate timing at all levels.
However, the flow is complicated compared to Magma's."
- an anon engineer
( DAC 99 Item 29 ) ----------------------------------------------- [6/99]
"Cadence's Distributed Synthesis (Ambit PKS/Envisia) :
They showed 2-3x improvement for designs using 5 CPUs. The steps the
tool followed were
1) partition
2) budget and create jobs
3) submit the jobs to a queue for execution
4) reassemble
The user simply adds resource information to their script and adds the
'-distributed' flag when optimizing:
do_optimize -distributed
The tool had some useful graphical displays which the designer could
use to analyze the distribution of jobs and adjust for the next run.
Each CPU requires a full synthesis license. The QOR (Quality of
Results) will be the same for any distributed optimization (no matter
how many CPUs were used) because the jobs would be set up the same.
However, the QoR was different than a single CPU optimization.
Compared to a single CPU, distributed optimization often had designs
that had 2-3% slower clock."
- an anon engineer
( DAC 99 Item 30 ) ----------------------------------------------- [6/99]
"Cadence and Synopsys are in a leapfrog race towards the goal of
concurrent logical, physical, and timing optimization. Right now,
I'd say Cadence has the lead."
- Rita Glover, EDA Analyst, in the 7/99 issue of EE Times
( DAC 99 Item 31 ) ----------------------------------------------- [6/99]
"Tera Systems demonstrated their RTL partitioning tool to automate
structured design for optimization of performance and density.
According to the makers, the tool provides feedback which should
lead a designer to optimize HDL code rather than rely on the less
productive physical optimization of inferred logic. Could be worth
a closer look. ( http://www.terasystems.com ) I also heard that
Aristo had something similar, but I did not get a chance to see it."
( http://www.aristotech.com )
- an anon engineer
"TERA SYSTEMS
This is a RTL-level floorplanner. It offers RTL area and timing
estimation. Automatic RTL partitioning. Hierarchical area and
timing budgeting. Hierarchical chip and block-level floorplanning.
Routing estimation. RTL in-place optimization. Hierarchical design
management.
This tool is written for the front-end designer. They write out
files that drive Synopsys for synthesis and Cadence and Avanti for
chip assembly. This tool is available now."
- an anon engineer
( DAC 99 Item 32 ) ----------------------------------------------- [6/99]
IT'S DEJA VU ALL OVER AGAIN! After reading those user quotes that gave
the impression Synopsys Chip Architect and Cadence Ambit PKS are very
similar, now user first impressions of Avant!'s 'Jupiter' see it, too, as
very similar to Synopsys Chip Architect. And Avant!'s tool is designed
to feed into Synopsys' Design Compiler (which surprised me!) Gut reaction
without having seen Jupiter -- it just might be warmed over Planet-RTL.
When the going gets tough, many times the tough will change their name.
"Avanti's Jupiter: This is Avanti's answer to Synopsys' Chip Architect.
It addresses the synthesis/place and route timing closure problem by
doing floor planning before synthesis. The tool takes in RTL code, a
TDF constraint file, and library information (will accept .lib format).
The RTL code is linted and then pre-synthesized. (RTL Explore,
previously Verilint, is embedded.) The tool produces a floorplan,
custom wireload models and a Synopsys constraint file. From there you
go directly to Design Compiler. Optionally you could use their VDSM
(very deep sub-micron) synthesis tool, but I'm skeptical because their
salesmen didn't seem very excited about that capability. Finally
we've already got Apollo's place and route. Jupiter requires ("works
better in") a top-down design methodology."
- an anon engineer
( DAC 99 Item 33 ) ----------------------------------------------- [6/99]
"Product: Avant! Jupiter Rating: 2 gators (out of 4)
This is Avant!'s new front-end tool for "physical synthesis" which
is used to do preliminary floorplanning and placement of macros. RTL
can be read into the tool where a "dummy" synthesis is done to
generate size and timing estimates. Blocks not yet available can be
assigned a "black-box" based upon the estimated size of the block.
Rat's Nest type global routes can be done and graphically displayed
to help place blocks. Busses can be defined and manually placed
between blocks. Once a user is satisfied, custom wire-load models
per block can be generated. Timing constraints can be applied and
then written out into a TDF file which is given to the Apollo P&R
tool to chew on for the final layout. I saw some interesting
capability here which might help us achieve timing closure for bigger
designs. However, it appears that we would probably need some
trained experts to help guide us through the tool."
- an anon engineer
( DAC 99 Item 34 ) ----------------------------------------------- [6/99]
"The buzz words seem to be "one-pass" and "timing closure". I heard
horror stories of 4-17 iterations required for designs in order to
meet timing closure. To deal with this problem Synopsys, is releasing
Chip Architect and Avant! is releasing Jupiter. Both are front end
floorplanning, quick synthesis, placement, and global routing tools
that pass interconnect information to Synopsys Design Compiler."
- an anon engineer
"If Avant!'s product is based on ACEO, then we have a good idea of
what it is and consider it a non-threat."
- Sanjiv Kaul, Synopsys VP. ACEO is Avant!'s synthesis tool.
"I talked to TI to get a better understanding of how their new tool
flow is expected to work. With their push to using Avanti layout
tools (Planet-PL), TI pledges that they will initially couple their
support engineers with design teams to jointly layout designs
together. Within about a year, they plan to push the floorplanning
solely into the designers hands with minor assistance from the field
engineers. They plan to evaluate using the new Jupiter tool from
Avanti, but they have no commitment about it in their design flow."
- an anon engineer
( DAC 99 Item 35 ) ----------------------------------------------- [6/99]
SIAMESE TWINS EDA: The next two "synthesis-aware P&R" tools are so close
together, so similar, most users can't technically distinguish between
them: Magma Design Automation ( http://www.magma-da.com ) and Monterey
Design Systems ( http://www.montereydesign.com ). To better understand
where we're at, I've got to cite an illustration Richard Goering of
EE Times uses:
Extend Synthesis Post Synth Synthesis Between
Into Phys. Design Optimization Down To P&R Synth and P&R
(Synopsys Chip Into P&R (Avant! Jupiter, (Sapphire,
Architect) (Magma, Monterey) Cadence/Ambit) Silicon Perspec)
--------------- ---------------- ---------------- ----------------
| SYNTHESIS | | SYNTHESIS | | SYNTHESIS | | SYNTHESIS |
|OPTIMIZATION | ---------------- | OPTIMIZATION | ================
| PLACEMENT | ---------------- | PLACEMENT | | OPTIMIZATION |
|BLOCK ROUTING| | OPTIMIZATION | | BLOCK ROUTE | | PLACEMENT |
--------------- | PLACEMENT | | CELL ROUTE | | BLOCK ROUTE |
--------------- | BLOCK ROUTE | ---------------- ================
| CELL ROUTE | | CELL ROUTING | | CELL ROUTING |
--------------- ---------------- ----------------
Verbally, Chip Architect does everything but the final Cell Route. Magma
and Monterey takes Design Compiler output and does the rest. Jupiter and
Ambit does it all. Sapphire and Silicon Perspective sandwitch between
Design Compiler output and other people's Routers. Now, here's what users
thought of Magma and Monterey at this year's DAC:
"The new guys, Magma and Monterey, are examples of the 'synthesis aware
layout' approach. Magma strips the synthesis-created netlist back to
equation level and are prepared to not only do buffer insertion and
sizing but also logic reorganisation and cloning to maintain timing at
P&R time. As far as I can tell, Magma is also the first company to
automate Ivan Sutherland's Logical Effort Paradigm for sizing circuits.
Monterey has an incremental refinement approach -- basically everything
is up for modification as the cells are being placed, globally routed
and detail routed. Both Magma and Monterey are "guaranteeing" a one
pass P&R that meets timing.
Don't know if its true, but it sure is an attractive story!"
- an anon engineer
( DAC 99 Item 36 ) ----------------------------------------------- [6/99]
"Magma: FLOOR DEMO
Integrated technology mapping, placement, routing, and timing. They
take a synthesized netlist, unmap it, use technology-independent
variable-strength gates, assign strengths to meet timing (taking
loading into account) and finally place & route. Midway through
the flow, before P&R, they provide a "MPG" -- a performance
guarantee that they will be able to meet timing.
Magma: SUITE DEMO 1: "BLAST FUSION"
Two part flow; MPG given between the two. Timing constrains in
Synopsys Primetime format. Crosstalk taken into account during track
routing (router is global; then sub routing, then track routing, then
final). Overall flow: verilog, lef, .lib in, GDSII out. Extractor:
field solver to produce rules, then used by Quasi-3D extractor,
including cross, lateral, area, and fringe caps. Have tested on 1M
placeable objects, ran in <2GB memory (this was a bogus netlist).
Magma: SUITE DEMO 2: "SIGNAL INTEGRITY"
This works during the "blast builder" phase, which is also doing
timing analysis. Noise target: fraction (e.g., 25% of Vdd). Current
analysis: crosstalk, noise/delay optimization, IR drop analysis.
Planned: EM (AC & DC). Basics: added crosstalk awareness to router.
When tool does not work, can do shielding through the TCL interface.
Wire sizing: limited capability. Concept of Magma's stuff is "logical
effort" which is published. Incremental net-by-net extractor. Can
write spef/dspf. Timer: .lib, incrementally better interconnect.
Supports PrimeTime constraints. Also look at drive/wiresize, for
signal EM. Includes buffer insertion; can use TCL to do shielding.
Buffer insertion manages both long wire delay, and breaks up coupling
caps. Track router observes timing windows. Global routing drives
buffering for noise. Router is interactive; can rip up and reroute
if solution is not correct for noise at end. Example (live demo
claimed): 20k gates, 5k placeable cells.
Monterey: FLOOR DEMO
Simultaneous synthesis, P&R, extraction, timing, noise analysis.
(Note: noise analysis is not really there.) PD dissolves/flows
cells across floor planned boundaries, unlike Magma. Claimed
integration with standard flows.
Monterey: SUITE DEMO: "Dolphin"
Simultaneous P&R, timing, logic optimization. Open architecture for
cost function. Model refined during design flow and across views.
Cells migrate across floor planned boundaries for both timing and
congestion. Timer is PrimeTime compatible. Reads simple Synopsys
constraints. For complex ones, go into Design Compiler then do a
"write_script" to get constraint file that tool can read. Tool
does timing, buffering. Simultaneously creates clock tree while
placing latches. User specifies preroutes as desired (e.g., I/O's,
megacells, routing of global clock). Partnered with Coyote Systems'
BEM tool (field solver?). Still working to define ECO flow with
beta partners. Shape based router; tool can do width selection. Scan
chain reordering to reduce congestion. Recommend: ATPG after P&R.
Largest example: 280k cells, 800k gates, 1200 microns on a side1.
1-2 days run time on a multiprocessor (Sun 6500, 24 processor,
24 GByte). Input: .lib, netlist, lef, Synopsys timing constraints.
In-memory data model, checkpoint capability.
Tools historically have a 5 year lifetime, they'd like to do better.
Said HP N-class machines have much better memory bandwidth than Sun."
- an anon engineer
( DAC 99 Item 37 ) ----------------------------------------------- [6/99]
"John - A highly unscientific poll of big-chip people coming through
our suite:
40 percent: "Monterey is brilliant, Magma is a mess"
60 percent: "Magma is brilliant, Monterey is a mess"
Very polarized."
- from a non-competing EDA vendor
( DAC 99 Item 38 ) ----------------------------------------------- [6/99]
"For the world of Place and Route things are about the same if you want
to tapeout prior DAC 2000. There were several new players on the
field rolling out products - Magma, and Snaketech, being the most
prominent - but their technologies, features and support need about
another year before they are ready for production environments. As an
example of too early a release - the Magma P&R environment while
supporting timing driven layout - only targets +/- 15% timing accuracy
and does not allow an ECO loop without going back to the floorplanning
stage. The leaders are still Avanti with Apollo and Cadence with
Silicon Ensemble. Silicon Ensemble did not roll out and new
groundbreaking features at the show - just some standard updates and
patches. Avanti did rollout their new 'connectivity-based' layout
editor 'Discovery' which allows for polygon edits to the design INSIDE
the P&R environment which means that ECO, timing and routing info is
not lost through export-import with GDSII. For mixed signal design and
'non-standard application' processes this is a major advantage as you
can now tweak the power supply and bias lines to meet 'non-timing'
critical performance. Gambit's design software was acquired by
Synopsys in Q1 and was not listed as a currently available standalone
commercial product." ( http://www.gambit.com )
- an anon engineer
( DAC 99 Item 39 ) ----------------------------------------------- [6/99]
THE EMPEROR HAS NO CLOTHES? For this DAC Trip Report, I had 77 engineers
respond. And, as a rough cut on how engineers comparitively saw all these
new physical tools, I did a quick keyword count.
Magma 'Blast Fusion' 103
Avant! Jupiter 48
Cadence Ambit PKS/Envisia 26
Monterey Dolphin 22
Synopsys 'Chip Architect' 9
Tera Systems TeraForm 5
Sapphire FormIT/NoiseIT/PowerIT 3
Silicon Perspective 'First Encounter' 3
Aristo 'IC Wizard' 2
Mentally checking the data, it made sense. The between-synth-and-P&R
tools like TeraForm, Sapphire, Encounter, and IC Wizard weren't big news
items compared to the Magma/Monterey/Avant! stories. What surprised me
was that so few engineers made reference to Chip Architect from Synopsys.
Roughly a 10X difference between it and Magma.
When I mentioned this to the Synopsys top brass, they said lots of users
saw the Chip Architect demo at DAC and loved it. To take a fair approach
to this, I told them to send me the names, e-mail addresses, and phone
numbers of the users who saw the demo at DAC and I'd survey them about
Magma/Jupiter/Ambit/Monterey/Chip Architect. Their first reply was that
they couldn't "violate the privacy of their customers by giving out their
names." Later, I was told that they had contracted an outside consultant
to survey the users and "two people surveying at the same time can mess
things up. We'll share the survey results with you, though." Whatever.
So, from the outside looking in, while it appears that Magma made the
biggest customer impression at DAC -- it also appears they may be grabbing
defeat from the jaws of victory because the industry gossip is that
Magma's VP of Worldwide Sales, Kevin Lynch (confirmed), Magma's VP of
North American Sales, Bruce Costello (confirmed), and three of their R&D
staff (rumored) have all quit. Other bad news for Magma is that Atiq
Raza, the Prez of AMD, has resigned from AMD. Raza is on the Magma board
and drove the AMD/Magma relationship. No Raza may mean no Magma at AMD.
"All glory is fleeting."
- Roman proverb
"Why did the "no iterations" company, Magma, give away boomerangs?
If you're using a boomerang properly, you'll be doing lots of
iterations. Confusing message there."
- Lee Bradshaw of Alantro
( DAC 99 Item 40 ) ----------------------------------------------- [6/99]
AN ACE UP THEIR SLEEVE... Scoop time! Synopsys demoed an unannounced
tool called 'PhysOpt' at DAC. And, from the technical descriptions I've
heard, it's a Magma/Monterey-like tool. Chip Architect works managing
designs on the 'hundred(s) of blocks' level. PhysOpt (like Magma and
Monteray) works on the 'millions of cells' level doing highly intelligent
placement as a part of synthesis. (One user I spoke to said "you just do
some extra commands in your DC flow and it handles everything.") Ya
gotta keep watching those Synopsys guys. You never know what's next!
"They got it from IBM, did some work on it, and it didn't work at
first. They got an ex-LSI guy to redo PhysOpt with some special
algorithms and now it works. It's just a few more lines in your
DC script. No need to buy or learn Chip Architect. More importantly,
no more bloody wire load models! All the work is done in their
placement engine which focuses on congestion over timing. (A lot of
placers focus on timing and have later congestion problems.)
My only concern is that Avanti had a front-end placer like this that
didn't match their back-end placement. If Avanti had this problem
in-house, how can Synopsys PhysOpt handle this? They claim PhysOpt
feeds PDEF 2.0 into the Cadence and Avanti routers and it works. The
other issue about placement is you have to tell it about power and
ground. How will front-end Synopsys RTL-to-placement tool do this?
PhysOpt is high on my list of tools to in-house eval."
- an anon engineer
"Synopsys demonstrated Chip Architect. This tool is for chip-level
hierarchical design. PhysOpt will include logic synthesis and key
physical functions to yield gate-level timing-driven placement at
block level. Acquisition of Everest added FlexRoute to tool suite.
Used for top-level detailed gridless route and for block-level global
route. ( http://www.everest-da.com ) A shift towards more Synopsys
tools such as PhysOpt should really only be necessary if Cadence PbOpt
is inadequate. Deployment of tools such as Magma's BlastFusion may
give an additional area reduction but I'd have to see some real
in-house examples before I'd advocate addition of such a tool to our
flow. RTL partitioning a la Tera Systems is also worth evaluating as
could Ultima's clock-skew tool." ( http://www.terasystems.com )
- an anon engineer
"SYNOPSYS - PhysOpt
This tool is used in conjunction with a RTL floorplanner. It reads in
a PDEF file from Synopsys's Design Architect and does Synthesis and
Placement simultaneously. It works on one block at a time. Clock
Tree Synthesis (CTS) is not available, so the final placement would
have to be redone causing possible iterations. You must break the
design in to blocks. They claim that they have a better placer than
Avanti and Cadence, but since they don't route the design and don't
offer CTS, the placement would have to be redone anyway.
This tool is supposed to be available late this year."
- an anon engineer
( DAC 99 Item 41 ) ----------------------------------------------- [6/99]
OLDE FASHIONED ATPG, MEM, & BIST: Although commonly used, these types of
test for manufacture tools didn't make the big news like they used to at
past DACs. Only a few engineers talked about them. Guess they're pretty
much 'solved problems' in EDA (like simulation and basic synthesis.)
"LogicVision seems to have good stuff for logic & memory BIST. They
seem to be ahead of their rivals." ( http://www.logicvision.com )
- an anon engineer
"ATPG:
Synopsys TetraMax is the next generation of Test Compiler. Synopsys
claims that it's intended to handle larger designs (1.5M+ gates).
EDA Direct and ATG Technology where also at DAC and gave me business
cards. ATG was promoting sequential ATPG. ( http://www.atgtech.com )
I ran into a guy named Al Crouch at the Mentor's Design-For-Test
booth. He clued me in on a bunch of scan chain problems, so I feel
obliged to put in a plug for his book "DFT for Digital IC's and
Embedded Core Systems". Al definitely had a strong opinion that
Synopsys' Test Compiler is an inferior product. (Probably why
Mentor Graphics hosted him at their booth).
Here are the scan chain gotchas he told me to watch for if we allow
Avanti Apollo P&R to restitch the scan chain:
1) Apollo will not recognize separate clock domains when it
restitches. It simply routes from flop to nearest flop without
regard to the clock. To get around this you need to put each
clock domain on a separate scan chain and explicitly tell Apollo
which registers are on which chain. (I think that putting each
chain on it's own enable facilitates this.)
2) We cannot allow Synopsys to put buffers along the chain. Apollo
ignores them, routes flop to flop, and leaves the buffers and
inverters hanging.
3) Apollo does not have any sense of timing, so when it restitches
and routes to the flop next door it could cause hold violations.
Al mentioned a design he had with about 5000 flops. Apollo
introduced 3000 hold violations.
Email Al_Crouch@prodigy.net w/ questions. He was a really nice guy."
- an anon engineer
( DAC 99 Item 42 ) ----------------------------------------------- [6/99]
"Denali makes PLI-based Memory Models, and demoed some interesting
utilities where you could interactively view the contents of the
memory as it changes, in all different formats including disassembled
code. I had previously only thought of Denali as a model provider.
Some of their utilities built into the models suggest they can help
debug some more complex memory problems such as Address analysis,
FLASH 'weathering' or DRAM refresh." ( http://www.denalisoft.com )
- an anon engineer
( DAC 99 Item 43 ) ----------------------------------------------- [6/99]
"Synopsys Test roadmap featured TetraMax for ATPG. They claim 5X
speed improvement over Test Compiler, 10X capacity improvement and
2X vector compaction. We'll see."
- an anon engineer
( DAC 99 Item 44 ) ----------------------------------------------- [6/99]
AND TWO DATAPATH PLAYERS REMAIN Three years ago, Viewlogic strutted about
the place with its Silerity datapath compiler -- now it's history and the
two remaining players are Synopsys Module Compiler and Arcadia's Mustang.
"Arcadia demonstrated their Mustang datapath layout synthesis tool.
The tool takes a Verilog or EDIF netlist, performs Regularity
Analysis, Datapath Partitioning and Datapath Placement. Placement
can be varied, e.g. using Interleaving or selecting #rows/bitlslice.
Placement file is exported (DEF?) to detail P&R tool; Cadence SE and
Avanti Apollo are supported. Example presented was 16X16 multiplier.
Demonstrator wasn't sure if Mustang could handle a multi-tap FIR
filter. Also no figures for area, timing or power gains associated
with Mustang's usage. Price: $100K. ( http://www.arcadiadesign.com )
Synopsys Module Compiler reported they can now produce relative
placement information to ensure optimal layout of datapath elements."
- an anon engineer
( DAC 99 Item 45 ) ----------------------------------------------- [6/99]
WE DID NOT PRINT THAT Two weeks before DAC, Kluwer Academic sent out a
flyer advertising various chip design books. ( http://www.wkap.nl ) The
book "Understanding Behavioral Synthesis" by John Elliot, a Mentor
employee, was on the cover of the Kluwer flyer. This got me curious
because Mentor offered an interesting new behavioral synthesis tool,
Monet, two years ago -- so I wondered if the book was about Monet or
Behavioral Compiler from Synopsys. At the Kluwer booth at DAC, I asked
for the book. The guy in the Kluwer booth said "Mentor bought the entire
first edition run for its customers." I said, "That's OK. I just want
to look at a copy of it for a minute." He replied: "Legally, all I can
say is that Mentor bought the entire first edition run for its customers."
Oh. So 750 copies in that first printing at $115 each, that's $86,250
Mentor spent to hide something... Hmmmm....
"The worst freebie was Altera's pool cues -- these did not unscrew
in the middle -- how the hell do you get them on the plane????"
- an anon engineer
( DAC 99 Item 46 ) ----------------------------------------------- [6/99]
BRAVE NEW (TEST) WORLDS In professional wrestling terms, EDA tools for
*functional* test are in an 8-way or 10-way 'free for all'. Read for
yourself and you tell me who's going to come out in top!
"Cadence's Affirma Cockpit (i.e. their warmed-over DAI Signalscan)
Another example of an oversized beast which is supposed to be the
end-all of all verification tools containing DAI's signalscan,
NC-Verilog, Affirma Model checking, yada, yada, yada. Signalscan
is still a standalone tool and has some new upgraded features for
doing transaction checking (things like verifying a valid PCI
cycle has occurred, a valid cell transfer is okay, etc.). Signalscan
still has its source-code window browser, but it seems Novas Debussy
and Veritool Undertow have now surpassed its overall capabilities."
- an anon engineer
( DAC 99 Item 47 ) ----------------------------------------------- [6/99]
"This year I decided I would ignore the big flashy booths in the middle
and walk around the edge. Wow, was there some interesting stuff!
Take a look at HDAC. ( http://www.hdac.com ) I spotted their stand
in the far corner. They do static functional RTL verification that
does quasi model checking which seems very easy to use and appears
to actually work (in demo, of course.) They said Tandem and Cisco
are currently using their tool, 'Solidify'. It a different approach.
There are no test vectors in Solidify. 0-in and friends generate test
vectors that they feed to an internal simulator. For Solidify, you
write 'properties' in their HPL (which is Verilog with 4 additional
operators) to explain how your block works. (Their rule of thumb is
5 to 10 lines of Verilog typically translates to one 'property'. But
the specific metric they gave was one 12 kgate block, 8100 lines RTL
Verilog, had used 156 'properties' -- each 'property' covered 52 lines
of Verilog.) Then you use Solidify own 'properties'-oriented code
coverage utility to find what you're missing. Coverage is a separate
analysis, so it doesn't load down the tool, and it does incrementals.
It then lets you write new 'properties' to cover what you missed.
Currently, it's block level only with a 25 kgate per block capacity.
I liked what I saw. I cannot comment on the tool hands-on as yet,
but I'll keep you informed."
- an anon engineer
( DAC 99 Item 48 ) ----------------------------------------------- [6/99]
"The company 'Formalized Design' ( http://www.formalized.com ) had an
equivalence checker, model checker, switch level abstractor, and
nearly zero marketing effort. You could stand around in front of
these guys for minutes at a time without getting their attention.
Prediction: regardless of technology they will not last long, from
lack of marketing."
- an anon engineer
( DAC 99 Item 49 ) ----------------------------------------------- [6/99]
"BFM or Test Bench generators: Chronology's writes em just like we do,
with full checks. The other one (forgot its name at the moment)
mimics a process approach with lots of forever loops and no use of
fork and join. Both can be down loaded off the net and run free with
no saving. Both have the problem of not understanding that we want
to build these bfms and then move on. They're not too flexible on
how they package BFMs, and they think that you will live in there
little GUI all through verification." ( http://www.chronology.com )
- Peet James of Qualis Design
( DAC 99 Item 50 ) ----------------------------------------------- [6/99]
"Product: Summit's Visual Testbench Rating: 1 Gator (out of 4)
Another product to help designers solve their verification woes.
This tool allows users to graphically capture timing diagrams and
use this data for documentation, generation of test vectors, interact
with the simulator, and capture simulation results. It's somewhat
similar to the Chronology tool as well. I'm not impressed with a
graphical waveform capture tool for million-gate designs since it
lacks concurrency features, random test features, and a much higher
level of abstraction. This tool might be of use to designers who are
doing small CPLD designs and or work mainly using schematic design.
Otherwise, its a waste." ( http://www.summit-design.com )
- an anon engineer
"SynaptiCAD's TestBencherPro:
They are competing against Chronology's Quickbench testbench
generation tool. SynaptiCAD's tool generates a Verilog testbench
from a waveform timing diagram. The waveform editor looked very
simple to use. I was impressed by the ability to load up a waveform,
move one of the input signals and then rerun the simulation to see
what you get. The tool is obviously designed to help debug small
blocks of code. http://www.syncad.com "
- an anon engineer
( DAC 99 Item 51 ) ----------------------------------------------- [6/99]
"Chronology's Quickbench Verification Suite
This is another tool which permits users to define transactions to
stimulate their design. A dataflow language called RAVE (it is based
on Perl) allows users to define complex data structures and randomness
features similar to what is done with Vera and Verisity.
The high-level data sources then generate data sequences which drive
the transactions that interact with the DUT in the sim environment.
RAVE requires a runtime engine which links with the simulator though
the PLI interface. It also utilizes mailbox mechanisms for
synchronization and data storage/manipulation. Internal signals can
be referenced and used as triggers for transactions. A few standard
models are available such as PCI and Utopia which can be used as
examples to help define other models.
In general, this tool seems to be similar in concept to Vera and
Verisity, but it does not seem to have as much capability. Basing
the RAVE language on Perl is one advantage over its competitors since
many designers now have some knowledge of the Perl language."
- an anon engineer
( DAC 99 Item 52 ) ----------------------------------------------- [6/99]
"According to the last data in 1997, Verisity had 84 percent and
VERA had 16 percent of the test bench generator market share."
- Gary Smith, Dataquest EDA Analyst
"Next, I spent some time at Verisity (e.g. Specman Elite). I almost
didn't bother since we already know about Specman. I'm glad I did
visit because they showed a brand new product that couples Specman
with Seamless from Mentor Graphics (more later). This coupling really
extends the idea of Co-Verification. The combination of the two
allows Specman verification code to check both the HDL and the C
firmware all at the same time in Seamless. Watching this blurred the
lines between firmware and HDL." ( http://www.verisity.com )
- an anon engineer
( DAC 99 Item 53 ) ----------------------------------------------- [6/99]
"Demo: Synopsys Intelligent Testbench
This demo combined their new FlexModels library along with Vera to
provide a rapid testbench environment. Few details were provided for
Vera use. Most of the other stuff was pretty basic about using
bus-functional models and models from standard parts so that the
verification team would not have to create these from scratch."
( http://www.synopsys.com/products/vera )
- an anon engineer
( DAC 99 Item 54 ) ----------------------------------------------- [6/99]
MORPH'N POWER RANGERS DAC newbie Summus ( http://www.summusdesign.com )
boasted about its 'PowerEscort' pre- and post- layout power analysis tool
checking IR drop and electromigration problems. Simplex makes the same
claim to power fame. ( http://www.simplex.com ) At the RTL-level, old
guard Sente just introduced their 'WattSmith' RTL power optimizer, which
might bang heads with Synopsys' Power Compiler. And TransEDA has just
jumped into the RTL level power analysis game (playing catch-up w/ Sente
& Synopsys) by announcing their 'PowerSure'. ( http://www.transeda.com )
Veritools and Avanti/interHDL are minor league players in this game, too.
"It seems that Sente is the best. I saw also TransEDA and Veritool's
tools, but they are inferior. Probably the prices are proportional
but this is another issue."
- an anon engineer
"Sente: Power analysis tools. Claimed application to commercial uP
yielded 127 changes, e.g., reduce glitches in datapath. WattSmith:
makes temporary changes to database to estimate effect of change."
- an anon engineer
"Product: Sente Wattwatcher and Wattbots Rating: 3 gators (out of 4)
Wattwatcher provides an RTL and gate-level power estimation tool. I
have used the gate-level tool in the past and found it to be within
about 10% of the actual power dissipation levels. For RTL designs,
the accuracy can vary slightly with a 20-25% range being typical. In
past releases, the methodology for running gate-level and RTL-level
power estimation tasks differed from the user's perspective. These
have now been merged together in a more cohesive interface. The GUI
provides some nice color-coding features of the design hierarchy to
identify "hot-spots" within the design. The newest tool, called
Wattbots, provides intelligent monitoring agents which analyze a
design's power dissipation against a set of 'power rules' and makes
recommendations on how to change the design to reduce power. It even
quantifies the amount of power savings that occur and sorts the list
of recommendations from the highest to lowest impact. Being that
power is often difficult for designers to accurately estimate since
much of it is based on toggle rates and capacitive loads, tools like
Wattwatcher are very useful." ( http://www.sente.com )
- an anon engineer
( DAC 99 Item 55 ) ----------------------------------------------- [6/99]
SKEWED DATA One the more popular new tools 'discovered' at this year's
DAC was Ultima's ClockWise tool. It's a physical-level based tool that
tweaks your clock skew to optimize power and performance.
"Ultima's ClockWise - Ultima has a tool that modifies clock skew to
improve margins by changing branching points and inserting buffers
(about 20% more than normal). It is a point tool used after placement
and before routing. As a side effect, it also reduces peak current
by 30-40%. We ate lunch with one of the guys who wrote the program."
( http://www.ultimatech.com )
- an anon engineer
"Ultima's Clockwise (I thought this was pretty cool):
This is a clock tree synthesis tool. It will use clock skew to try
fixing timing problems. If a flip-flop has tight timing on one side
and relaxed timing on the other the tool will try to move the clock
edge toward the relaxed side.
In the design flow, Clockwise is post-placement and pre-routing.
It takes in DEF, a verilog netlist, .lib, LEF and primetime timing
constraints. It does a routing estimation and then inserts the clock
tree buffers and returns a DEF, a revised netlist, and an SDF."
- an anon engineer
( DAC 99 Item 56 ) ----------------------------------------------- [6/99]
THE BEST DAC PARTY This year, the DAC party that got the most praise was
the Synopsys "House Of Blues" party in the French Quarter. Three very
large rooms of free booze, free food, Madi Gras dancers, and Bo Diddly
singing the blues. (A number of people expected Aart to jump on stage at
any moment because he's a bass guitar blues player. Didn't happen, tho.)
"Our party was on the 4th floor. They came up the elevator and
plastered 'Powered By Exemplar' stickers all over the inside of
the elevator. Then they tried to bribe the wait-staff to wear
their Exemplar shirts. When security chased them out, the Exemplar
people threw the shirts and extra stickers at the guards and ran
laughing. It was just like a fraternity raid on a rival frat."
- Synplicity founder Ken McElvain
"Uh... No names, John. Just a story I know you'd like. We went to
the Denali party at the balcony at the Tricou House on Bourbon
Street. Lots of drinking and loud music. I spent a good part of
the night on the balcony trying to get women on the street below to
flash for my beads. It only worked a two times. It was a good party
until I heard the next morning that there was a live webcam aimed at
the balcony. My wife is an ex-Netscape employee. I still don't know
if she watched me from California that night or not. I can't really
ask her can I? <laughing> Bye."
- an anon phonecall. Tricou's is at http://www.711bourbon.com
I also heard that the Simplex riverboat party got good but limited
reviews by customers because it was too hard to get a ticket or crash.
Boat parties are like that. "Oh, I was just swiming by... mind if I
join you?"
- John Cooley
the ESNUG guy
P.S. If you agree/disagree/have-violent-reactions with anything in this
trip report, please feel free to send me a reply! I love reader feedback!
P.P.S. The 'Mike Santarini' DAC'99 photos are at http://www.deepchip.com
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