Editor's Note: Although being a parent may *age* you quite a few years,
I'm finding being an Uncle actually makes me *younger*. I've just
returned from a family vacation down in Florida with my two brothers'
families and it was: "Do you want to go body surfing again, Uncle John?",
fun soda straw fights in restaurants, following dolphins in our fishing
boat so the kids could see them closer, and family card games at night.
I even have the *physical* symptoms of becoming younger. For the days
when we were in/near/on the ocean, we all put on waterproof SPF 50
sunscreen oil (which I later discovered didn't wash off in the shower
and it clogged the pores of my skin.) By the time I returned to Boston,
I had acne on my arms, face, and back just like I did when I was 16.
And I now have this odd urge to watch MTV's "Real World", stay up all
night, and cop an attitude. Being "Uncle John" is fun! :^)
- John Cooley
the ESNUG guy
( ESNUG 326 Subjects ) -------------------------------------------- [8/99]
Item 1: Customers Royally Pissed About The New Synopsys "Pricing Models"
Item 2: CynApps To Give Away Its Hardware Design Oriented C++ Class Libs
Item 3: ( ESNUG 324 #10 ) Avant!: "No Engineers Lost To Magma In Germany"
Item 4: A Workaround For The Design Compiler / DesignWare Wireload Bug
Item 5: ( ESNUG 325 #11 ) Converting Synopsys DC .lib To Cadence/Ambit ALF
Item 6: Intel Using Mentor's Monet Behavioral Synthesis For Real Designs
Item 7: Damn! Design Compiler (99.05) Won't Give Me *Signed* Comparitors!
Item 8: SynPerl Is No Longer Supported; Use Jeff Solomon's SPP CLI Instead
Item 9: My Nightmare Trying To Use More than 2 Gig of Memory in DC_Shell
Item 10: No, Metastability 'Z' Doesn't Pass Through Disabled Logic Gates
Item 11: ( ESNUG 324 #15 ) Porting Synopsys IPO Into Cadence Design Planner
Item 12: Cadence Example Of Using LINUX As An EDA File-Locking Daemon Server
Item 13: Links To The VIM Homepages And Hewlett-Packard's VERA VIM Syntax
Item 14: ( ESNUG 325 #9 ) A Useful Vim Syntax To View Synopsys Logfiles
Item 15: Help! I Can't Get Synopsys change_names To Change Names Uniformly!
Item 16: ( ESNUG 325 #3 ) Request For Some Sample Hierarchical GDSII files
Item 17: Has Anyone Done Any User Y2K Testing Of The Synopsys UNIX Toolset?
The complete, searchable ESNUG Archive Site is at <http://www.DeepChip.com>
( ESNUG 326 Item 1 ) ---------------------------------------------- [8/99]
Subject: Customers Royally Pissed About The New Synopsys "Pricing Models"
From: [ Rage Against The Machine ]
John -
Please keep me anonymous.
Your loyal readers urgently need your help. Synopsys is totally changing
their licensing business model. They have been rolling out the new model to
most customers over the last few weeks. They had already got feedback from
their biggest customers over the summer. Of course, they first solicited
feedback from Wall Street.
They are moving away from perpetual licenses and toward term-based licenses.
Of course, the prices of perpetual licenses are going up substantially and
discounts are going down! Please solicit feedback from your readers ASAP
about these new plans.
They are leaving a window until August 31, 1999 for users to purchase
licenses uder the old plan. I guess they are hoping for a large influx of
orders before the window closes.
I can't wait to read ESNUG feedback from this.
- [ Rage Against The Machine ]
---- ---- ---- ---- ---- ---- ----
From: Curt Berg <cberg@extremenetworks.com>
Hi John,
Hope you saw that Synopsys is raising prices 20%, and no more discounts for
small guys. This basically means 40% increase, for small companies !!
My first thought: buy SUN stock! It will be a lot cheaper to upgrade
machines then buying Synoopsys tools. 2nd thought: buy Cadence and Avanti
stock, they have a good chance of getting back some market share. 3rd
thought: I'm depressed over Synopsys price tactics.
Why should the end user pay for all their dabbling with tools that end users
don't want. Synopsys puts out something like 8 compilers, when it should
have been one or two. Both Motive and Sunrise were trashed -- what a waste
of money.
I guess Synopsys is the Cisco of EDA industry.
Making $41 M profit on $207 M revenue, not bad in my mind. Anyway asking for
even more might backfire. Looking at the financials, I now understand why
Synopsys service is so bad, $75M in revenue on service, and only spent $19 M.
Soon we are going to see, just like Cisco, Aart de Geus flying around the
country, calling all their big customers, just to stay brand loyal !!
Or is this a good strategy, if I give them more money they can aquire more
companies, to provide users with better technology. But then, if they can't
develop tools themselves with 22% of their revenue, why do they spend all
that money on R&D. Well, here they are much like Cisco again, very little
has come out of their own R&D !
Sorry no more time, have to dust of my Candence and Avanti business cards,
and do some evals.
- Curt Berg, ASIC Manager
Extreme Networks
( ESNUG 326 Item 2 ) ---------------------------------------------- [8/99]
Subject: CynApps To Give Away Its Hardware Design Oriented C++ Class Libs
> To make the first converts, some start-ups offer C/C++ to Verilog/VHDL
> translators like C-Level Design ( http://www.cleveldesign.com ), CynApps
> ( http://www.cynapps.com ), and Frontier ( http://www.frontierd.com ).
> And there's already a company, LavaLogic ( http://www.lavalogic.com )
> that's offering the heretical idea of translating *Java* to synthesizable
> Verilog. These tools all effectively give designers the basic ability to
> create C/C++/Java -> translate 2 Verilog/VHDL -> Design Compiler to gates.
>
> (Not to be left behind, Synopsys in their NDA suites, discussed 'Scenery',
> a way to standardize C/C++ for synthesis purposes and their C-based
> synthesis tool -- which is almost identical to CynApps' Cynlib approach.)
>
> - from the DAC'99 Trip Report
From: John Sanguinetti <jws@cynapps.com>
John,
About the beginning of last year, an old friend (Andy Goodrich) showed me a
C++ class HW library he had written for his own purposes -- he was the
architect at a graphics company. Through a series of experiments I did with
it and discussions with other former Chronologic people, I came to the
conclusion that using C++ as a hardware description language is quite
attractive, and a better idea than creating a new language. It seems that a
number of other people have come to the same conclusion at about the same
time. At any rate, I started the company with Andy Goodrich and Randy Allen
(who was one of the former Chronologic people I had consulted) in the spring
of last year and we are now making good progress in creating a usable design
environment in C++.
Now for the punch line, Why am I sending you this message? Because we are
going to make the class library, Cynlib, available *freely* under an open
source license. Since you are now an official MOVER AND SHAKER in this
industry, I figure that when we make this announcement, people are likely
to ask you your opinion of this move, and I should give you a little
background.
There are a couple of obvious questions about taking this course of action.
What's the advantage to using Cynlib?
There are several advantages to using the free Cynlib class lib and C++ as a
design language. The first, and obvious one, is that you can do a real
top-down elaboration, starting from a pretty high-level design and proceed
all the way to RTL. Another benefit is that you can do your simulation using
nothing besides Cynlib and gcc. Ultimately, I think this will be a huge
benefit, since the simulation is cycle-based, two-state, light-weight, and
quite efficient. Since you can actually run the model at a high level of C++
abstraction, you can do a lot of simulation where it is the fastest, and when
you do get down to RTL, it still goes as fast, or nearly as fast, as the
high-priced simulators.
Why make Cynlib free?
The reason for doing it is that a class library is pretty light-weight. It
is not a trivial piece of code, but once you see the general idea, it's not
too hard to do something similar. So if we tried to sell it, it wouldn't
support a high enough price to be really interesting for us, and it would
encourage people to roll their own. While rolling your own is not easy, it
is just easy enough so that some people would succeed, and we would have a
number of competing dialects, losing the advantages of standardization. So
the answer is that we want to promote Cynlib as a standard, and this is the
best way to do it.
Why make it open source?
There are actually quite a few features that could be added to the class
library, and by opening the source up, other people can implement them, so
we are not the bottleneck in the development of the library. The other
reason is that this should give people more confidence when using a new
design method, since they can actually look at the source to see how it
works.
How is CynApps going to make money on this?
The short answer is we don't know. The longer answer is that we are making
other products that are needed to effectively design in C++. Particularly,
you need to be able to translate the C++ code into something Design
Compiler can take as input, and that is the product we expect to make our
money on. So if lots of people use Cynlib, we will have a market to sell
our Cynthesizer into. I should also mention that we have a couple of other
products, including a translator from Verilog to C++ (works with
synthesizable Verilog code) and a macro language which turns C++/Cynlib
into a Verilog dialect of C.
Cynlib will be up at <http://www.cynapps.com> on Wednesday, Sept. 1st, free
for the taking.
- John Sanguinetti, CEO
CynApps, Inc. Santa Clara, CA
( ESNUG 326 Item 3 ) ---------------------------------------------- [8/99]
Subject: ( ESNUG 324 #10 ) Avant!: "No Engineers Lost To Magma In Germany"
> In Germany, Avant! consultants are leaving the company. A big deal of them
> heads for Magma. So Avant! has a problem in offering expert support.
> To my knowledge, Magma has impelemented a new approach to layout which so
> far other vendors only promise.
>
> - Klaus Vongehr
> Infineon/Siemens Munich, Germany
From: Graham Curren <graham@avanticorp.com>
Hi John,
Contrary to the posting by Klaus Vongehr, we have not had any engineers leave
for Magma in Germany. Let me set the record straight:
- some engineers left the UK office for Magma early this year.
- two engineers left the German office, but neither has gone to Magma.
- so far this year we have roughly doubled the number of AEs in Europe.
I need to increase the number of engineers still further in line with our
business and am always looking for good, self-motivated engineers, located
almost anywhere within Europe. If anyone is interested in working for the
fastest growing and most profitable EDA company, then please get in contact
with any of our European offices for details.
- Graham Curren, Technical Manager ( Europe )
Avant! Corporation Theale, Berkshire, UK
( ESNUG 326 Item 4 ) ---------------------------------------------- [8/99]
From: Robert Wiegand <rwiegand@ensoniq.com>
Subject: A Workaround For The Design Compiler / DesignWare Wireload Bug
Hi John,
I've found that Design Compiler generated hierarchy (i.e. DesignWare) gets
the wrong wireload model. I've run into this using 1998.98-1, but I checked
the problem with 1998.02-2 and 1999.05 and got the same results.
When using enclosed wireload models, generated DesignWare hierarchy gets
the wrong wireload. If there is a default_wire_load attribute in the
library, that wireload is used. If there is no default_wire_load attribute
set, NO wireload is used. The same behavior occurs regardless of the
auto_wire_load_selection value. I generally ungroup DesignWare hierarchy
into the design after the compile is finished, but I would like the
DesignWare to have the same wireload as the parent design during the
compile. This can be accompilshed using "top" instead of "enclosed" mode,
but if there are subdesigns under this block with different wireloads,
they will be forced to use the parent block wireload instead.
Before arriving at a workaround, I tried forcing the generated hierarchy
to exist before the compile using replace_synthetic or compile -no_map so I
could set the wireload before compiling. The compile, however, generated
"_1" versions of the DesignWare designs, gave them the incorrect wireload
as described above, and threw out the "_0" versions with the correct
wireloads.
The workaround:
/* create a new variable, current_wireload */
current_wireload = [appropriate wireload for design]
set_wire_load -library wireload_library -mode wireload_mode current_wireload
/* wireload_library is the name of the library containing the wireload
info, wireload_mode is the mode, enclosed in this case. */
/* set the library default wireload to be current_wireload */
supress_errors = supress_errors + {UID-101}
get_attribute wireload_library default_wire_load
if (dc_shell_status) {
set_attribute wireload_library default_wire_load current_wireload
} else {
set_attribute wireload_library default_wire_load current_wireload -type string
}
supress_errors = supress_errors - {UID-101}
Any compile generated hierarchy now takes on the default_wire_load that
matches the parent design.
- Bob B. Wiegand
Ensoniq Corp. Malvern,PA
( ESNUG 326 Item 5 ) ---------------------------------------------- [8/99]
Subject: ( ESNUG 325 #11 ) Converting Synopsys DC .lib To Cadence/Ambit ALF
>> I'm switching over from Synopsys Design Compiler to Ambit BuildGates. I
>> have some uncompiled ASCII .lib files from Synopsys. I don't know where
>> to start looking to figure out how to convert these to Ambit ALF library
>> files. I'm not even sure what program is used to do it.
>>
>> - David Rogoff
>
> From: Jeroen Vermeeren <Jeroen.Vermeeren@nym.sc.philips.com>
>
> Hi David,
>
> The trick is not to create ALF files but TLF files. Ambit can read CTLF
> files as well as ALF files. Use "syn2tlf" for conversion of synopsys .lib
> to TLF. Use "tlfc" for conversion from tlf to ctlf (to compile the tlf).
>
> - Jeroen Vermeeren
> Philips Semiconductors
From: Ori Chalak <ori.chalak@analog.com>
I use ALF, and found no problem with it. Ambit's "libcompile" program
correctly converts from uncompiled ASCII .lib files to .alf . Do you
know if there is an advantage to go through CTLF ?
- Ori Chalak
Analog Devices Israel
---- ---- ---- ---- ---- ---- ----
From: Joe Barz <Joe.Barz@motorola.com>
John,
Ambit provides a utility (libcompile) that will convert the .lib to a .alf
file. It's in the $AMBIT_DIR/bin directory. Good luck.
- Joe Barz
Motorola
---- ---- ---- ---- ---- ---- ----
From: Tom David <tomd@silogix.com>
Hi John,
Use : libcompile <inputfile> <outputfile>
where input file is your .lib file and output file is the .alf file. This
will translate the .lib files to .alf files for Ambit... libcompile is
shipped free (well, I'm sure the price is built into the pricing for
BuildGates) with every copy of Ambit.
- Tom David
SiLogiX, LLC
---- ---- ---- ---- ---- ---- ----
From: Jay McDougal <jaym@hpcvcdt.cv.hp.com>
Hi, John,
There is a utility that ships with BuildGates that will compile a .lib file
into a .alf. It is called libcompile and can be found in the bin directory
under the BuildGates install.
- Jay McDougal
Hewlett-Packard
( ESNUG 326 Item 6 ) ---------------------------------------------- [8/99]
Subject: Intel Using Mentor's Monet Behavioral Synthesis For Real Designs
> Two years ago, at DAC'97, behavioral tools seemed to be the wave of the
> future at that time. A number of companies there presented some sort of
> behavioral this or behavioral that, with the leader being the Synopsys
> Behavioral Compiler (BC). But, what was even more interesting at that DAC
> was a true architectural exploration tool from Mentor called 'Monet' that
> rode on top of BC. Monet was a cool tool that looked really neat in its
> demo; it ran quickly and didn't have 1/100th of the painful complexity
> that awkward Behavioral Compiler had. If I had written a DAC Trip Report
> that year, I would have given Monet first prize.
>
> - John Cooley in "The $86,250 Question"
From: [ The Walls Have Ears ]
John,
I just read your "The $86,250 question" column in this week's EE Times. I
won't say how I know this, but I know that the server chipset group for
Intel in Portland is using Monet as a front-end to get synthesizable VHDL
for the chipset to go with McKinley. I also know that they are still in
the coding and early behavioral debug stage. Just FYI to add to your quest
for info. (I'd like to keep this info as being from an anon source, if you
don't mind.)
- [ The Walls Have Ears ]
( ESNUG 326 Item 7 ) ---------------------------------------------- [8/99]
From: Menno Spijker <menno_spijker@mitel.com>
Subject: Damn! Design Compiler (99.05) Won't Give Me *Signed* Comparitors!
Hi John,
I'm having trouble synthesizing signed arithmatic from Verilog. I thought
converting everything to integers would do the trick since integers are
defined in Verilog as 32-bit signed values. However Design Compiler (99.05)
creates unsigned comparators when I compare two integers. Of course, I can
instantiate a signed DesignWare comparator, but I hate to do that since that
makes the Verilog code tool dependent. The thing is that the Synopsys VCS
simulator handles integers correctly as signed. When I check the HDL
Compiler for Verilog Reference Manual, it says on page 4-6; "All comparisons
assume unsigned quantities", apparently regardless if it compares integers
or regs. How do I force DC to synthesize a *signed* comparator without
instantiating or writing my own comparison functions?
- Menno Spijker
Mitel Semiconductor Kanata, Canada
( ESNUG 326 Item 8 ) ---------------------------------------------- [8/99]
From: "Tom Harrington" <tharring@ford.com>
Subject: SynPerl Is No Longer Supported; Use Jeff Solomon's SPP CLI Instead
John,
I'm leaving my job at Ford effective 8/20. I don't have a new email address
to add, because I'm not going to be doing Synopsys-related work anymore.
Greg Mann is also leaving Ford to become a pastor of a church. ESNUG has
been a great list, thanks a lot for your efforts in running it.
One final note before we're out the door --
I don't know how many people are currently using Synperl, but with our
changes of careers, we don't plan on updating it any more. I would
recommend that anyone who wants to combine Perl and Synopsys take a look at
Jeff Solomon's SPP, at <http://www.stanford.edu/~jsolomon/SPP/>. Jeff was
obviously thinking along the same lines as me when he wrote SPP, but he
took it a step further with a really cool Perl command-line interface to
Synopsys tools. Jeff says that he plans to continue supporting SPP, so I
encourage everyone to give it a look.
The most recent (and final) version of Synperl can be found at
<ftp://ftp.rmi.net/pub2/tph/synperl/synperl.tar.Z>. It still works,
but it's a dead project at this point. If anyone's interested in
taking up development on their own, they can contact me at tph@acm.org.
But with SPP around it's probably not worth the time, unless you want
to take it in a direction that's very different from SPP...
Best of luck to you and everyone in ESNUG!
- Tom Harrington
Ford Microelectronics Colorado Springs, CO
[ Editor's Note: I was bummed to read this. Tom & Greg did a lot of good
bug reporting, etc., over the years. They'll be missed. :^( - John ]
( ESNUG 326 Item 9 ) ---------------------------------------------- [8/99]
From: Don Monroe <don_monroe@tenornetworks.com>
Subject: My Nightmare Trying To Use More than 2 Gig of Memory in DC_Shell
Hi, John,
Does anybody know ALL the requirements to get dcshell to not crash when it
wants to allocate more than 2 Gigabytes of memory? Running on Solaris 2.7
with 'datasize' unlimited. Does the LD_LIBRARY_PATH environment variable
have to contain /usr/lib/sparcv9?
- Don Monroe
Tenor Networks Acton, MA
( ESNUG 326 Item 10 ) --------------------------------------------- [8/99]
Subject: No, Metastability 'Z' Doesn't Pass Through Disabled Logic Gates
> Will metastabily propagate through logic gates even when they are disabled?
> That is, assume I have an AND gate, with two inputs A & B. Input A is a
> signal with a posibility of being in metastable state. (Say, it is the
> output of a flip flop which has an asynchronous input). Now if I make
> input B at logic zero, during the possible period of A being at metastable
> state, what will be the output of this AND gate? Or the question is as
> simple as, if one input of an AND gate is a metastable input and other
> input is a logic zero, what will be its output? What if it is an OR gate
> with the other input at logic one?
>
> - Rejeesh
From: Jari Mutikainen <jari.mutikainen@tellabs.fi>
No Rajeesh, metastability can't propagate like that through disabled gates.
If you have a '0' at one input to an AND, the output of it is going to be
'0' regardless of the other input(s) of that gate. Similarly you can can
count on the output of a OR-gate being '1' as soon as you have one '1' at
some of the inputs.
- Jari Mutikainen
Tellabs Finland
---- ---- ---- ---- ---- ---- ----
From: Kuba Smieciuszewski <kuba@fnc.fujitsu.com>
AND gate A B OUTPUT
H H H
L X L
X L L
OR gate A B OUTPUT
L L L
H X H
X H H
- Kuba Smieciuszewski
Fujitsu Network Communications, INC
( ESNUG 326 Item 11 ) --------------------------------------------- [8/99]
Subject: ( ESNUG 324 #15 ) Porting Synopsys IPO Into Cadence Design Planner
>> A customer is running Cadence's Design Planner (HLD) that uses some
>> "synopsys.ipo" file that is supposed to contain information about the
>> changes made after synopsys in-place optimization is done. Does anyone
>> know how to generate this file from synopsys?
>>
>> - Robert K. Yu
>> CadFarm, Inc. Newark, CA
>
>
> From: Jean-Marc Calvez <jean-marc.calvez@st.com>
>
> Your customer probably used:
>
> reoptimize_design_changed_list_file_name = "synopsys.ipo"
>
> in his/her script. Check what this variable does exactly in the Synopsys
> online documentation...
>
> - Jean-Marc Calvez
> STMicroelectronics Grenoble, France
From: NUKALA RAVIKANTH <ravikanth@msemi.com>
Hi, John,
In Synopsys, when IPO is done with the reoptimize_design -in_place, if the
following variable is set to a file name, the command will output a list of
design modifications/additions to the file. The commands will use the file
to store the list of those cells which changed and those cells and nets which
were added. Even the command compile -in_place uses this variable to store
the changes in a file.
The variable is :
reoptimize_design_changed_list_file_name = swap.cells.log
I hope this helps!!!
- Nukala Ravikanth
Meridian Semiconductor
( ESNUG 326 Item 12 ) --------------------------------------------- [8/99]
Subject: Cadence Example Of Using LINUX As An EDA File-Locking Daemon Server
> Does anyone know if the Cadence cdsd file-locking daemon runs on Linux,
> i.e. is it possible to use a Linux (RedHat 6) file server when we run
> Cadence on our Suns?
>
> - Philippe Duchene
> Snake Tech
From: Martin Meserve <martin.e.meserve@lmco.com>
Philippe,
That should be no problem at all. The main important factor is that the
server adhere to proper NFS protocol. As long as it does that, no app cares
where you store it. I am not a Linux person, but from what I know about it,
it does NFS just fine.
One of my file servers is a 48 GByte file system from Falcon. It's split
into three partitions, 2 - 12 GBytes and 1 - 24 GBytes. All of our apps are
stored on the 24 GByte partition and NFS mounted to our Sun workstations and
compute servers. The file server itself is DOS based PC. I have been
storing my Cadence (or Valid as it use to be) installs on remote file
systems for over 10 years.
Some of our applications must support multiple Operating Systems (SunOS 4.x
and SunOS 5.x) and multiple platforms (Sun, SGI, HP). If you get the right
software, you can even store PC applications. A generic file server, IMHO,
is the only way to go.
- Martin E. Meserve
Lockheed Martin M&DS - Reconnaissance Systems
---- ---- ---- ---- ---- ---- ----
From: phz@cadence.com (Pete Zakel)
No, that's not true. Cadence programs need to lock the file locally (on the
server the file system is on), which is why cdsd normally DOES have to run
on the file server.
But, you can setup a proxy server, and I believe that will work with Linux.
Sorry, I don't know the details, someone else will have to post that.
- Pete Zakel
Cadence Design Systems
---- ---- ---- ---- ---- ---- ----
From: Martin Meserve <martin.e.meserve@lmco.com>
Maybe I explained it poorly, or someone has missed the point, but it makes no
difference whether the release is stored on a local file system or a remote
file system, that is NFS mounted. As far as file locking, this is fully
supported on remote mounts. A proxy server is not necessary, but can be
used. Back when Cadence operated under "sunview" (it was Valid then and the
X-Window system wasn't available) the release could be installed on any
remote NFS mounted file system and run on any other system. It has never
been necessary to run Cadence programs on the same server that the file
system it was installed on.
This whole thing has nothing to do with Cadence, but is an operating system
issue. If the machine you are using can see the remote file system, through
a NFS mount or whatever, you can run the application. If you can't, then
you are doing something wrong, and I would be more than glad to help.
- Martin E. Meserve
Lockheed Martin M&DS - Reconnaissance Systems
---- ---- ---- ---- ---- ---- ----
From: "Steve Potter" <spotter@cadence.com>
The dfII tools do file locking using the Cadence locking daemon 'cdsd'.
There is no cdsd for Linux, but the Linux filesystem can still be used as a
fileserver for dfII data by setting up a "proxy" file which tells the dfII
applications where to find a cdsd that is serving that filesystem. Setting
up the proxy file is described in the 'cdsd' chapters of the 'Configuration
Guide'. Just do a search for 'cdsd' in Cadence OpenBook.
- Steve Potter
Cadence Design Systems
---- ---- ---- ---- ---- ---- ----
From: atl@cray.com (Tony Laundrie)
Cdsd is needed to maintain integrity on the data in Cadence libraries, not
the executables and install path. I, too, would like to see a Linux port of
this program vs. setting up a proxy.
- Tony Laundrie
Cray Computers
( ESNUG 326 Item 13 ) --------------------------------------------- [8/99]
From: Beth Leonard <beth@cdc.hp.com>
Subject: Links To The VIM Homepages And Hewlett-Packard's VERA VIM Syntax
Hi, John,
For those who don't know what VIM is, it's a vi-like editor with color
syntax highlighting. More information about vim is available from:
<http://www.vim.org/>
More information about maintaining/tweaking syntax files is located at:
<http://www.vim.org/howto/synmain.html>
I've modified a vim syntax file to cover the Vera.
Several groups within HP are using this file, and I'd like to make it
generally available to the ESNUG community.
- Beth Leonard
Hewlett-Packard
" Vim syntax file
" Language: Vera
" Maintainer: Beth Leonard <beth@cdc.hp.com>
" Last Update: Tuesday June 29, 1999
"
" Vera is a Hardware Verification Language sold by Synopsys.
"
" History:
" Mark Madsen leveraged this from Verilog syntax file
" Beth Leonard added some enhancements
syn clear
" A bunch of useful Vera keywords
syn keyword veraStatement all any async begin bind bind_var
syn keyword veraStatement bit break breakpoint case class continue
syn keyword veraStatement coverage_block default depth else end enum event
syn keyword veraStatement extern extends for fork function if illegal_state
syn keyword veraStatement illegal_transation illegal_self_transition inout
syn keyword veraStatement input integer interface
syn keyword veraStatement join local negedge new
syn keyword veraStatement none null output port posedge program reg
syn keyword veraStatement repeat return shadow soft state static string
syn keyword veraStatement super task terminate this trans typedef
syn keyword veraStatement var vector verilog_node verilog_task
syn keyword veraStatement vhdl_node vhdl_task virtual
syn keyword veraStatement void while with CLOCK
syn keyword veraLabel begin end fork join
syn keyword veraConditional if else case default
syn keyword veraRepeat forever repeat while for
" predefined vera tasks
syn keyword veraTask alloc call_func call_task cast_assign
syn keyword veraTask close_conn delay error error_mode exit
syn keyword veraTask fclose fflush flag fopen fprintf freadb
syn keyword veraTask freadh freadstr get_bind get_bind_id
syn keyword veraTask get_conn_err get_cycle get_plus_arg
syn keyword veraTask get_systime get_time mailbox_get
syn keyword veraTask mailbox_put make_client make_server
syn keyword veraTask printf rand48 random region_enter
syn keyword veraTask region_exit rewind semaphore_get
syn keyword veraTask semaphore_put sprintf sscanf stop
syn keyword veraTask sync timeout trace trigger unit_delay
syn keyword veraTask up_connections urand48 urandom vsv_call_func
syn keyword veraTask vsv_call_task vsv_close_conn vsv_get_conn_err
syn keyword veraTask vsv_make_client vsv_make_server
syn keyword veraTask vsv_up_connections vsv_wait_for_done
syn keyword veraTask vsv_wait_for_input wait_child wait_var
syn keyword veraTodo contained TODO
syn match veraOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"
syn region veraComment start="/\*" end="\*/"
syn match veraComment "//.*"
syn match veraGlobal "`[a-zA-Z0-9_]\+\>"
syn match veraGlobal "$[a-zA-Z0-9_]\+\>"
syn match veraConstant "\<[A-Z][A-Z0-9_]\+\>"
syn match veraNumber "\(\<[0-9]\+\|\)'[bdh][0-9a-fxzA-F]\+\>"
syn match veraNumber "\<[+-]\=[0-9]\+\>"
syn region veraString start=+"+ end=+"+
" predefined vera constants
syn keyword veraConst stderr stdin stdout ALL ANY BAD_STATE
syn keyword veraConst BAD_TRANS CHECK CHGEDGE CLEAR CROSS
syn keyword veraConst CROSS_TRANS DEBUG DELETE EC_ARRAYX
syn keyword veraConst EC_NEXPECT EC_RETURN EC_RHNTMOUT
syn keyword veraConst EC_SCONFLICT EC_SEMTMOUT EC_SEXPECT
syn keyword veraConst EC_SFULLEXPECT EC_SNEXTPECT EC_USERET
syn keyword veraConst EQ EVENT FIRST GE GOAL GT LIC_EXIT
syn keyword veraConst LIC_PRERR LIC_PRWARN LIC_WAIT LO LOAD
syn keyword veraConst LOW LT MAILBOX NAME NEGEDGE NEXT
syn keyword veraConst NO_OVERLAP NO_WAIT NUM ORDER POSEDGE
syn keyword veraConst PROGRAM RAWIN REGION REPORT SAVE
syn keyword veraConst SEMAPHORE SET SILENT STATE STR
syn keyword veraConst STR_ERR_OUT_OF_RANGE
syn keyword veraConst STR_ERR_REGEXP_SYNTAX SUM
syn keyword veraConst EC_CODE_END EC_CONFLICT EC_EXPECT
syn keyword veraConst EC_FULLEXPECT EC_MBXTMOUT HAND_SHAKE HI
syn keyword veraConst HIGH HNUM LE NUM_BIN OFF ON ONE_BLAST
syn keyword veraConst ONE_SHOT TRANS VERBOSE WAIT
"copied these from the c.vim file and modified
syn region veraPreCondit start="^\s*#\s*\(if\>\|ifdef\>\|ifndef\>\|elif\>\|else\>\|endif\>\)" skip="\\$" end="$" contains=veraComment,veraString,veraCharacter,veraNumber
syn region veraIncluded contained start=+"+ skip=+\\\\\|\\"+ end=+"+
syn match veraIncluded contained "<[^>]*>"
syn match veraInclude "^\s*#\s*include\>\s*["<]" contains=veraIncluded
"syn match veraLineSkip "\\$"
syn region veraDefine start="^\s*#\s*\(define\>\|undef\>\)" skip="\\$" end="$" contains=ALLBUT,veraPreCondit,veraIncluded,veraInclude,veraDefine
syn region veraPreProc start="^\s*#\s*\(pragma\>\|line\>\|warning\>\|warn\>\|error\>\)" skip="\\$" end="$" contains=ALLBUT,veraPreCondit,veraIncluded,veraInclude,veraDefine
"Modify the following as needed. The trade-off is performance versus
"functionality.
syn sync lines=50
if !exists("did_vera_syntax_inits")
let did_vera_syntax_inits = 1
" The default methods for highlighting. Can be overridden later
hi link veraCharacter Character
hi link veraConditional Conditional
hi link veraRepeat Repeat
hi link veraString String
hi link veraTodo Todo
hi link veraDefine Macro
hi link veraInclude Include
hi link veraIncluded cString
hi link veraComment Comment
hi link veraConstant Todo
hi link veraLabel PreCondit
hi link veraPreCondit PreCondit
hi link veraNumber Special
hi link veraOperator Type
hi link veraStatement Statement
hi link veraGlobal String
hi link veraTask Statement
hi link veraConst Statement
endif
let b:current_syntax = "vera"
" vim: ts=8
( ESNUG 326 Item 14 ) --------------------------------------------- [8/99]
Subject: ( ESNUG 325 #9 ) A Useful Vim Syntax To View Synopsys Logfiles
> I started playing with VIM not long ago and wanted to pretty up what I was
> seeing in my Synopsys scripts, so I started to generate a rudimentary .vim
> syntax file for Synopsys tools. ...
>
> - Gzim Derti
> Intrinsix Corp. Rochester, NY
From: Peter Kamphuis <kamphuis@hl.siemens.de>
Hi John,
I want to thank Gzim Derti for providing us with a basic dc_shell VIM syntax
file. I'm a VIM fan, too, and have asked for this a year ago already and
haven't had the time to set up something by myself. I have been using the
C-mode as workaround up to now.
A few comments to Gzim's syntax file. I added the following lines:
syn keyword synopStatement which
syn region cString start=+"+ end=+"+
and deleted the "^" character from following line
syn region cComment start="^/\*" end="\*/" contains=cTodo,cSpaceError
Maybe I'll find the time (at home) to improve things, add a syntax file for
the new DC Tcl mode, etc. Of course, I'll share this with the ESNUG
community.
Some time ago I created a simple VIM syntax file for reviewing Synopsys log
files. I think this might be useful for other people, too. I've added the
code below:
" Vim syntax file for (dc_shell) log files
" by Peter Kamphuis, Infineon Technologies AG, Munich
" Remove any old syntax stuff
syntax clear
" Message code
syntax match logCode "\s([A-Z]\+-[0-9]\+)\s$"
" Errors
syntax match lError "^\s*Error:\s.\+)" contains=llError
syntax match llError "^\s*Error:\s" nextgroup=logError
syntax region logError start="." matchgroup=logCode end="\s([A-Z]\+-[0-9]\+)" contained
" Warnings
syntax match lWarning "^\s*Warning:\s.\+)" contains=llWarning
syntax match llWarning "^\s*Warning:\s" nextgroup=logWarning
syntax region logWarning start="." matchgroup=logCode end="\s([A-Z]\+-[0-9]\+)" contained
" Informations
syntax match lInfo "^\s*Information:\s.\+)" contains=llInfo
syntax match llInfo "^\s*Information:\s" nextgroup=logInfo
syntax region logInfo start="." matchgroup=logCode end="\s([A-Z]\+-[0-9]\+)" contained
" Comments
syntax region logComment start="/\*" end="*\/"
if !exists("did_log_syntax_inits")
let did_log_syntax_inits = 1
" Message code
highlight logCode term=NONE ctermfg=DarkRed
" Message
highlight logError term=reverse ctermfg=Red
highlight logWarning term=bold ctermfg=DarkMagenta
highlight logInfo term=underline ctermfg=DarkBlue
" The words Error: Warning: Information:
highlight llError term=NONE ctermfg=Red
highlight llWarning term=NONE ctermfg=Red
highlight llInfo term=NONE ctermfg=DarkBlue
" Comment
highlight link logComment Comment
endif
let b:current_syntax = "log"
" EoF
Note that the color information included is a personal touch that can be
changed, of course. Do not forget to add something like the following line
to your VIM setup file.
au BufNewFile,BufRead *.log* so $VIM/syntax/log.vim
Best regards,
- Peter Kamphuis
Infineon (Siemens) Technologies AG Munich, Germany
( ESNUG 326 Item 15 ) --------------------------------------------- [8/99]
From: Andrew Maccormack <andrewm@bristol.st.com>
Subject: Help! I Can't Get Synopsys change_names To Change Names Uniformly!
John,
I have a .db file that I have inherited from another source with instances
and nets with the same names. Since this causes problems (i.e. in our
VHDL netlist) I used the -special sge_vhdl name rule to collapse the name
spaces and eliminate any double underscores, etc. However, I notice that
the Synopsys change_names command collapses the name space when DETECTING
clashes, but not when choosing new unique names, so I had this:
Inst name Net name New net name (after change_names)
U U Ub
Ub Ub Ubb
Ubb Ubb Ubbb
So it worked out that it needed to change the names, and the new net names
don't clash with other net names, but they do still clash with the instance
names.
So I had to run change_names twice more to get rid of all the problems:
Inst name Net name New #1 New #2 New #3 (unique at last)
U U Ub Ubb Ubbb
Ub Ub Ubb Ubbb Ubbbb
Ubb Ubb Ubbb Ubbbb Ubbbbb
This seems a general problem, (ie checking clashes at beginning but not end)
because I had a net called some_reg[5]_q that got changed to some_reg_5__q
which broke the double underscore rule.
The man page doesn't say what the dc_shell_status is for this command, so I
don't know if I can have a script like:
change_names
while (dc_shell_status > 0) {
change_names
}
Does anyone know anything about this problem?
- Andrew R MacCormack
STMicroelectronics
( ESNUG 326 Item 16 ) --------------------------------------------- [8/99]
Subject: ( ESNUG 325 #3 ) Request For Some Sample Hierarchical GDSII files
> I would greatly appreciate if someone can send me some GDSII files which
> contain data in a hierarchical manner. That is, it should contain say some
> circuit elements which are replicated some number of times in the X and Y
> directions. Presently, I have GDSII files which are in the flat format and
> am interested in trying to deal with GDSII files which contain data in the
> hierarchical format.
>
> - Jayesh Laddha
> Auburn University
From: Mariusz Niewczas <mn@ece.cmu.edu>
Jayesh, Try:
ftp://ftp.ece.cmu.edu/cad/cmu56k.cif.Z
this is a nice benchmark (signal processor) I use as a first try on layout
processing applications I write. (You can convert it to GDS if you need
magic, DFII or what have you.)
- Mariusz Niewczas, a post-doc researcher
(On leave from Warsaw University of Technology, Warsaw, Poland)
Carnegie Mellon University Pittsburgh, PA
( ESNUG 326 Item 17 ) --------------------------------------------- [8/99]
From: "Steve Gonzales" <GonzaSA@LOUISVILLE.STORTEK.COM>
Subject: Has Anyone Done Any User Y2K Testing Of The Synopsys UNIX Toolset?
John,
Do you know of any archives or where I can get some info on Y2K testing of
Synopsys products done by users rather than from Synopsys? There didn't seem
to be much in the way of Y2K info in <http://www.deepchip.com> . We would
be very interested to learn more about your own or anybody's Unix + Synopsys
Y2K approach.
- Steve Gonzales
Storage Technology Inc.
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